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/openbmc/u-boot/arch/x86/lib/
H A Dzimage.c33 * relative to setup_base (which is 0x90000 currently)
35 * 0x0000-0x7FFF Real mode kernel
36 * 0x8000-0x8FFF Stack and heap
37 * 0x9000-0x90FF Kernel command line
39 #define DEFAULT_SETUP_BASE 0x90000
40 #define COMMAND_LINE_OFFSET 0x9000
41 #define HEAP_END_OFFSET 0x8e00
49 command_line[0] = '\0'; in build_command_line()
76 "(found 0x%04x, expected 0x%04x)\n", in kernel_magic_ok()
78 return 0; in kernel_magic_ok()
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dmcu.h12 #define MT_MCU_CPU_CTL 0x0704
13 #define MT_MCU_CLOCK_CTL 0x0708
14 #define MT_MCU_PCIE_REMAP_BASE1 0x0740
15 #define MT_MCU_PCIE_REMAP_BASE2 0x0744
16 #define MT_MCU_PCIE_REMAP_BASE3 0x0748
18 #define MT_MCU_ROM_PATCH_OFFSET 0x80000
19 #define MT_MCU_ROM_PATCH_ADDR 0x90000
21 #define MT_MCU_ILM_OFFSET 0x80000
23 #define MT_MCU_DLM_OFFSET 0x100000
24 #define MT_MCU_DLM_ADDR 0x90000
[all …]
/openbmc/linux/Documentation/arch/x86/
H A Dboot.rst28 Protocol 2.02 (Kernel 2.4.0-test3-pre3) New command line protocol.
99 0A0000 +------------------------+
121 0x100000 ("high memory"), and the kernel real-mode block (boot sector,
123 0x10000 and end of low memory. Unfortunately, in protocols 2.00 and
124 2.01 the 0x90000+ memory range is still used internally by the kernel;
139 0x90000 segment, the boot loader should make sure not to use memory
140 above the 0x9A000 point; too many BIOSes will break above that point.
149 0A0000 +------------------------+
180 following header at offset 0x01f1. The real-mode code can total up to
195 01FE/2 ALL boot_flag 0xAA55 magic number
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx8qxp-lpcg.h11 #define LSIO_PWM_0_LPCG 0x00000
12 #define LSIO_PWM_1_LPCG 0x10000
13 #define LSIO_PWM_2_LPCG 0x20000
14 #define LSIO_PWM_3_LPCG 0x30000
15 #define LSIO_PWM_4_LPCG 0x40000
16 #define LSIO_PWM_5_LPCG 0x50000
17 #define LSIO_PWM_6_LPCG 0x60000
18 #define LSIO_PWM_7_LPCG 0x70000
19 #define LSIO_GPIO_0_LPCG 0x80000
20 #define LSIO_GPIO_1_LPCG 0x90000
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dkirkwood-openblocks_a6.dts13 reg = <0x00000000 0x20000000>;
40 reg = <0x30>;
45 pinctrl-0 = <&pmx_dip_switches>;
95 pinctrl-0 = <&pmx_leds>;
116 pinctrl-0 = <&pmx_gpio_init>;
119 #size-cells = <0>;
133 partition@0 {
135 reg = <0x0 0x90000>;
140 reg = <0x90000 0x44000>;
145 reg = <0xd4000 0x20000>;
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx3x.h36 #define MX3x_L2CC_BASE_ADDR 0x30000000
42 #define MX3x_AIPS1_BASE_ADDR 0x43f00000
44 #define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
45 #define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
46 #define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
47 #define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
48 #define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
49 #define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
50 #define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
51 #define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/security/tpm/
H A Dtpm_tis_mmio.txt15 - reg: The location of the MMIO registers, should be at least 0x5000 bytes
22 reg = <0x90000 0x5000>;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,msm8996-apcc.yaml13 Qualcomm CPU clock controller for MSM8996 CPUs, clock 0 is for Power cluster
50 reg = <0x6400000 0x90000>;
H A Dqcom,gcc-msm8994.yaml48 reg = <0x00300000 0x90000>;
H A Dqcom,gcc-msm8996.yaml29 - description: PCIe 0 PIPE clock (optional)
33 - description: UFS RX symbol 0 clock (optional)
35 - description: UFS TX symbol 0 clock (optional)
66 reg = <0x300000 0x90000>;
H A Dqcom,gcc-msm8916.yaml33 - description: DSI phy instance 0 dsi clock
34 - description: DSI phy instance 0 byte clock
64 reg = <0x300000 0x90000>;
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dqoriq-fman3-0-10g-0.dtsi3 * QorIQ FMan v3 10g port #0 device tree
11 cell-index = <0x10>;
13 reg = <0x90000 0x1000>;
18 cell-index = <0x30>;
20 reg = <0xb0000 0x1000>;
25 cell-index = <0x8>;
27 reg = <0xf0000 0x1000>;
34 #size-cells = <0>;
36 reg = <0xf1000 0x1000>;
38 pcsphy6: ethernet-phy@0 {
[all …]
H A Dqoriq-bman-portals.dtsi14 bman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
26 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
32 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
38 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
44 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
50 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
56 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
62 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
68 reg = <0x80000 0x4000>, <0x4080000 0x4000>;
[all …]
H A Dqoriq-qman-portals.dtsi14 qportal0: qman-portal@0 {
20 reg = <0x0 0x4000>, <0x4000000 0x4000>;
22 cell-index = <0>;
27 reg = <0x10000 0x4000>, <0x4010000 0x4000>;
34 reg = <0x20000 0x4000>, <0x4020000 0x4000>;
41 reg = <0x30000 0x4000>, <0x4030000 0x4000>;
48 reg = <0x40000 0x4000>, <0x4040000 0x4000>;
55 reg = <0x50000 0x4000>, <0x4050000 0x4000>;
62 reg = <0x60000 0x4000>, <0x4060000 0x4000>;
69 reg = <0x70000 0x4000>, <0x4070000 0x4000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/crypto/
H A Dmarvell-cesa.txt37 reg = <0x90000 0x10000>;
43 marvell,crypto-sram-size = <0x600>;
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqcom,ipq4019-mdio.yaml29 const: 0
79 #size-cells = <0>;
81 reg = <0x90000 0x64>;
83 ethphy0: ethernet-phy@0 {
84 reg = <0>;
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am65-main.dtsi16 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
17 <0x00 0x01880000 0x00 0x90000>; /* GICR */
26 reg = <0x00 0x01820000 0x00 0x10000>;
36 reg = <0x00 0x32c00000 0x00 0x100000>,
37 <0x00 0x32400000 0x00 0x100000>,
38 <0x00 0x32800000 0x00 0x100000>;
45 reg = <0x00 0x02800000 0x00 0x100>;
55 reg = <0x00 0x02810000 0x00 0x100>;
65 reg = <0x00 0x02820000 0x00 0x100>;
H A Dkirkwood-6281.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
H A Dkirkwood-6192.dtsi12 bus-range = <0x00 0xff>;
15 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
16 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
17 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
19 pcie0: pcie@1,0 {
21 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
22 reg = <0x0800 0 0 0 0>;
26 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
27 0x81000000 0 0 0x81000000 0x1 0 1 0>;
28 bus-range = <0x00 0xff>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dqoriq-fman-0-10g-0.dtsi2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
60 interrupts = <101 2 0 0>;
H A Dqoriq-fman-1-10g-0.dtsi2 * QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
43 cell-index = <0x30>;
45 reg = <0xb0000 0x1000>;
49 cell-index = <0x8>;
51 reg = <0xf0000 0x1000>;
57 #size-cells = <0>;
59 reg = <0xf1000 0x1000>;
H A Dqoriq-fman3-1-10g-0.dtsi2 * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x500000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
44 cell-index = <0x30>;
46 reg = <0xb0000 0x1000>;
51 cell-index = <0x8>;
53 reg = <0xf0000 0x1000>;
68 #size-cells = <0>;
70 reg = <0xf1000 0x1000>;
73 pcsphy14: ethernet-phy@0 {
[all …]
H A Dqoriq-fman3-0-10g-0.dtsi2 * QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x400000 ]
37 cell-index = <0x10>;
39 reg = <0x90000 0x1000>;
44 cell-index = <0x30>;
46 reg = <0xb0000 0x1000>;
51 cell-index = <0x8>;
53 reg = <0xf0000 0x1000>;
68 #size-cells = <0>;
70 reg = <0xf1000 0x1000>;
73 pcsphy6: ethernet-phy@0 {
[all …]
/openbmc/linux/arch/x86/boot/
H A Dheader.S28 BOOTSEG = 0x07C0 /* original address of boot-sector */
29 SYSSEG = 0x1000 /* historical load address >> 4 */
39 .set salign, 0x1000
40 .set falign, 0x200
47 .org 0x38
62 .set image_file_add_flags, 0
67 .long 0 # TimeDateStamp
68 .long 0 # PointerToSymbolTable
78 .byte 0x02 # MajorLinkerVersion
79 .byte 0x14 # MinorLinkerVersion
[all …]

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