/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6ull-pinfunc.h | 16 #define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00BC 0x0348 0x0644 0x0 0x6 18 #define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00C0 0x034C 0x0644 0x0 0x7 20 #define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00CC 0x0358 0x0640 0x1 0x5 22 #define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00D0 0x035C 0x0640 0x1 0x6 24 #define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01EC 0x0478 0x0640 0x8 0x7 27 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DCE_TX 0x0084 0x0310 0x0000 0x9 0x0 28 #define MX6ULL_PAD_UART1_TX_DATA__UART5_DTE_RX 0x0084 0x0310 0x0644 0x9 0x4 29 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DCE_RX 0x0088 0x0314 0x0644 0x9 0x5 30 #define MX6ULL_PAD_UART1_RX_DATA__UART5_DTE_TX 0x0088 0x0314 0x0000 0x9 0x0 31 #define MX6ULL_PAD_UART1_CTS_B__UART5_DCE_CTS 0x008C 0x0318 0x0000 0x9 0x0 [all …]
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H A D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0 16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0 17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1 18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1 19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1 20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0 21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0 22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0 23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0 24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1 [all …]
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H A D | imx6sx-pinfunc.h | 13 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 14 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 15 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 16 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 17 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 18 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 19 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 20 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 21 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 22 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 [all …]
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H A D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0 18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0 19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0 20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0 21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0 22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0 23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0 24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0 26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | imx6ull-pinfunc.h | 17 #define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 18 #define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 19 #define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 20 #define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 21 #define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 22 #define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 23 #define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 24 #define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 25 #define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 26 #define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 [all …]
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H A D | imx6sx-pinfunc.h | 17 #define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1 18 #define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0 19 #define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0 20 #define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0 21 #define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0 22 #define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0 23 #define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0 24 #define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0 25 #define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1 26 #define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0 [all …]
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H A D | imx7ulp-pinfunc.h | 26 #define ULP1_PAD_PTA0_LLWU0_P0__CMP0_IN2A 0x0000 0x0000 0x0 0x0 27 #define ULP1_PAD_PTA0_LLWU0_P0__PTA0 0x0000 0x0000 0x1 0x0 28 #define ULP1_PAD_PTA0_LLWU0_P0__LLWU0_P0 0x0000 0x0000 0xd 0x0 29 #define ULP1_PAD_PTA0_LLWU0_P0__LPSPI0_PCS1 0x0000 0xd104 0x3 0x2 30 #define ULP1_PAD_PTA0_LLWU0_P0__LPUART0_CTS_B 0x0000 0xd1f8 0x4 0x2 31 #define ULP1_PAD_PTA0_LLWU0_P0__LPI2C0_SCL 0x0000 0xd17c 0x5 0x2 32 #define ULP1_PAD_PTA0_LLWU0_P0__TPM0_CLKIN 0x0000 0xd1a8 0x6 0x2 33 #define ULP1_PAD_PTA0_LLWU0_P0__I2S0_RX_BCLK 0x0000 0x01b8 0x7 0x2 34 #define ULP1_PAD_PTA1__CMP0_IN2B 0x0004 0x0000 0x0 0x0 35 #define ULP1_PAD_PTA1__PTA1 0x0004 0x0000 0x1 0x0 [all …]
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/openbmc/u-boot/arch/arm/cpu/armv8/ |
H A D | psci.S | 71 PSCI_TABLE(0, 0) 97 PSCI_TABLE(0, 0) 103 ldr x15, =0x3C0 132 /* Caller must put PSCI function-ID table base in x9 */ 135 1: ldr x10, [x9] /* Load PSCI function table */ 137 ubfx x10, x10, #0, #32 141 add x9, x9, #8 /* If not match, try next entry */ 151 ldr x0, =0xFFFFFFFF 155 /* SMC function ID 0x84000000-0x8400001F: 32 bits PSCI */ 156 ldr w9, =0x8400001F [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0 14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1 15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0 16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1 17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0 18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0 19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0 20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0 21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0 22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0 [all …]
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/openbmc/u-boot/arch/arm/lib/ |
H A D | gic_64.S | 29 mov w9, #0x37 /* EnableGrp0 | EnableGrp1NS */ 33 and w10, w9, #0x1f /* ITLinesNumber */ 37 mov w9, #~0 38 0: str w9, [x11], #0x4 39 str wzr, [x12], #0x4 /* Config SPIs as Group1NS */ 40 sub w10, w10, #0x1 41 cbnz w10, 0b 43 mov w9, #0x3 /* EnableGrp0 | EnableGrp1 */ 46 and w10, w9, #0x1f /* ITLinesNumber */ 49 mov w9, #~0 /* Config SPIs as Grp1 */ [all …]
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H A D | crt0_64.S | 51 * environment has BSS (initialized to 0), initialized non-const 69 * Set up initial C runtime environment and call board_init_f(0). 81 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ 89 mov x0, #0 99 bic sp, x0, #0xf /* 16-byte alignment for ABI compliance */ 106 ldr x9, _TEXT_BASE /* x9 <- Linked value of _start */ 107 sub x9, x9, x0 /* x9 <- Run-vs-link offset */ 108 add lr, lr, x9 111 ldr x9, [x18, #GD_RELOC_OFF] /* x9 <- gd->reloc_off */ 112 add lr, lr, x9 /* new return address after relocation */ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dpcs/ |
H A D | dpcs_4_2_3_sh_mask.h | 31 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 32 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 34 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 35 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 40 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 41 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 43 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 44 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 49 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 50 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
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H A D | dpcs_3_1_4_sh_mask.h | 33 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN__SHIFT 0x0 34 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_EN_OVRD_EN__SHIFT 0x1 35 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD__SHIFT 0x2 36 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_USE_PAD_OVRD_EN__SHIFT 0x3 37 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE__SHIFT 0x4 38 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__REF_CLK_RANGE_OVRD_EN__SHIFT 0x7 39 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN__SHIFT 0x8 40 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__BG_EN_OVRD_EN__SHIFT 0x9 41 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_EN__SHIFT 0xa 42 …S_CR0_SUP_DIG_REFCLK_OVRD_IN__HDMIMODE_ENABLE_OVRD_EN__SHIFT 0xb [all …]
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H A D | dpcs_4_2_2_sh_mask.h | 14 …S_CR0_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 15 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 17 …S_CR0_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 18 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 23 …S_CR1_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 24 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL 26 …S_CR1_DPCSSYS_CR_DATA__RDPCS_TX_CR_DATA__SHIFT 0x0 27 …CSSYS_CR_DATA__RDPCS_TX_CR_DATA_MASK 0x0000FFFFL 32 …S_CR2_DPCSSYS_CR_ADDR__RDPCS_TX_CR_ADDR__SHIFT 0x0 33 …CSSYS_CR_ADDR__RDPCS_TX_CR_ADDR_MASK 0x0000FFFFL [all …]
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/openbmc/linux/arch/arm64/crypto/ |
H A D | poly1305-armv8.pl | 34 $0 =~ m/(.*[\/\\])[^\/\\]+$/; $dir=$1; 44 my ($ctx,$inp,$len,$padbit) = map("x$_",(0..3)); 78 mov $s1,#0xfffffffc0fffffff 79 movk $s1,#0x0fff,lsl#48 84 and $r0,$r0,$s1 // &=0ffffffc0fffffff 86 and $r1,$r1,$s1 // &=0ffffffc0ffffffc 145 cmp x17,#0 // is_base2_26? 233 cmp $r0,#0 // is_base2_26? 262 my ($R0,$R1,$S1,$R2,$S2,$R3,$S3,$R4,$S4) = map("v$_.4s",(0..8)); 313 and x12,$h0,#0x03ffffff // base 2^64 -> base 2^26 [all …]
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H A D | aes-modes.S | 55 frame_push 0 85 frame_push 0 182 frame_push 0 248 add x9, x8, #32 250 sub x9, x9, x4 252 ld1 {v4.16b}, [x9] 277 add x9, x8, #32 279 sub x9, x9, x4 281 ld1 {v4.16b}, [x9] 306 .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff [all …]
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/openbmc/qemu/tests/tcg/i386/ |
H A D | test-i386-f2xm1.c | 14 { 0x4.1481697ac693aa6p-4L, 0x3.17ec9f8454896518p-4L, 0x3.17ec9f845489651cp-4L }, 15 { -0xd.84a873b14b9c0e2p-4L, -0x7.1788c46ac260d948p-4L, -0x7.1788c46ac260d94p-4L }, 16 { 0xa.a3dc18b1eff7e8ap-188L, 0x7.6009241b9e21523p-188L, 0x7.6009241b9e215238p-188L }, 17 { -0xe.846aeb6f58174d5p-92L, -0xa.1006405817acc33p-92L, -0xa.1006405817acc32p-92L }, 18 { 0x5.4459f2ac77bb0978p-4L, 0x4.19d3ce7fd5b90ac8p-4L, 0x4.19d3ce7fd5b90adp-4L }, 19 { -0xb.79bece734a62216p-4L, -0x6.4489a7fc150c0fp-4L, -0x6.4489a7fc150c0ef8p-4L }, 20 { 0xa.ab48f9ef732f5c4p-4L, 0x9.66acd7d4b7cf015p-4L, 0x9.66acd7d4b7cf016p-4L }, 21 { -0xb.8204e63359a46e6p-4L, -0x6.48060f0a504e3488p-4L, -0x6.48060f0a504e348p-4L }, 22 { 0xd.c732865701ae935p-4L, 0xd.103bc1a15cd9f71p-4L, 0xd.103bc1a15cd9f72p-4L }, 23 { -0x1.6296e8ff499827a2p-4L, -0xe.e8dc973f0bce9d1p-8L, -0xe.e8dc973f0bce9dp-8L }, [all …]
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H A D | test-i386-fyl2x.c | 31 { 0x1p-16400L, 1.5L, -24600.0L, -24600.0L }, 33 …{ 0x2.0a40b4bd6349d53p+14380L, -0x3.612a1cec52e70388p-14116L, -0xb.dd9637a24570d1ap-14104L, -0xb.d… 34 …{ 0xa.a3dc18b1eff7e8ap-4L, 0x7.423575b7ac0ba6a8p-7212L, -0x4.45ac6ae2f9cc1a7p-7212L, -0x4.45ac6ae2… 35 …{ 0x1.51167cab1deec25ep-9616L, 0xb.79bece734a62216p-14512L, -0x1.af0880f05109d5c8p-14496L, -0x1.af… 36 …{ 0x1.55691f3dee65eb88p+6420L, -0x2.e081398cd6691b98p-2640L, -0x4.8275aa22ebb6ebe8p-2628L, -0x4.82… 37 …{ 0x3.71cca195c06ba4d4p-6312L, -0xb.14b747fa4cc13d1p+5052L, 0x1.112301748a1cc83p+5068L, 0x1.112301… 38 …{ 0x2.0f924dde0806572p+8924L, -0x7.ece8699d62a9f76p-14464L, -0x1.144eba5c079d0fa2p-14448L, -0x1.14… 39 …{ 0x4.b875c0342c9f86b8p-5832L, 0xe.a37e0fa859e499cp+732L, -0x1.4d5bc95e2af0bb08p+748L, -0x1.4d5bc9… 40 …{ 0x7.23210d9474f0715p+364L, -0x5.baaf3a431730f158p-2436L, -0x8.35afbc04cd37fafp-2428L, -0x8.35afb… 41 …{ 0xd.2330923899aae43p+776L, 0x2.a68cc6ddbe3b3a5p+6528L, 0x8.12b3f5a7b346e37p+6536L, 0x8.12b3f5a7b… [all …]
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H A D | test-i386-fyl2xp1.c | 26 { 0x4p-4L, 0x1p-16400L, 0x5.269e12f3468p-16404L, 0x5.269e12f347p-16404L }, 28 …{ 0x1.31edb79669dd58b4p-4L, 0x6.c25439d8a5ce071p+14380L, 0xb.3d0da52c1f58af3p+14376L, 0xb.3d0da52c… 29 …{ -0x1.8ee6680c65ce5a5p-4L, -0x7.423575b7ac0ba6a8p-2228L, 0x1.12aefa96f5501268p-2228L, 0x1.12aefa9… 30 …{ 0x2.a22cf9563bdd84bcp-140L, -0x2.de6fb39cd2988858p-9616L, -0xa.e65ebedd6a09e4cp-9756L, -0xa.e65e… 31 …{ -0x7.d1095c8p-16416L, 0x1.faa600d255691f3cp+6420L, -0x1.6516c14a553da39ap-9992L, -0x1.6516c14a55… 32 …{ 0x4.109249df7871ecb8p-4L, 0x1.48d8eebeb8e650ccp-4976L, 0x6.b65f4ea303a8bc3p-4980L, 0x6.b65f4ea30… 33 …{ -0x4.69bcd5ccca0e4b7p-4L, -0x5.8808ae941f249bb8p+5056L, 0x2.93432047c7d8a37p+5056L, 0x2.93432047… 34 …{ 0x3.311f29ec8b38ef74p-4L, -0x3.9865a5505c3ae018p+8924L, -0xf.188d6a2bba06e17p+8920L, -0xf.188d6a… 35 …{ -0x2.d60110be2e4f812p-4L, 0x9.d61827e646421b3p-11580L, -0x2.c4c3e84b6c7366c8p-11580L, -0x2.c4c3e… 36 …{ 0xe.e4d7ebcee10774ap-8L, 0x6.5cde5b7691984918p+732L, 0x8.4e3d353f31e18a3p+728L, 0x8.4e3d353f31e1… [all …]
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H A D | test-i386-fpatan.c | 10 { -__builtin_infl(), -__builtin_infl(), -0x2.5b2f8fe6643a46ap+0L, -0x2.5b2f8fe6643a469cp+0L }, 11 { -__builtin_infl(), -1.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 12 { -__builtin_infl(), -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 13 { -__builtin_infl(), 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 14 { -__builtin_infl(), 1.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 15 { -__builtin_infl(), __builtin_infl(), 0x2.5b2f8fe6643a469cp+0L, 0x2.5b2f8fe6643a46ap+0L }, 16 { -1.0L, -__builtin_infl(), -0x1.921fb54442d1846ap+0L, -0x1.921fb54442d18468p+0L }, 17 { -1.0L, -0.0L, -0x3.243f6a8885a308d4p+0L, -0x3.243f6a8885a308dp+0L }, 18 { -1.0L, 0.0L, 0x3.243f6a8885a308dp+0L, 0x3.243f6a8885a308d4p+0L }, 19 { -1.0L, __builtin_infl(), 0x1.921fb54442d18468p+0L, 0x1.921fb54442d1846ap+0L }, [all …]
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/openbmc/linux/arch/arm64/mm/ |
H A D | proc.S | 36 #define TCR_KASLR_FLAGS 0 47 #define TCR_KASAN_SW_FLAGS 0 59 #define TCR_MTE_FLAGS 0 89 mrs x9, mdscr_el1 97 stp x8, x9, [x0, #48] 117 ldp x9, x10, [x0, #48] 137 msr vbar_el1, x9 210 tbz \type, #0, .Lnext_\type // Skip invalid and 265 end_pudp .req x9 287 __idmap_cpu_set_reserved_ttbr1 x8, x9 [all …]
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/openbmc/linux/arch/arm/boot/dts/microchip/ |
H A D | at91-natte.dtsi | 13 #mux-control-cells = <0>; 15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>, 60 #size-cells = <0>; 62 i2c@0 { 63 reg = <0>; 65 #size-cells = <0>; 69 reg = <0x9>; 81 #size-cells = <0>; 85 reg = <0x9>; 97 #size-cells = <0>; [all …]
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/openbmc/linux/arch/arm/crypto/ |
H A D | chacha-scalar-core.S | 14 * (x8, x9) to the stack and swap them out with (x10, x11). This adds one 24 * similarly for row 'd'. (brot, drot) start out as (0, 0) but we make it such 38 X9_X11 .req r9 // shared by x9 and x11 106 // quarterrounds: (x0, x4, x8, x12) and (x1, x5, x9, x13) 109 // save (x8, x9); restore (x10, x11) 110 __strd X8_X10, X9_X11, sp, 0 124 // save (x10, x11); restore (x8, x9) 126 __ldrd X8_X10, X9_X11, sp, 0 128 // quarterrounds: (x2, x7, x8, x13) and (x3, x4, x9, x14) 133 .set brot, 0 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/ |
H A D | dcn_3_2_0_sh_mask.h | 28 …T_DISPCLK_CNTL__DENTIST_DISPCLK_WDIVIDER__SHIFT 0x0 29 …T_DISPCLK_CNTL__DENTIST_DISPCLK_RDIVIDER__SHIFT 0x8 30 …T_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_MODE__SHIFT 0xf 31 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHGTOG__SHIFT 0x11 32 …_DISPCLK_CNTL__DENTIST_DISPCLK_DONETOG__SHIFT 0x12 33 …_DISPCLK_CNTL__DENTIST_DISPCLK_CHG_DONE__SHIFT 0x13 34 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHG_DONE__SHIFT 0x14 35 …_DISPCLK_CNTL__DENTIST_DPPCLK_CHGTOG__SHIFT 0x15 36 …_DISPCLK_CNTL__DENTIST_DPPCLK_DONETOG__SHIFT 0x16 37 …_DISPCLK_CNTL__DENTIST_DPPCLK_WDIVIDER__SHIFT 0x18 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_4_1_sh_mask.h | 27 #define MM_INDEX__MM_OFFSET_MASK 0x7fffffff 28 #define MM_INDEX__MM_OFFSET__SHIFT 0x0 29 #define MM_INDEX__MM_APER_MASK 0x80000000 30 #define MM_INDEX__MM_APER__SHIFT 0x1f 31 #define MM_INDEX_HI__MM_OFFSET_HI_MASK 0xffffffff 32 #define MM_INDEX_HI__MM_OFFSET_HI__SHIFT 0x0 33 #define MM_DATA__MM_DATA_MASK 0xffffffff 34 #define MM_DATA__MM_DATA__SHIFT 0x0 35 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE_MASK 0x2 36 #define CC_BIF_BX_FUSESTRAP0__STRAP_BIF_PX_CAPABLE__SHIFT 0x1 [all …]
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