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/openbmc/qemu/hw/ppc/
H A Drs6000_mc.c52 uint32_t val = 0; in rs6000mc_port0803_read()
56 for (socket = 0; socket < 6; socket++) { in rs6000mc_port0803_read()
71 uint32_t val = 0xff; in rs6000mc_port0804_read()
75 for (socket = 0; socket < 6; socket++) { in rs6000mc_port0804_read()
80 s->port0820_index = 0; in rs6000mc_port0804_read()
91 uint32_t val = s->end_address[s->port0820_index] & 0x1f; in rs6000mc_port0820_read()
101 uint32_t end_address = val & 0x1f; in rs6000mc_port0820_write()
105 if (socket > 0 && socket < 7) { in rs6000mc_port0820_write()
108 uint32_t start_address = 0; in rs6000mc_port0820_write()
114 memory_region_set_enabled(&s->simm[socket - 1], size != 0); in rs6000mc_port0820_write()
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/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dqcom,sm8250-camss.yaml113 port@0:
308 reg = <0 0xac6a000 0 0x2000>,
309 <0 0xac6c000 0 0x2000>,
310 <0 0xac6e000 0 0x1000>,
311 <0 0xac70000 0 0x1000>,
312 <0 0xac72000 0 0x1000>,
313 <0 0xac74000 0 0x1000>,
314 <0 0xacb4000 0 0xd000>,
315 <0 0xacc3000 0 0xd000>,
316 <0 0xacd9000 0 0x2200>,
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_GECC2 0x9c9
36 #define mmMC_ARB_GECC2_CLI 0x9ca
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H A Dgmc_8_2_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
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H A Dgmc_7_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_AGE_CNTL 0x9bf
29 #define mmMC_ARB_RET_CREDITS2 0x9c0
30 #define mmMC_ARB_FED_CNTL 0x9c1
31 #define mmMC_ARB_GECC2_STATUS 0x9c2
32 #define mmMC_ARB_GECC2_MISC 0x9c3
33 #define mmMC_ARB_GECC2_DEBUG 0x9c4
34 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
35 #define mmMC_ARB_PERF_CID 0x9c6
36 #define mmMC_ARB_GECC2 0x9c9
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H A Dgmc_8_1_d.h27 #define mmMC_CONFIG 0x800
28 #define mmMC_ARB_ATOMIC 0x9be
29 #define mmMC_ARB_AGE_CNTL 0x9bf
30 #define mmMC_ARB_RET_CREDITS2 0x9c0
31 #define mmMC_ARB_FED_CNTL 0x9c1
32 #define mmMC_ARB_GECC2_STATUS 0x9c2
33 #define mmMC_ARB_GECC2_MISC 0x9c3
34 #define mmMC_ARB_GECC2_DEBUG 0x9c4
35 #define mmMC_ARB_GECC2_DEBUG2 0x9c5
36 #define mmMC_ARB_PERF_CID 0x9c6
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/openbmc/linux/drivers/net/wireless/broadcom/b43/
H A Dphy_ht.c22 HT_RSSI_W1 = 0,
42 b43_radio_write(dev, 0x16, e->radio_syn16); in b43_radio_2059_channel_setup()
43 b43_radio_write(dev, 0x17, e->radio_syn17); in b43_radio_2059_channel_setup()
44 b43_radio_write(dev, 0x22, e->radio_syn22); in b43_radio_2059_channel_setup()
45 b43_radio_write(dev, 0x25, e->radio_syn25); in b43_radio_2059_channel_setup()
46 b43_radio_write(dev, 0x27, e->radio_syn27); in b43_radio_2059_channel_setup()
47 b43_radio_write(dev, 0x28, e->radio_syn28); in b43_radio_2059_channel_setup()
48 b43_radio_write(dev, 0x29, e->radio_syn29); in b43_radio_2059_channel_setup()
49 b43_radio_write(dev, 0x2c, e->radio_syn2c); in b43_radio_2059_channel_setup()
50 b43_radio_write(dev, 0x2d, e->radio_syn2d); in b43_radio_2059_channel_setup()
[all …]
/openbmc/linux/drivers/media/i2c/
H A Drj54n1cb0c.c24 #define RJ54N1_DEV_CODE 0x0400
25 #define RJ54N1_DEV_CODE2 0x0401
26 #define RJ54N1_OUT_SEL 0x0403
27 #define RJ54N1_XY_OUTPUT_SIZE_S_H 0x0404
28 #define RJ54N1_X_OUTPUT_SIZE_S_L 0x0405
29 #define RJ54N1_Y_OUTPUT_SIZE_S_L 0x0406
30 #define RJ54N1_XY_OUTPUT_SIZE_P_H 0x0407
31 #define RJ54N1_X_OUTPUT_SIZE_P_L 0x0408
32 #define RJ54N1_Y_OUTPUT_SIZE_P_L 0x0409
33 #define RJ54N1_LINE_LENGTH_PCK_S_H 0x040a
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]
/openbmc/linux/include/linux/mlx5/
H A Dmlx5_ifc.h38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
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