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Searched +full:0 +full:x80c00000 (Results 1 – 10 of 10) sorted by relevance

/openbmc/u-boot/board/imgtec/xilfpga/
H A DKconfig13 default 0x80C00000
/openbmc/u-boot/board/espt/
H A Dlowlevel_init.S168 PACR_A: .long 0xFFEF0000
169 PBCR_A: .long 0xFFEF0002
170 PCCR_A: .long 0xFFEF0004
171 PDCR_A: .long 0xFFEF0006
172 PECR_A: .long 0xFFEF0008
173 PFCR_A: .long 0xFFEF000A
174 PGCR_A: .long 0xFFEF000C
175 PHCR_A: .long 0xFFEF000E
176 PICR_A: .long 0xFFEF0010
177 PJCR_A: .long 0xFFEF0012
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath11k.yaml267 reg = <0xcd00000 0x4040>,
268 <0x4ab000 0x20>;
275 reg = <0xc000000 0x2000000>;
276 interrupts = <0 320 1>,
277 <0 319 1>,
278 <0 318 1>,
279 <0 317 1>,
280 <0 316 1>,
281 <0 315 1>,
282 <0 314 1>,
[all …]
/openbmc/linux/drivers/gpu/drm/sun4i/
H A Dsun8i_hdmi_phy.c17 #define I2C_ADDR 0x69
22 { 0x00b3, 0x0000 },
23 { 0x2153, 0x0000 },
24 { 0x40f3, 0x0000 },
28 { 0x00b3, 0x0000 },
29 { 0x2153, 0x0000 },
30 { 0x40a2, 0x0001 },
34 { 0x00b3, 0x0000 },
35 { 0x2142, 0x0001 },
36 { 0x40a2, 0x0001 },
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dqdu1000.dtsi24 #size-cells = <0>;
26 CPU0: cpu@0 {
29 reg = <0x0 0x0>;
30 clocks = <&cpufreq_hw 0>;
34 qcom,freq-domains = <&cpufreq_hw 0>;
52 reg = <0x0 0x100>;
53 clocks = <&cpufreq_hw 0>;
57 qcom,freq-domains = <&cpufreq_hw 0>;
70 reg = <0x0 0x200>;
71 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm6375.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #size-cells = <0>;
41 CPU0: cpu@0 {
44 reg = <0x0 0x0>;
45 clocks = <&cpufreq_hw 0>;
48 qcom,freq-domain = <&cpufreq_hw 0>;
70 reg = <0x0 0x100>;
71 clocks = <&cpufreq_hw 0>;
74 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
/openbmc/linux/drivers/net/wireless/marvell/mwifiex/
H A Dpcie.c40 .tx_start_ptr = 0,
42 .tx_wrap_mask = 0,
44 .rx_wrap_mask = 0,
48 .ring_flag_sop = 0,
49 .ring_flag_eop = 0,
50 .ring_flag_xs_sop = 0,
51 .ring_flag_xs_eop = 0,
52 .ring_tx_start_ptr = 0,
53 .pfu_enabled = 0,
55 .msix_support = 0,
[all …]