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Searched +full:0 +full:x80004000 (Results 1 – 16 of 16) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mxs/
H A Dregs-base.h21 #define MXS_ICOLL_BASE 0x80000000
22 #define MXS_APBH_BASE 0x80004000
23 #define MXS_ECC8_BASE 0x80008000
24 #define MXS_BCH_BASE 0x8000A000
25 #define MXS_GPMI_BASE 0x8000C000
26 #define MXS_SSP0_BASE 0x80010000
27 #define MXS_SSP1_BASE 0x80034000
28 #define MXS_ETM_BASE 0x80014000
29 #define MXS_PINCTRL_BASE 0x80018000
30 #define MXS_DIGCTL_BASE 0x8001C000
[all …]
/openbmc/linux/drivers/dma/bestcomm/
H A Dbcom_fec_rx_task.c27 0x4243544b,
28 0x18060709,
29 0x00000000,
30 0x00000000,
33 0x808220e3, /* LCD: idx0 = var1, idx1 = var4; idx1 <= var3; idx0 += inc4, idx1 += inc3 */
34 0x10601010, /* DRD1A: var4 = var2; FN=0 MORE init=3 WS=0 RS=0 */
35 0xb8800264, /* LCD: idx2 = *idx1, idx3 = var0; idx2 < var9; idx2 += inc4, idx3 += inc4 */
36 0x10001308, /* DRD1A: var4 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
37 0x60140002, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=2 EXT init=0 WS=2 RS=2 */
38 0x0cccfcca, /* DRD2B1: *idx3 = EU3(); EU3(*idx3,var10) */
[all …]
H A Dbcom_fec_tx_task.c27 0x4243544b,
28 0x2407070d,
29 0x00000000,
30 0x00000000,
33 0x8018001b, /* LCD: idx0 = var0; idx0 <= var0; idx0 += inc3 */
34 0x60000005, /* DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
35 0x01ccfc0d, /* DRD2B1: var7 = EU3(); EU3(*idx0,var13) */
36 0x8082a123, /* LCD: idx0 = var1, idx1 = var5; idx1 <= var4; idx0 += inc4, idx1 += inc3 */
37 0x10801418, /* DRD1A: var5 = var3; FN=0 MORE init=4 WS=0 RS=0 */
38 0xf88103a4, /* LCDEXT: idx2 = *idx1, idx3 = var2; idx2 < var14; idx2 += inc4, idx3 += inc4 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,mxs-dma.yaml60 reg = <0x80004000 0x2000>;
64 87 86 0 0>;
71 reg = <0x80024000 0x2000>;
72 interrupts = <78 79 66 0
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dst,nomadik-i2c.yaml90 reg = <0x80004000 0x1000>;
94 #size-cells = <0>;
105 reg = <0x101f8000 0x1000>;
110 #size-cells = <0>;
/openbmc/u-boot/drivers/dma/
H A DMCD_tasks.c66 0x00000000,
67 0x00000000,
68 (u32) MCD_varTab0, /* Task 0 Variable Table */
69 (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */
70 0x00000000,
71 0x00000000,
72 (u32) MCD_contextSave0, /* Task 0 context save space */
73 0x00000000,
74 0x00000000,
75 0x00000000,
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dgen9_renderstate.c11 0x000007a8,
12 0x000007b4,
13 0x000007bc,
14 0x000007cc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
H A Dgen8_renderstate.c11 0x00000798,
12 0x000007a4,
13 0x000007ac,
14 0x000007bc,
19 0x7a000004,
20 0x01000000,
21 0x00000000,
22 0x00000000,
23 0x00000000,
24 0x00000000,
[all …]
/openbmc/qemu/hw/mips/
H A Djazz.c78 address_space_read(&address_space_memory, 0x90000071, in rtc_read()
86 uint8_t buf = val & 0xff; in rtc_write()
87 address_space_write(&address_space_memory, 0x90000071, in rtc_write()
104 return 0xff; in dma_dummy_read()
144 sysbus_mmio_map(sysbus, 0, 0x80001000); in mips_jazz_init_net()
145 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4)); in mips_jazz_init_net()
149 checksum = 0; in mips_jazz_init_net()
150 for (i = 0; i < 6; i++) { in mips_jazz_init_net()
153 if (checksum > 0xff) { in mips_jazz_init_net()
154 checksum = (checksum + 1) & 0xff; in mips_jazz_init_net()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/mxs/
H A Dimx23.dtsi32 #size-cells = <0>;
34 cpu@0 {
37 reg = <0>;
45 reg = <0x80000000 0x80000>;
52 reg = <0x80000000 0x40000>;
59 reg = <0x80000000 0x2000>;
64 reg = <0x80004000 0x2000>;
65 interrupts = <0>, <14>, <20>, <0>,
73 reg = <0x80008000 0x2000>;
81 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
[all …]
H A Dimx28.dtsi43 #size-cells = <0>;
45 cpu@0 {
48 reg = <0>;
56 reg = <0x80000000 0x80000>;
63 reg = <0x80000000 0x3c900>;
70 reg = <0x80000000 0x2000>;
74 reg = <0x80002000 0x2000>;
83 reg = <0x80004000 0x2000>;
87 <87>, <86>, <0>, <0>;
94 reg = <0x80006000 0x800>;
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dcg14.c58 #define CG14_MCR_INTENABLE_MASK 0x80
60 #define CG14_MCR_VIDENABLE_MASK 0x40
62 #define CG14_MCR_PIXMODE_MASK 0x30
64 #define CG14_MCR_TMR_MASK 0x0c
66 #define CG14_MCR_TMENABLE_MASK 0x02
67 #define CG14_MCR_RESET_SHIFT 0
68 #define CG14_MCR_RESET_MASK 0x01
70 #define CG14_REV_REVISION_MASK 0xf0
71 #define CG14_REV_IMPL_SHIFT 0
72 #define CG14_REV_IMPL_MASK 0x0f
[all …]
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0_3.c37 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
76 return 0; in jpeg_v4_0_3_early_init()
92 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
108 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
111 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
130 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
141 (j ? (0x40 * j - 0xc80) : 0)); in jpeg_v4_0_3_sw_init()
153 return 0; in jpeg_v4_0_3_sw_init()
192 direct_wt = { {0} }; in jpeg_v4_0_3_start_sriov()
193 struct mmsch_v4_0_cmd_end end = { {0} }; in jpeg_v4_0_3_start_sriov()
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0.dtsi40 #size-cells = <0>;
56 reg = <0x300>;
65 reg = <0x301>;
81 polling-delay = <0>;
93 hysteresis = <0>;
121 /* The first (always on) ESRAM 0, 128 KB */
123 reg = <0x40000000 0x20000>;
126 ranges = <0 0x40000000 0x20000>;
128 sram@0 {
130 reg = <0x0 0x10000>;
[all …]
/openbmc/linux/arch/arm/
H A DKconfig.debug149 0x80000000 | 0xf0000000 | UART0
150 0x80004000 | 0xf0004000 | UART1
151 0x80008000 | 0xf0008000 | UART2
152 0x8000c000 | 0xf000c000 | UART3
153 0x80010000 | 0xf0010000 | UART4
154 0x80014000 | 0xf0014000 | UART5
155 0x80018000 | 0xf0018000 | UART6
156 0x8001c000 | 0xf001c000 | UART7
157 0x80020000 | 0xf0020000 | UART8
158 0x80024000 | 0xf0024000 | UART9
[all …]
/openbmc/qemu/disas/
H A Dnanomips.c62 return g_strdup_printf("0x%" PRIx64, a); in to_string()
97 * 1 0
98 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
107 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
108 * 3 2 1 0
123 sizeof(register_list) / sizeof(register_list[0]), info); in decode_gpr_gpr4()
132 * 1 0
133 * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
142 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
143 * 3 2 1 0
[all …]