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/openbmc/u-boot/include/configs/
H A Dsocfpga_stratix10_socdk.h17 #define CONFIG_LOADADDR 0x2000000
21 #define CPU_RELEASE_ADDR 0xFFD12210
23 #define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */
40 #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
41 #define CONFIG_SYS_INIT_RAM_SIZE 0x40000
51 #define CONFIG_ENV_SIZE 0x1000
52 #define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
60 /*#define CONFIG_QSPI_RBF_ADDR 0x720000*/
68 #define CONFIG_ENV_OFFSET 0x710000
76 #define MTDIDS_DEFAULT "nor0=ff705000.spi.0"
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmarvell,nand-controller.yaml66 minimum: 0
71 - minimum: 0
156 reg = <0xd0000 0x54>;
158 #size-cells = <0>;
160 clocks = <&coredivclk 0>;
162 nand@0 {
163 reg = <0>;
165 nand-rb = <0>;
177 partition@0 {
179 reg = <0x00000000 0x40000000>;
[all …]
/openbmc/qemu/hw/misc/
H A Dimx7_ccm.c27 memset(s->pmu, 0, sizeof(s->pmu)); in imx7_analog_reset()
28 memset(s->analog, 0, sizeof(s->analog)); in imx7_analog_reset()
30 s->analog[ANALOG_PLL_ARM] = 0x00002042; in imx7_analog_reset()
31 s->analog[ANALOG_PLL_DDR] = 0x0060302c; in imx7_analog_reset()
32 s->analog[ANALOG_PLL_DDR_SS] = 0x00000000; in imx7_analog_reset()
33 s->analog[ANALOG_PLL_DDR_NUM] = 0x06aaac4d; in imx7_analog_reset()
34 s->analog[ANALOG_PLL_DDR_DENOM] = 0x100003ec; in imx7_analog_reset()
35 s->analog[ANALOG_PLL_480] = 0x00002000; in imx7_analog_reset()
36 s->analog[ANALOG_PLL_480A] = 0x52605a56; in imx7_analog_reset()
37 s->analog[ANALOG_PLL_480B] = 0x52525216; in imx7_analog_reset()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-cp110-master.dtsi62 ranges = <0x0 0x0 0xf2000000 0x2000000>;
64 cpm_ethernet: ethernet@0 {
66 reg = <0x0 0x100000>, <0x129000 0xb000>;
74 port-id = <0>;
75 gop-port-id = <0>;
96 #size-cells = <0>;
98 reg = <0x12a200 0x10>;
104 reg = <0x440000 0x1000>;
126 reg = <0x440000 0x20>;
128 max-func = <0xf>;
[all …]
/openbmc/u-boot/drivers/video/
H A Dssd2828.c20 #define SSD2828_DIR 0xB0
21 #define SSD2828_VICR1 0xB1
22 #define SSD2828_VICR2 0xB2
23 #define SSD2828_VICR3 0xB3
24 #define SSD2828_VICR4 0xB4
25 #define SSD2828_VICR5 0xB5
26 #define SSD2828_VICR6 0xB6
27 #define SSD2828_CFGR 0xB7
28 #define SSD2828_VCR 0xB8
29 #define SSD2828_PCR 0xB9
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-cp11x.dtsi29 polling-delay-passive = <0>; /* Interrupt driven */
30 polling-delay = <0>; /* Interrupt driven */
32 thermal-sensors = <&CP11X_LABEL(thermal) 0>;
58 ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
60 CP11X_LABEL(ethernet): ethernet@0 {
62 #size-cells = <0>;
64 reg = <0x0 0x100000>, <0x129000 0xb000>, <0x220000 0x800>;
74 CP11X_LABEL(eth0): ethernet-port@0 {
88 reg = <0>;
89 port-id = <0>; /* For backward compatibility. */
[all …]
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dxtensa-modules.c.inc32 { "MMID", 89, 0 },
33 { "DDR", 104, 0 },
34 { "CONFIGID0", 176, 0 },
35 { "CONFIGID1", 208, 0 },
36 { "INTERRUPT", 226, 0 },
37 { "INTCLEAR", 227, 0 },
38 { "CCOUNT", 234, 0 },
39 { "PRID", 235, 0 },
40 { "ICOUNT", 236, 0 },
41 { "CCOMPARE0", 240, 0 },
[all …]
/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dxtensa-modules.c.inc31 { "LBEG", 0, 0 },
32 { "LEND", 1, 0 },
33 { "LCOUNT", 2, 0 },
34 { "BR", 4, 0 },
35 { "ACCLO", 16, 0 },
36 { "ACCHI", 17, 0 },
37 { "M0", 32, 0 },
38 { "M1", 33, 0 },
39 { "M2", 34, 0 },
40 { "M3", 35, 0 },
[all …]