| /openbmc/linux/drivers/pinctrl/mediatek/ |
| H A D | pinctrl-mt8365.c | 18 /* 0E4E8SR 4/8/12/16 */
20 /* 0E2E4SR 2/4/6/8 */
23 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0x710, 0, 2),
29 MTK_PIN_DRV_GRP(1, 0x710, 0, 2),
30 MTK_PIN_DRV_GRP(2, 0x710, 0, 2),
31 MTK_PIN_DRV_GRP(3, 0x710, 0, 2),
32 MTK_PIN_DRV_GRP(4, 0x710, 4, 2),
33 MTK_PIN_DRV_GRP(5, 0x710, 4, 2),
34 MTK_PIN_DRV_GRP(6, 0x710, 4, 2),
[all …]
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | pipeline.dot | 6 …scaler [label="{<scaler_0> 0} | Host\nScaler | {<scaler_1> 1} ", shape=Mrecord, style=filled, fill…
7 …frontend [label="{<frontend_0> 0} | Host\nFrontend | {<frontend_1> 1}", shape=Mrecord, style=fille…
8 sensor [label="Sensor | {<sensor_0> 0}", shape=Mrecord, style=filled, fillcolor=aquamarine]
9 io [label="{<io_0> 0} | V4L I/O", shape=Mrecord, style=filled, fillcolor=aquamarine]
13 scaler:scaler_1 -> io:io_0 [color=blue, label="HQ: 1280x720\nHS: 1280x720"]
|
| /openbmc/linux/Documentation/devicetree/bindings/display/panel/ |
| H A D | sony,tulip-truly-nt35521.yaml | 7 title: Sony Tulip Truly NT35521 5.24" 1280x720 MIPI-DSI Panel
13 The Sony Tulip Truly NT35521 is a 5.24" 1280x720 MIPI-DSI panel, which
55 #size-cells = <0>;
57 panel@0 {
59 reg = <0>;
|
| /openbmc/linux/arch/sh/kernel/cpu/sh4/ |
| H A D | setup-sh4-202.c | 23 DEFINE_RES_MEM(0xffe80000, 0x100),
24 DEFINE_RES_IRQ(evt2irq(0x700)),
25 DEFINE_RES_IRQ(evt2irq(0x720)),
26 DEFINE_RES_IRQ(evt2irq(0x760)),
27 DEFINE_RES_IRQ(evt2irq(0x740)),
32 .id = 0,
45 DEFINE_RES_MEM(0xffd80000, 0x30),
46 DEFINE_RES_IRQ(evt2irq(0x400)),
47 DEFINE_RES_IRQ(evt2irq(0x420)),
48 DEFINE_RES_IRQ(evt2irq(0x440)),
[all …]
|
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | am4.h | 8 #define AM4_CLKCTRL_OFFSET 0x20
12 #define AM4_L3S_TSC_CLKCTRL_OFFSET 0x120
14 #define AM4_L3S_TSC_ADC_TSC_CLKCTRL AM4_L3S_TSC_CLKCTRL_INDEX(0x120)
17 #define AM4_L4_WKUP_AON_CLKCTRL_OFFSET 0x228
19 #define AM4_L4_WKUP_AON_WKUP_M3_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x228)
20 #define AM4_L4_WKUP_AON_COUNTER_32K_CLKCTRL AM4_L4_WKUP_AON_CLKCTRL_INDEX(0x230)
23 #define AM4_L4_WKUP_CLKCTRL_OFFSET 0x220
25 #define AM4_L4_WKUP_L4_WKUP_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x220)
26 #define AM4_L4_WKUP_TIMER1_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x328)
27 #define AM4_L4_WKUP_WD_TIMER2_CLKCTRL AM4_L4_WKUP_CLKCTRL_INDEX(0x338)
[all …]
|
| /openbmc/linux/drivers/gpu/drm/ |
| H A D | drm_edid.c | 65 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
93 #define MICROSOFT_IEEE_OUI 0xca125c
102 #define LEVEL_DMT 0
121 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60),
123 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
124 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC),
127 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC),
130 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC),
133 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC),
136 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC),
[all …]
|
| /openbmc/u-boot/include/dt-bindings/sound/ |
| H A D | azalia.h | 18 #define AZALIA_OPCODE_CONFIG_DEFAULT 0x71c
19 #define AZALIA_OPCODE_IMPL_ID 0x720
20 #define AZALIA_OPCODE_READ_PARAM 0xf00
22 #define AZALIA_PARAM_VENDOR_ID 0
29 (((val) >> ((byte) * 8)) & 0xff))
33 (AZALIA_SET_BYTE(codec, nid, opcode, val, 0) | \
|
| /openbmc/linux/arch/arm/include/asm/hardware/ |
| H A D | cache-aurora-l2.h | 14 #define AURORA_SYNC_REG 0x700
15 #define AURORA_RANGE_BASE_ADDR_REG 0x720
16 #define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
17 #define AURORA_INVAL_RANGE_REG 0x774
18 #define AURORA_CLEAN_RANGE_REG 0x7b4
19 #define AURORA_FLUSH_RANGE_REG 0x7f4
23 (0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
25 (0 << AURORA_ACR_REPLACEMENT_OFFSET)
34 #define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
36 (0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
[all …]
|
| /openbmc/qemu/include/hw/intc/ |
| H A D | loongarch_extioi.h | 25 #define APIC_OFFSET 0x400
26 #define APIC_BASE (0x1000ULL + APIC_OFFSET)
28 #define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
29 #define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
30 #define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
31 #define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
32 #define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
33 #define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
34 #define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
35 #define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
[all …]
|
| /openbmc/linux/Documentation/fb/ |
| H A D | viafb.modes | 256 # 0 chars 7 lines
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
487 # 0 chars 0 lines
499 timings 8825 280 0 16 0 88 8 endmode mode "1152x720-60"
524 hsync high vsync high endmode mode "1200x720-60"
530 timings 16260 184 28 18 1 128 3 endmode mode "1280x720-50"
779 # 1280x720, 60 Hz, Non-Interlaced (74.481 MHz dotclock)
796 mode "1280x720-60"
|
| /openbmc/linux/drivers/phy/samsung/ |
| H A D | phy-exynos7-ufs.c | 10 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720
11 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
12 #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
14 #define EXYNOS7_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x5e
18 PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
19 PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
20 PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
21 PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY),
22 PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
23 PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
[all …]
|
| /openbmc/linux/drivers/video/fbdev/sis/ |
| H A D | init.h | 70 static const unsigned short ModeIndex_320x200[] = {0x59, 0x41, 0x00, 0x4f};
71 static const unsigned short ModeIndex_320x240[] = {0x50, 0x56, 0x00, 0x53};
72 static const unsigned short ModeIndex_320x240_FSTN[] = {0x5a, 0x5b, 0x00, 0x00}; /* FSTN */
73 static const unsigned short ModeIndex_400x300[] = {0x51, 0x57, 0x00, 0x54};
74 static const unsigned short ModeIndex_512x384[] = {0x52, 0x58, 0x00, 0x5c};
75 static const unsigned short ModeIndex_640x400[] = {0x2f, 0x5d, 0x00, 0x5e};
76 static const unsigned short ModeIndex_640x480[] = {0x2e, 0x44, 0x00, 0x62};
77 static const unsigned short ModeIndex_720x480[] = {0x31, 0x33, 0x00, 0x35};
78 static const unsigned short ModeIndex_720x576[] = {0x32, 0x34, 0x00, 0x36};
79 static const unsigned short ModeIndex_768x576[] = {0x5f, 0x60, 0x00, 0x61};
[all …]
|
| /openbmc/linux/Documentation/admin-guide/media/ |
| H A D | vimc.rst | 36 media-ctl -d platform:vimc -V '"Sensor A":0[fmt:SBGGR8_1X8/640x480]'
37 media-ctl -d platform:vimc -V '"Debayer A":0[fmt:SBGGR8_1X8/640x480]'
38 media-ctl -d platform:vimc -V '"Scaler":0[fmt:RGB888_1X24/640x480]'
39 media-ctl -d platform:vimc -V '"Scaler":0[crop:(100,50)/400x150]'
42 v4l2-ctl -z platform:vimc -d "Raw Capture 0" -v pixelformat=BA81
65 - entity 28: Lens A (0 pad, 0 link)
66 type V4L2 subdev subtype Lens flags 0
68 - entity 29: Lens B (0 pad, 0 link)
69 type V4L2 subdev subtype Lens flags 0
72 focus_absolute: 0
[all …]
|
| /openbmc/linux/include/linux/usb/ |
| H A D | usb338x.h | 19 #define SCRATCH 0x0b
36 #define USB3380_EP_CFG_MASK_IN ((0x3 << IN_ENDPOINT_TYPE) | \
38 #define USB3380_EP_CFG_MASK_OUT ((0x3 << OUT_ENDPOINT_TYPE) | \
45 #define DEVICE_CLASS 0
48 #define U1_SYSTEM_EXIT_LATENCY 0
51 #define U1_DEVICE_EXIT_LATENCY 0
55 #define USB_L1_LPM_SUPPORT 0
58 #define BEST_EFFORT_LATENCY_TOLERANCE 0
66 #define SERIAL_NUMBER_STRING_ENABLE 0
79 #define GPEP0_TIMEOUT_ENABLE 0
[all …]
|
| /openbmc/linux/drivers/gpu/drm/sti/ |
| H A D | sti_hda.c | 24 #define HDA_ANA_CFG 0x0000
25 #define HDA_ANA_SCALE_CTRL_Y 0x0004
26 #define HDA_ANA_SCALE_CTRL_CB 0x0008
27 #define HDA_ANA_SCALE_CTRL_CR 0x000C
28 #define HDA_ANA_ANC_CTRL 0x0010
29 #define HDA_ANA_SRC_Y_CFG 0x0014
30 #define HDA_COEFF_Y_PH1_TAP123 0x0018
31 #define HDA_COEFF_Y_PH1_TAP456 0x001C
32 #define HDA_COEFF_Y_PH2_TAP123 0x0020
33 #define HDA_COEFF_Y_PH2_TAP456 0x0024
[all …]
|
| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-shx3.c | 20 * This intentionally only registers SCIF ports 0, 1, and 3. SCIF 2
34 DEFINE_RES_MEM(0xffc30000, 0x100),
35 DEFINE_RES_IRQ(evt2irq(0x700)),
36 DEFINE_RES_IRQ(evt2irq(0x720)),
37 DEFINE_RES_IRQ(evt2irq(0x760)),
38 DEFINE_RES_IRQ(evt2irq(0x740)),
43 .id = 0,
57 DEFINE_RES_MEM(0xffc40000, 0x100),
58 DEFINE_RES_IRQ(evt2irq(0x780)),
59 DEFINE_RES_IRQ(evt2irq(0x7a0)),
[all …]
|
| /openbmc/linux/drivers/gpu/drm/loongson/ |
| H A D | lsdc_pixpll.c | 21 /* Byte 0 ~ Byte 3 */
22 unsigned div_out : 7; /* 6 : 0 Output clock divider */
78 {74250, 1280, 720, 60, 22, 49, 3}, /* 1280x720@60Hz */
79 /* 1280x720@50Hz */
147 * Return 0 if success, return -1 if not found.
157 for (i = 0; i < num; ++i) { in lsdc_pixpll_find()
165 return 0; in lsdc_pixpll_find()
189 * Return 0 if a set of parameter is found, otherwise return the error
204 return 0; in lsdc_pixel_pll_compute()
209 unsigned int diff = 0; in lsdc_pixel_pll_compute()
[all …]
|
| /openbmc/linux/drivers/video/fbdev/ |
| H A D | sm712fb.c | 71 .red = {16, 8, 0},
72 .green = {8, 8, 0},
73 .blue = {0, 8, 0},
78 .nonstd = 0,
88 .type_aux = 0,
89 .xpanstep = 0,
90 .ypanstep = 0,
91 .ywrapstep = 0,
102 {"0x301", 640, 480, 8},
103 {"0x303", 800, 600, 8},
[all …]
|
| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | r600_reg.h | 31 #define R600_PCIE_PORT_INDEX 0x0038
32 #define R600_PCIE_PORT_DATA 0x003c
34 #define R600_RCU_INDEX 0x0100
35 #define R600_RCU_DATA 0x0104
37 #define R600_UVD_CTX_INDEX 0xf4a0
38 #define R600_UVD_CTX_DATA 0xf4a4
40 #define R600_MC_VM_FB_LOCATION 0x2180
41 #define R600_MC_FB_BASE_MASK 0x0000FFFF
42 #define R600_MC_FB_BASE_SHIFT 0
43 #define R600_MC_FB_TOP_MASK 0xFFFF0000
[all …]
|
| /openbmc/linux/arch/sh/kernel/cpu/sh3/ |
| H A D | setup-sh7705.c | 20 UNUSED = 0,
36 INTC_VECT(PINT07, 0x700), INTC_VECT(PINT815, 0x720),
37 INTC_VECT(DMAC, 0x800), INTC_VECT(DMAC, 0x820),
38 INTC_VECT(DMAC, 0x840), INTC_VECT(DMAC, 0x860),
39 INTC_VECT(SCIF0, 0x880), INTC_VECT(SCIF0, 0x8a0),
40 INTC_VECT(SCIF0, 0x8e0),
41 INTC_VECT(SCIF2, 0x900), INTC_VECT(SCIF2, 0x920),
42 INTC_VECT(SCIF2, 0x960),
43 INTC_VECT(ADC_ADI, 0x980),
44 INTC_VECT(USB, 0xa20), INTC_VECT(USB, 0xa40),
[all …]
|
| /openbmc/linux/drivers/gpu/host1x/hw/ |
| H A D | hw_host1x01_sync.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x1ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x1ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
|
| H A D | hw_host1x02_sync.h | 29 * <x> value 'r' after being shifted to place its LSB at bit 0.
46 return 0x400 + id * REGISTER_STRIDE; in host1x_sync_syncpt_r()
52 return 0x40 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_cpu0_int_status_r()
58 return 0x60 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_disable_r()
64 return 0x68 + id * REGISTER_STRIDE; in host1x_sync_syncpt_thresh_int_enable_cpu0_r()
70 return 0x80 + channel * REGISTER_STRIDE; in host1x_sync_cf_setup_r()
76 return (r >> 0) & 0x3ff; in host1x_sync_cf_setup_base_v()
82 return (r >> 16) & 0x3ff; in host1x_sync_cf_setup_limit_v()
88 return 0xac; in host1x_sync_cmdproc_stop_r()
94 return 0xb0; in host1x_sync_ch_teardown_r()
[all …]
|
| /openbmc/u-boot/include/configs/ |
| H A D | tao3530.h | 79 "loadaddr=0x82000000\0" \
80 "console=ttyO2,115200n8\0" \
81 "mpurate=600\0" \
82 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
83 "tv_mode=omapfb.mode=tv:ntsc\0" \
84 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
85 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
86 "extra_options= \0" \
87 "mmcdev=0\0" \
88 "mmcroot=/dev/mmcblk0p2 rw\0" \
[all …]
|
| /openbmc/qemu/hw/cpu/ |
| H A D | arm11mpcore.c | 36 memory_region_add_subregion(&s->container, 0, in mpcore_priv_map_setup()
37 sysbus_mmio_get_region(scubusdev, 0)); in mpcore_priv_map_setup()
38 /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs in mpcore_priv_map_setup()
39 * at 0x200, 0x300... in mpcore_priv_map_setup()
41 for (i = 0; i < (s->num_cpu + 1); i++) { in mpcore_priv_map_setup()
42 hwaddr offset = 0x100 + (i * 0x100); in mpcore_priv_map_setup()
49 for (i = 0; i < (s->num_cpu + 1); i++) { in mpcore_priv_map_setup()
50 /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */ in mpcore_priv_map_setup()
51 hwaddr offset = 0x600 + i * 0x100; in mpcore_priv_map_setup()
54 memory_region_add_subregion(&s->container, offset + 0x20, in mpcore_priv_map_setup()
[all …]
|
| /openbmc/linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_mipi_dsi_regs.h | 11 #define LINKSR 0x010
13 #define LINKSR_HSBUSY (1 << 0)
18 #define TXVMSETR 0x180
19 #define TXVMSETR_SYNSEQ_PULSES (0 << 16)
24 #define TXVMSETR_VSEN_DIS (0 << 4)
26 #define TXVMSETR_HFPBPEN_DIS (0 << 2)
28 #define TXVMSETR_HBPBPEN_DIS (0 << 1)
29 #define TXVMSETR_HSABPEN_EN (1 << 0)
30 #define TXVMSETR_HSABPEN_DIS (0 << 0)
32 #define TXVMCR 0x190
[all …]
|