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/openbmc/u-boot/include/configs/
H A Dat91sam9m10g45ek.h38 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
46 #define CONFIG_SYS_SDRAM_BASE 0x70000000
47 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
70 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
73 #define CONFIG_SYS_MEMTEST_END 0x23e00000
77 #define CONFIG_ENV_OFFSET 0x140000
78 #define CONFIG_ENV_OFFSET_REDUND 0x100000
79 #define CONFIG_ENV_SIZE 0x20000
82 "nand read 0x70000000 0x200000 0x300000;" \
83 "bootm 0x70000000"
[all …]
H A Dls1088aqds.h18 #define CONFIG_SYS_MMC_ENV_DEV 0
20 #define CONFIG_ENV_SIZE 0x20000
21 #define CONFIG_ENV_OFFSET 0x500000
24 #define CONFIG_ENV_SECT_SIZE 0x40000
27 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
28 #define CONFIG_ENV_SECT_SIZE 0x40000
31 #define CONFIG_SYS_MMC_ENV_DEV 0
32 #define CONFIG_ENV_SIZE 0x2000
34 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
35 #define CONFIG_ENV_SECT_SIZE 0x20000
[all …]
H A Dcorvus.h59 #define CONFIG_SYS_SDRAM_SIZE 0x08000000
90 #define CONFIG_ENV_OFFSET 0x100000
91 #define CONFIG_ENV_OFFSET_REDUND 0x180000
95 "nand read 0x70000000 0x200000 0x300000;" \
96 "bootm 0x70000000"
102 SZ_4M, 0x1000)
105 #define CONFIG_SPL_TEXT_BASE 0x300000
117 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
118 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
138 #define CONFIG_SYS_AT91_PLLA 0x20c73f03
[all …]
/openbmc/linux/drivers/of/unittest-data/
H A Dtests-address.dtsi17 ranges = <0x70000000 0x70000000 0x50000000>,
18 <0x00000000 0xd0000000 0x20000000>;
19 dma-ranges = <0x0 0x20000000 0x40000000>;
22 reg = <0x70000000 0x1000>;
28 ranges = <0x0 0x0 0x80000000 0x0 0x100000>;
29 dma-ranges = <0x1 0x0 0x0 0x20 0x0>;
32 reg = <0x0 0x1000 0x0 0x1000>;
40 reg = <0x90000000 0x1000>;
41 ranges = <0x42000000 0x0 0x40000000 0x40000000 0x0 0x10000000>;
42 dma-ranges = <0x42000000 0x0 0x80000000 0x00000000 0x0 0x10000000>,
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65.dtsi54 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
57 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
58 <0x00 0x30800000 0x00 0x30800000 0x00 0x0bc00000>, /* MAIN NAVSS */
59 <0x00 0x70000000 0x00 0x70000000 0x00 0x00200000>, /* MSMC SRAM */
60 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
62 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
63 <0x00 0x40200000 0x00 0x40200000 0x00 0x00900100>,
64 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
[all …]
H A Dk3-am62p-main.dtsi10 reg = <0x00 0x70000000 0x00 0x10000>;
13 ranges = <0x00 0x00 0x70000000 0x10000>;
23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
25 <0x01 0x00000000 0x00 0x2000>, /* GICC */
26 <0x01 0x00010000 0x00 0x1000>, /* GICH */
27 <0x01 0x00020000 0x00 0x2000>; /* GICV */
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
49 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>;
[all …]
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
H A Dk3-am62.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-j721s2.dtsi29 #size-cells = <0>;
42 cpu0: cpu@0 {
44 reg = <0x000>;
47 i-cache-size = <0xc000>;
50 d-cache-size = <0x8000>;
58 reg = <0x001>;
61 i-cache-size = <0xc000>;
64 d-cache-size = <0x8000>;
75 cache-size = <0x100000>;
118 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/ocelot/
H A Docelot.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71010000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/luton/
H A Dluton.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x60000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x01000000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x70000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x00200000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x60070000)
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval.h17 #define MSCC_IO_ORIGIN1_OFFSET 0x70000000
18 #define MSCC_IO_ORIGIN1_SIZE 0x00200000
19 #define MSCC_IO_ORIGIN2_OFFSET 0x71000000
20 #define MSCC_IO_ORIGIN2_SIZE 0x01000000
21 #define BASE_CFG ((void __iomem *)0x70000000)
22 #define BASE_DEVCPU_GCB ((void __iomem *)0x71070000)
/openbmc/linux/arch/sparc/include/asm/
H A Dfbio.h10 #define CG6_FBC 0x70000000
11 #define CG6_TEC 0x70001000
12 #define CG6_BTREGS 0x70002000
13 #define CG6_FHC 0x70004000
14 #define CG6_THC 0x70005000
15 #define CG6_ROM 0x70006000
16 #define CG6_RAM 0x70016000
17 #define CG6_DHC 0x80000000
19 #define CG3_MMAP_OFFSET 0x4000000
22 #define TCX_RAM8BIT 0x00000000
[all …]
/openbmc/u-boot/tools/
H A Dk3_fit_atf.sh8 # usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
39 load = <0x70000000>;
40 entry = <0x70000000>;
49 load = <0x9e800000>;
50 entry = <0x9e800000>;
59 load = <0x80080000>;
60 entry = <0x80080000>;
/openbmc/linux/arch/arm/mach-tegra/
H A Diomap.h16 #define TEGRA_IRAM_BASE 0x40000000
19 #define TEGRA_ARM_PERIF_BASE 0x50040000
22 #define TEGRA_ARM_INT_DIST_BASE 0x50041000
25 #define TEGRA_TMR1_BASE 0x60005000
28 #define TEGRA_TMR2_BASE 0x60005008
31 #define TEGRA_TMRUS_BASE 0x60005010
34 #define TEGRA_TMR3_BASE 0x60005050
37 #define TEGRA_TMR4_BASE 0x60005058
40 #define TEGRA_CLK_RESET_BASE 0x60006000
43 #define TEGRA_FLOW_CTRL_BASE 0x60007000
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/phy/
H A Dphytbl_lcn.c10 0x00000000,
11 0x00000000,
12 0x00000000,
13 0x00000000,
14 0x00000000,
15 0x00000000,
16 0x00000000,
17 0x00000000,
18 0x00000004,
19 0x00000000,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dsifive,fu740-pcie.yaml94 reg = <0xe 0x00000000 0x0 0x80000000>,
95 <0xd 0xf0000000 0x0 0x10000000>,
96 <0x0 0x100d0000 0x0 0x1000>;
100 bus-range = <0x0 0xff>;
101 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
102 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
103 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */
104 … <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
105 num-lanes = <0x8>;
109 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dfbio.h13 #define FBTYPE_SUN1BW 0 /* mono */
58 #define FBIOGTYPE _IOR('F', 0, struct fbtype)
61 int index; /* first element (0 origin) */
124 #define FB_WID_SHARED_8 0
196 #define FB_CLUT_WAIT 0x00000001 /* Not yet implemented */
225 #define CG6_FBC 0x70000000
226 #define CG6_TEC 0x70001000
227 #define CG6_BTREGS 0x70002000
228 #define CG6_FHC 0x70004000
229 #define CG6_THC 0x70005000
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A DkuroboxHG.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x8000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
H A DkuroboxHD.dts37 #size-cells = <0>;
41 reg = <0x0>;
44 bus-frequency = <0>; /* Fixed by bootloader */
46 i-cache-size = <0x4000>;
47 d-cache-size = <0x4000>;
53 reg = <0x0 0x4000000>;
61 store-gathering = <0>; /* 0 == off, !0 == on */
62 reg = <0x80000000 0x100000>;
63 ranges = <0x80000000 0x80000000 0x70000000 /* pci mem space */
64 0xfc000000 0xfc000000 0x100000 /* EUMB */
[all …]
/openbmc/qemu/linux-user/sparc/
H A Dtarget_mman.h4 #define TARGET_MAP_NORESERVE 0x40
5 #define TARGET_MAP_LOCKED 0x100
6 #define TARGET_MAP_GROWSDOWN 0x0200
11 * _AC(0x0000000070000000,UL) : \
13 * But VA_EXCLUDE_END is > 0xffff800000000000UL which doesn't work
17 #define TASK_UNMAPPED_BASE 0x70000000
28 #define ELF_ET_DYN_BASE 0x78000000
30 #define ELF_ET_DYN_BASE 0x0000010000000000ull

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