Home
last modified time | relevance | path

Searched +full:0 +full:x68000 (Results 1 – 25 of 36) sorted by relevance

12

/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dimx-regs.h11 #define ROMCP_ARB_BASE_ADDR 0x00000000
12 #define ROMCP_ARB_END_ADDR 0x000FFFFF
15 #define GPU_2D_ARB_BASE_ADDR 0x02200000
16 #define GPU_2D_ARB_END_ADDR 0x02203FFF
17 #define OPENVG_ARB_BASE_ADDR 0x02204000
18 #define OPENVG_ARB_END_ADDR 0x02207FFF
20 #define CAAM_ARB_BASE_ADDR 0x00100000
21 #define CAAM_ARB_END_ADDR 0x00107FFF
22 #define GPU_ARB_BASE_ADDR 0x01800000
23 #define GPU_ARB_END_ADDR 0x01803FFF
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/cfg/
H A D8000.c20 #define IWL8000_NVM_VERSION 0x0a1d
23 #define IWL8260_DCCM_OFFSET 0x800000
24 #define IWL8260_DCCM_LEN 0x18000
25 #define IWL8260_DCCM2_OFFSET 0x880000
26 #define IWL8260_DCCM2_LEN 0x8000
27 #define IWL8260_SMEM_OFFSET 0x400000
28 #define IWL8260_SMEM_LEN 0x68000
97 .min_umac_error_event_table = 0x800000
H A D9000.c19 #define IWL9000_NVM_VERSION 0x0a1d
22 #define IWL9000_DCCM_OFFSET 0x800000
23 #define IWL9000_DCCM_LEN 0x18000
24 #define IWL9000_DCCM2_OFFSET 0x880000
25 #define IWL9000_DCCM2_LEN 0x8000
26 #define IWL9000_SMEM_OFFSET 0x400000
27 #define IWL9000_SMEM_LEN 0x68000
92 .mac_addr_from_csr = 0x380, \
95 .min_umac_error_event_table = 0x800000, \
96 .d3_debug_data_base_addr = 0x401000, \
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dmme0_qm_regs.h22 #define mmMME0_QM_GLBL_CFG0 0x68000
24 #define mmMME0_QM_GLBL_CFG1 0x68004
26 #define mmMME0_QM_GLBL_PROT 0x68008
28 #define mmMME0_QM_GLBL_ERR_CFG 0x6800C
30 #define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
32 #define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
34 #define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
36 #define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
38 #define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
40 #define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/hdcp/
H A Dhdcp_msg.c79 [HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
80 [HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
81 [HDCP_MESSAGE_ID_READ_PJ] = 0xA,
82 [HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
83 [HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
84 [HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
85 [HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
86 [HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
87 [HDCP_MESSAGE_ID_READ_VH_1] = 0x24,
88 [HDCP_MESSAGE_ID_READ_VH_2] = 0x28,
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_tv_regs.h12 #define TV_CTL _MMIO(0x68000)
20 # define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
31 # define TV_OVERSAMPLE_4X (0 << 18)
54 # define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
57 # define TV_FUSE_STATE_ENABLED (0 << 4)
63 # define TV_TEST_MODE_NORMAL (0 << 0)
65 # define TV_TEST_MODE_PATTERN_1 (1 << 0)
67 # define TV_TEST_MODE_PATTERN_2 (2 << 0)
69 # define TV_TEST_MODE_PATTERN_3 (3 << 0)
71 # define TV_TEST_MODE_PATTERN_4 (4 << 0)
[all …]
/openbmc/linux/drivers/parisc/
H A Dsuperio.c32 * Function 0 is an IDE controller. It is identical to a PC87415 IDE
54 * 0x5A: FDC, SP1, IDE1, SP2, IDE2, PAR, Reserved, P92
55 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
100 outb (OCW3_POLL,IC_PIC1+0); in superio_interrupt()
102 results = inb(IC_PIC1+0); in superio_interrupt()
105 * Bit 7: 1 = active Interrupt; 0 = no Interrupt pending in superio_interrupt()
107 * Bits 2-0: highest priority, active requesting interrupt ID (0-7) in superio_interrupt()
109 if ((results & 0x80) == 0) { in superio_interrupt()
118 local_irq = results & 0x0f; in superio_interrupt()
129 outb(OCW3_ISR,IC_PIC1+0); in superio_interrupt()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dt4240si-post.dtsi37 alloc-ranges = <0 0 0x10000 0>;
42 alloc-ranges = <0 0 0x10000 0>;
47 alloc-ranges = <0 0 0x10000 0>;
54 interrupts = <25 2 0 0>;
57 /* controller at 0x240000 */
59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
63 bus-range = <0x0 0xff>;
64 interrupts = <20 2 0 0>;
65 pcie@0 {
70 reg = <0 0 0 0 0>;
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp_ddc.c29 #define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/
30 #define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */
40 MOD_HDCP_MESSAGE_ID_READ_BKSV = 0,
81 [MOD_HDCP_MESSAGE_ID_READ_BKSV] = 0x0,
82 [MOD_HDCP_MESSAGE_ID_READ_RI_R0] = 0x8,
83 [MOD_HDCP_MESSAGE_ID_WRITE_AKSV] = 0x10,
84 [MOD_HDCP_MESSAGE_ID_WRITE_AINFO] = 0x15,
85 [MOD_HDCP_MESSAGE_ID_WRITE_AN] = 0x18,
86 [MOD_HDCP_MESSAGE_ID_READ_VH_X] = 0x20,
87 [MOD_HDCP_MESSAGE_ID_READ_VH_0] = 0x20,
[all …]
/openbmc/u-boot/cmd/aspeed/
H A Ddptest.c18 #define MAINVER 0
33 #define DBG_ERR 0x00000001 /* DBG_ERROR */
34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */
35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */
36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */
37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */
38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */
39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */
40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */
41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_3_0_2_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_3_0_0_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
31 …e regDAGB0_RDCLI0_BASE_IDX 0
32 …DAGB0_RDCLI1 0x0001
33 …e regDAGB0_RDCLI1_BASE_IDX 0
34 …DAGB0_RDCLI2 0x0002
35 …e regDAGB0_RDCLI2_BASE_IDX 0
36 …DAGB0_RDCLI3 0x0003
37 …e regDAGB0_RDCLI3_BASE_IDX 0
38 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_2_0_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_3_0_1_offset.h29 // base address: 0x68000
30 …DAGB0_RDCLI0 0x0000
32 …DAGB0_RDCLI1 0x0001
34 …DAGB0_RDCLI2 0x0002
36 …DAGB0_RDCLI3 0x0003
38 …DAGB0_RDCLI4 0x0004
40 …DAGB0_RDCLI5 0x0005
42 …DAGB0_RDCLI6 0x0006
44 …DAGB0_RDCLI7 0x0007
46 …DAGB0_RDCLI8 0x0008
[all …]
H A Dmmhub_9_1_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_9_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_1_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
29 …ne mmDAGB0_RDCLI0_BASE_IDX 0
30 …DAGB0_RDCLI1 0x0001
31 …ne mmDAGB0_RDCLI1_BASE_IDX 0
32 …DAGB0_RDCLI2 0x0002
33 …ne mmDAGB0_RDCLI2_BASE_IDX 0
34 …DAGB0_RDCLI3 0x0003
35 …ne mmDAGB0_RDCLI3_BASE_IDX 0
36 …DAGB0_RDCLI4 0x0004
[all …]
H A Dmmhub_2_3_0_offset.h27 // base address: 0x68000
28 …DAGB0_RDCLI0 0x0000
30 …DAGB0_RDCLI1 0x0001
32 …DAGB0_RDCLI2 0x0002
34 …DAGB0_RDCLI3 0x0003
36 …DAGB0_RDCLI4 0x0004
38 …DAGB0_RDCLI5 0x0005
40 …DAGB0_RDCLI6 0x0006
42 …DAGB0_RDCLI7 0x0007
44 …DAGB0_RDCLI8 0x0008
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]
/openbmc/linux/include/drm/display/
H A Ddrm_dp.h44 #define DP_MSA_MISC_SYNC_CLOCK (1 << 0)
46 #define DP_MSA_MISC_STEREO_NO_3D (0 << 9)
50 #define DP_MSA_MISC_6_BPC (0 << 5)
66 #define DP_MSA_MISC_COLOR_RGB _DP_MSA_MISC_COLOR(0, 0, 0, 0)
67 #define DP_MSA_MISC_COLOR_CEA_RGB _DP_MSA_MISC_COLOR(0, 0, 1, 0)
68 #define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED _DP_MSA_MISC_COLOR(0, 3, 0, 0)
69 #define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT _DP_MSA_MISC_COLOR(0, 3, 0, 1)
70 #define DP_MSA_MISC_COLOR_Y_ONLY _DP_MSA_MISC_COLOR(1, 0, 0, 0)
71 #define DP_MSA_MISC_COLOR_RAW _DP_MSA_MISC_COLOR(1, 1, 0, 0)
72 #define DP_MSA_MISC_COLOR_YCBCR_422_BT601 _DP_MSA_MISC_COLOR(0, 1, 1, 0)
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x4a000000 */
21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
/openbmc/linux/drivers/phy/microchip/
H A Dsparx5_serdes.c31 #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c
34 SPX5_SD10G28_CMU_MAIN = 0,
353 .cfg_en_adv = 0,
355 .cfg_en_dly = 0,
356 .cfg_tap_adv_3_0 = 0,
358 .cfg_tap_dly_4_0 = 0,
359 .cfg_eq_c_force_3_0 = 0xf,
368 .cfg_tap_adv_3_0 = 0,
370 .cfg_tap_dly_4_0 = 0x10,
371 .cfg_eq_c_force_3_0 = 0xf,
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sdx75.c67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
[all …]

12