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/openbmc/linux/drivers/clk/renesas/
H A Dr9a09g011-cpg.c19 #define RZV2M_SAMPLL4_CLK1 0x104
20 #define RZV2M_SAMPLL4_CLK2 0x108
24 #define DIV_A DDIV_PACK(0x200, 0, 3)
25 #define DIV_B DDIV_PACK(0x204, 0, 2)
26 #define DIV_D DDIV_PACK(0x204, 4, 2)
27 #define DIV_E DDIV_PACK(0x204, 8, 1)
28 #define DIV_W DDIV_PACK(0x328, 0, 3)
30 #define SEL_B SEL_PLL_PACK(0x214, 0, 1)
31 #define SEL_CSI0 SEL_PLL_PACK(0x330, 0, 1)
32 #define SEL_CSI4 SEL_PLL_PACK(0x330, 4, 1)
[all …]
/openbmc/linux/drivers/clk/visconti/
H A Dclkc-tmpv770x.c35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
[all …]
/openbmc/u-boot/board/aspeed/ast2600_dcscm/
H A Dast2600_dcscm.c8 #define SCU_BASE 0x1e6e2000
9 #define ESPI_BASE 0x1e6ee000
10 #define LPC_BASE 0x1e789000
11 #define LPC_HICR5 (LPC_BASE + 0x80)
12 #define LPC_HICR6 (LPC_BASE + 0x84)
13 #define LPC_SNPWADR (LPC_BASE + 0x90)
14 #define LPC_HICRB (LPC_BASE + 0x100)
15 #define GPIO_BASE 0x1e780000
20 #define HICR5_SEL80HGIO (0x1f << 24) /* Select 80hGIO */
21 #define SET_SEL80HGIO(x) ((x & 0x1f) << 24) /* Select 80hGIO Offset */
[all …]
/openbmc/u-boot/board/synopsys/axs10x/
H A Dconfig.mk9 --arc-id 0x53 \
10 --spi-flash-offset 0x200000 \
16 --arc-id 0x434 \
17 --spi-flash-offset 0x0 \
/openbmc/u-boot/drivers/pinctrl/aspeed/
H A Dpinctrl_ast2600.c29 int ret = 0; in ast2600_pinctrl_probe()
45 return 0; in ast2600_pinctrl_probe()
49 { 0x418, GENMASK(9, 8), 1 },
50 { 0x4B8, GENMASK(9, 8), 0 },
54 { 0x418, GENMASK(11, 10), 1 },
55 { 0x4B8, GENMASK(11, 10), 0 },
59 { 0x418, GENMASK(13, 12), 1 },
60 { 0x4B8, GENMASK(13, 12), 0 },
64 { 0x418, GENMASK(15, 14), 1 },
65 { 0x4B8, GENMASK(15, 14), 0 },
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmmdc.h9 #define MMDC0 0
12 #define MMDC_MDCTL 0x0
13 #define MMDC_MDPDC 0x4
14 #define MMDC_MDOTC 0x8
15 #define MMDC_MDCFG0 0xC
16 #define MMDC_MDCFG1 0x10
17 #define MMDC_MDCFG2 0x14
18 #define MMDC_MDMISC 0x18
19 #define MMDC_MDSCR 0x1C
20 #define MMDC_MDREF 0x20
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-pinfunc.h14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0
15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3
16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0
17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3
18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0
19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0
20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0
21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0
22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0
23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0
[all …]
H A Dimx8mp-pinfunc.h13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
H A Dimx8mq-pinfunc.h15 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
16 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
17 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
18 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
19 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
20 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
21 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
22 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
23 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
24 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra210_mixer.h13 #define TEGRA210_MIXER_RX1_SOFT_RESET 0x04
14 #define TEGRA210_MIXER_RX1_STATUS 0x10
15 #define TEGRA210_MIXER_RX1_CIF_CTRL 0x24
16 #define TEGRA210_MIXER_RX1_CTRL 0x28
17 #define TEGRA210_MIXER_RX1_PEAK_CTRL 0x2c
18 #define TEGRA210_MIXER_RX1_SAMPLE_COUNT 0x30
21 #define TEGRA210_MIXER_TX1_ENABLE 0x280
22 #define TEGRA210_MIXER_TX1_SOFT_RESET 0x284
23 #define TEGRA210_MIXER_TX1_STATUS 0x290
24 #define TEGRA210_MIXER_TX1_INT_STATUS 0x294
[all …]
/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-vbi.c25 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
26 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
27 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96, in decode_vps()
28 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2, in decode_vps()
29 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94, in decode_vps()
30 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0, in decode_vps()
31 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4, in decode_vps()
32 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0, in decode_vps()
33 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5, in decode_vps()
34 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1, in decode_vps()
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_lvds.h12 #define RK3288_LVDS_CH0_REG0 0x00
20 #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)
22 #define RK3288_LVDS_CH0_REG1 0x04
28 #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)
30 #define RK3288_LVDS_CH0_REG2 0x08
38 #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)
40 #define RK3288_LVDS_CH0_REG3 0x0c
41 #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff
43 #define RK3288_LVDS_CH0_REG4 0x10
49 #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)
[all …]
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h24 #define MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ 0x014 0x27C 0x000 0x0 0
25 #define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ 0x018 0x280 0x000 0x0 0
26 #define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF 0x01C 0x284 0x000 0x0 0
27 #define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B 0x020 0x288 0x000 0x0 0
28 #define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B 0x024 0x28C 0x000 0x0 0
29 #define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0
30 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0
31 #define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0
32 #define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0
33 #define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx18-av-vbi.c18 * 4 byte EAV code: 0xff 0x00 0x00 0xRP
20 * 3 byte Anc data preamble: 0x00 0xff 0xff
24 * 2 byte Internal DID: VBI-line-# 0x80
31 * 0xb0 (Task 0 VerticalBlank HorizontalBlank 0 0 0 0)
32 * 0xf0 (Task EvenField VerticalBlank HorizontalBlank 0 0 0 0)
36 * 0x90 (Task 0 0 HorizontalBlank 0 0 0 0)
37 * 0xd0 (Task EvenField 0 HorizontalBlank 0 0 0 0)
40 * 0x91 (1 0 010 0 !ActiveLine AncDataPresent)
41 * 0x55 (0 1 010 2ndField !ActiveLine AncDataPresent)
44 static const u8 sliced_vbi_did[2] = { 0x91, 0x55 };
[all …]
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_a80.c16 [CLK_SPI0] = GATE(0x430, BIT(31)),
17 [CLK_SPI1] = GATE(0x434, BIT(31)),
18 [CLK_SPI2] = GATE(0x438, BIT(31)),
19 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
23 [CLK_BUS_SPI1] = GATE(0x580, BIT(21)),
24 [CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
25 [CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
27 [CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1170-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
H A Dimx6sl-pinfunc.h13 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
14 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
15 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
16 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
17 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
18 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
19 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
20 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
21 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
22 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
14 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
15 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
16 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
17 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
18 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
19 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
20 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
21 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
22 #define MX53_PAD_KEY_COL0__GPIO4_6 0x024 0x34c 0x000 0x1 0x0
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sl-pinfunc.h17 #define MX6SL_PAD_AUD_MCLK__AUDIO_CLK_OUT 0x04c 0x2a4 0x000 0x0 0x0
18 #define MX6SL_PAD_AUD_MCLK__PWM4_OUT 0x04c 0x2a4 0x000 0x1 0x0
19 #define MX6SL_PAD_AUD_MCLK__ECSPI3_RDY 0x04c 0x2a4 0x6b4 0x2 0x0
20 #define MX6SL_PAD_AUD_MCLK__FEC_MDC 0x04c 0x2a4 0x000 0x3 0x0
21 #define MX6SL_PAD_AUD_MCLK__WDOG2_RESET_B_DEB 0x04c 0x2a4 0x000 0x4 0x0
22 #define MX6SL_PAD_AUD_MCLK__GPIO1_IO06 0x04c 0x2a4 0x000 0x5 0x0
23 #define MX6SL_PAD_AUD_MCLK__SPDIF_EXT_CLK 0x04c 0x2a4 0x7f4 0x6 0x0
24 #define MX6SL_PAD_AUD_RXC__AUD3_RXC 0x050 0x2a8 0x000 0x0 0x0
25 #define MX6SL_PAD_AUD_RXC__I2C1_SDA 0x050 0x2a8 0x720 0x1 0x0
26 #define MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x050 0x2a8 0x000 0x2 0x0
[all …]
H A Dimx53-pinfunc.h13 #define IMX_PAD_SION 0x40000000
18 #define MX53_PAD_GPIO_19__KPP_COL_5 0x020 0x348 0x840 0x0 0x0
19 #define MX53_PAD_GPIO_19__GPIO4_5 0x020 0x348 0x000 0x1 0x0
20 #define MX53_PAD_GPIO_19__CCM_CLKO 0x020 0x348 0x000 0x2 0x0
21 #define MX53_PAD_GPIO_19__SPDIF_OUT1 0x020 0x348 0x000 0x3 0x0
22 #define MX53_PAD_GPIO_19__RTC_CE_RTC_EXT_TRIG2 0x020 0x348 0x000 0x4 0x0
23 #define MX53_PAD_GPIO_19__ECSPI1_RDY 0x020 0x348 0x000 0x5 0x0
24 #define MX53_PAD_GPIO_19__FEC_TDATA_3 0x020 0x348 0x000 0x6 0x0
25 #define MX53_PAD_GPIO_19__SRC_INT_BOOT 0x020 0x348 0x000 0x7 0x0
26 #define MX53_PAD_KEY_COL0__KPP_COL_0 0x024 0x34c 0x000 0x0 0x0
[all …]
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drzg2l_mipi_dsi_regs.h14 #define DSIDPHYCTRL0 0x00
19 #define DSIDPHYCTRL0_EN_BGR BIT(0)
21 #define DSIDPHYTIM0 0x04
23 #define DSIDPHYTIM0_T_INIT(x) ((x) << 0)
25 #define DSIDPHYTIM1 0x08
29 #define DSIDPHYTIM1_TCLK_SETTLE(x) ((x) << 0)
31 #define DSIDPHYTIM2 0x0c
35 #define DSIDPHYTIM2_TCLK_ZERO(x) ((x) << 0)
37 #define DSIDPHYTIM3 0x10
41 #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-pinmux.yaml147 reg = <0x70000868 0x164>, /* Pad control registers */
148 <0x70003000 0x434>, /* Mux registers */
149 <0x70000820 0x8>; /* MIPI pad control */

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