Home
last modified time | relevance | path

Searched +full:0 +full:x43000000 (Results 1 – 25 of 75) sorted by relevance

123

/openbmc/linux/arch/mips/boot/dts/brcm/
H A Dbcm97435svmb.dts11 memory@0 {
13 reg = <0x00000000 0x10000000>,
14 <0x20000000 0x30000000>,
15 <0x90000000 0x40000000>;
135 brcm,scb-sizes = <0 0x40000000 0 0x40000000>;
136 dma-ranges = <0x43000000 0x00000000 0x00000000 0x00000000 0x0 0x10000000
137 0x43000000 0x00000000 0x10000000 0x20000000 0x0 0x30000000
138 0x43000000 0x00000000 0x40000000 0x90000000 0x0 0x40000000>;
H A Dbcm97425svmb.dts11 memory@0 {
13 reg = <0x00000000 0x10000000>,
14 <0x20000000 0x30000000>,
15 <0x90000000 0x40000000>;
119 flash@0 {
121 reg = <0>;
133 flash0.cfe@0 {
134 reg = <0x0 0x200000>;
138 reg = <0x200000 0x40000>;
142 reg = <0x240000 0x10000>;
[all …]
/openbmc/u-boot/board/sunxi/
H A DREADME.nand35 sunxi-fel write 0x4a000000 u-boot-dtb.bin
36 sunxi-fel write 0x43000000 spl/sunxi-spl-with-ecc.bin
39 sunxi-fel exe 0x4a000000
48 nand write.raw.noverify 0x43000000 0 40
49 nand write.raw.noverify 0x43000000 0x400000 40
52 nand write 0x4a000000 0x800000 0xc0000
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p-wakeup.dtsi11 reg = <0x00 0x43000000 0x00 0x20000>;
14 ranges = <0x00 0x00 0x43000000 0x20000>;
19 reg = <0x14 0x4>;
25 reg = <0x00 0x2b300000 0x00 0x100>;
28 clocks = <&k3_clks 114 0>;
H A Dk3-am62a.dtsi54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62p.dtsi53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
H A Dk3-am62-wakeup.dtsi11 reg = <0x00 0x43000000 0x00 0x20000>;
14 ranges = <0x0 0x00 0x43000000 0x20000>;
18 reg = <0x14 0x4>;
24 reg = <0x00 0x2b300000 0x00 0x100>;
27 clocks = <&k3_clks 114 0>;
34 reg = <0x00 0x2b200000 0x00 0x100>;
37 #size-cells = <0>;
46 reg = <0x00 0x2b1f0000 0x00 0x100>;
48 clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
56 reg = <0x00 0x2b000000 0x00 0x100>;
[all …]
H A Dk3-am62a-wakeup.dtsi11 reg = <0x00 0x43000000 0x00 0x20000>;
14 ranges = <0x00 0x00 0x43000000 0x20000>;
18 reg = <0x14 0x4>;
24 reg = <0x00 0x2b300000 0x00 0x100>;
27 clocks = <&k3_clks 114 0>;
34 reg = <0x00 0x2b200000 0x00 0x100>;
37 #size-cells = <0>;
46 reg = <0x00 0x2b1f0000 0x00 0x100>;
48 clocks = <&k3_clks 117 6> , <&k3_clks 117 0>;
57 reg = <0x00 0x2b000000 0x00 0x100>;
[all …]
H A Dk3-am64.dtsi53 ranges = <0x00 0x000f4000 0x00 0x000f4000 0x00 0x000002d0>, /* PINCTRL */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
57 <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
58 <0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
59 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
60 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x00000100>, /* Main RTI0 */
62 <0x00 0x0e010000 0x00 0x0e010000 0x00 0x00000100>, /* Main RTI1 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dcdns,cdns-pcie-host.yaml47 bus-range = <0x0 0xff>;
48 linux,pci-domain = <0>;
49 vendor-id = <0x17cd>;
50 device-id = <0x0200>;
52 reg = <0x0 0xfb000000 0x0 0x01000000>,
53 <0x0 0x41000000 0x0 0x00001000>;
56 ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
57 <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
58 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>;
60 #interrupt-cells = <0x1>;
[all …]
H A Dxilinx-versal-cpm.yaml53 const: 0
84 interrupts = <0 72 4>;
86 interrupt-map-mask = <0 0 0 7>;
87 interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
88 <0 0 0 2 &pcie_intc_0 1>,
89 <0 0 0 3 &pcie_intc_0 2>,
90 <0 0 0 4 &pcie_intc_0 3>;
91 bus-range = <0x00 0xff>;
92 ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
93 <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
[all …]
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dmicrochip,pcie-host.yaml49 0-3
53 pattern: '^fic[0-3]$'
84 const: 0
116 reg = <0x0 0x70000000 0x0 0x08000000>,
117 <0x0 0x43000000 0x0 0x00010000>;
124 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
125 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
126 <0 0 0 2 &pcie_intc0 1>,
127 <0 0 0 3 &pcie_intc0 2>,
128 <0 0 0 4 &pcie_intc0 3>;
[all …]
/openbmc/u-boot/include/configs/
H A Devb_ast2400.h11 #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000)
12 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000)
17 #define CONFIG_SYS_LOAD_ADDR 0x43000000
H A Dexynos7420-common.h40 #define CONFIG_IRAM_BASE 0x02100000
41 #define CONFIG_IRAM_SIZE 0x58000
47 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
71 func(MMC, mmc, 0) \
75 "bootm_size=0x10000000\0" \
76 "kernel_addr_r=0x42000000\0" \
77 "fdt_addr_r=0x43000000\0" \
78 "ramdisk_addr_r=0x43300000\0" \
79 "scriptaddr=0x50000000\0" \
80 "pxefile_addr_r=0x51000000\0"
[all …]
H A Dexynos5-common.h22 #define CONFIG_TRACE_EARLY_ADDR 0x50000000
29 #define S5P_CHECK_SLEEP 0x00000BAD
30 #define S5P_CHECK_DIDLE 0xBAD00000
31 #define S5P_CHECK_LPA 0xABAD0000
34 #define INFORM0_OFFSET 0x800
35 #define INFORM1_OFFSET 0x804
36 #define INFORM2_OFFSET 0x808
37 #define INFORM3_OFFSET 0x80c
40 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
46 #define COPY_BL2_FNPTR_ADDR 0x02020030
[all …]
/openbmc/u-boot/arch/arm/mach-k3/include/mach/
H A Dam6_hardware.h12 #define CTRL_MMR0_BASE 0x00100000
13 #define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
15 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_MASK GENMASK(3, 0)
16 #define CTRLMMR_MAIN_DEVSTAT_BOOTMODE_SHIFT 0
26 #define WKUP_CTRL_MMR0_BASE 0x43000000
27 #define MCU_CTRL_MMR0_BASE 0x40f00000
34 #define CTRL_MMR0_PARTITION_SIZE 0x4000
40 #define CTRLMMR_LOCK_KICK0 0x01008
41 #define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
42 #define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dfaraday,fttmr010.txt32 reg = <0x43000000 0x1000>;
/openbmc/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs-polarberry-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
H A Dmpfs-m100pfs-fabric.dtsi7 #clock-cells = <0>;
13 #clock-cells = <0>;
19 #address-cells = <0x3>;
20 #interrupt-cells = <0x1>;
21 #size-cells = <0x2>;
23 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
25 bus-range = <0x0 0x7f>;
28 interrupt-map = <0 0 0 1 &pcie_intc 0>,
29 <0 0 0 2 &pcie_intc 1>,
30 <0 0 0 3 &pcie_intc 2>,
[all …]
H A Dmpfs-icicle-kit-fabric.dtsi10 reg = <0x0 0x40000000 0x0 0xF0>;
11 microchip,sync-update-mask = /bits/ 32 <0>;
19 reg = <0x0 0x40000200 0x0 0x100>;
21 #size-cells = <0>;
31 #address-cells = <0x3>;
32 #interrupt-cells = <0x1>;
33 #size-cells = <0x2>;
35 reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
37 bus-range = <0x0 0x7f>;
40 interrupt-map = <0 0 0 1 &pcie_intc 0>,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/bluetooth/
H A Dbrcm,bcm4377-bluetooth.yaml70 reg = <0xa0000000 0x1000000>;
72 ranges = <0x43000000 0x6 0xa0000000 0xa0000000 0x0 0x20000000>;
74 bluetooth@0,1 {
76 reg = <0x100 0x0 0x0 0x0 0x0>;
/openbmc/qemu/docs/system/arm/
H A Dorangepi.rst152 -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
160 -device usb-storage,bus=usb-bus.0,drive=stick
204 => ext2load mmc 0 0x42000000 zImage
205 => ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
206 => bootz 0x42000000 - 0x43000000
250 …=> setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload mmc 0:1 ${fdt_addr_r} ${fdt…
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]

123