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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dimxrt1050-clock.yaml54 reg = <0x400fc000 0x4000>;
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050.dtsi19 #clock-cells = <0>;
25 #clock-cells = <0>;
33 reg = <0x40184000 0x4000>;
42 reg = <0x401f8000 0x4000>;
43 fsl,mux_mask = <0x7>;
48 reg = <0x400d8000 0x4000>;
53 reg = <0x400fc000 0x4000>;
75 reg = <0x400e8000 0x4000>,
76 <0x400ec000 0x4000>;
78 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>,
[all …]
/openbmc/qemu/hw/arm/
H A Dstellaris.c38 #define GPIO_A 0
46 #define BP_OLED_I2C 0x01
47 #define BP_OLED_SSI 0x02
48 #define BP_GAMEPAD 0x04
60 * Register 13 .. 17: Device Capabilities 0 .. 4 (DC0 .. DC4).
127 qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0); in ssys_update()
131 0x31c0, /* 1 Mhz */
132 0x1ae0, /* 1.8432 Mhz */
133 0x18c0, /* 2 Mhz */
134 0xd573, /* 2.4576 Mhz */
[all …]