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Searched +full:0 +full:x3800c (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Didt,32434-pic.yaml43 reg = <0x3800c 0x0c>;
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-qcm2290.c46 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
61 .enable_reg = 0x79000,
62 .enable_mask = BIT(0),
75 { 0x1, 2 },
80 .offset = 0x0,
95 .offset = 0x1000,
98 .enable_reg = 0x79000,
113 .l = 0x3c,
114 .alpha = 0x0,
[all …]
H A Dgcc-sm6115.c50 { 500000000, 1250000000, 0 },
58 .offset = 0x0,
63 .enable_reg = 0x79000,
64 .enable_mask = BIT(0),
77 { 0x1, 2 },
82 .offset = 0x0,
97 { 0x0, 1 },
102 .offset = 0x0,
118 .l = 0x3c,
119 .vco_val = 0x1 << 20,
[all …]
H A Dgcc-sm6375.c54 { 249600000, 2000000000, 0 },
58 { 595200000, 3600000000UL, 0 },
62 .offset = 0x0,
65 .enable_reg = 0x79000,
66 .enable_mask = BIT(0),
79 { 0x1, 2 },
84 .offset = 0x0,
101 { 0x3, 3 },
106 .offset = 0x0,
123 .offset = 0x1000,
[all …]
H A Dgcc-sm6125.c42 .offset = 0x0,
45 .enable_reg = 0x79000,
46 .enable_mask = BIT(0),
85 .offset = 0x3000,
88 .enable_reg = 0x79000,
102 .offset = 0x4000,
105 .enable_reg = 0x79000,
119 .offset = 0x5000,
122 .enable_reg = 0x79000,
136 .offset = 0x6000,
[all …]
H A Dgcc-ipq5332.c51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
78 .offset = 0x20000,
91 .offset = 0x21000,
94 .enable_reg = 0xb000,
106 .offset = 0x21000,
119 .offset = 0x22000,
122 .enable_reg = 0xb000,
145 .offset = 0x22000,
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h26 // base address: 0x0
27 … 0x0000 // duplicate
28 … 0x0002 // duplicate
29 … 0x0004 // duplicate
30 … 0x0006 // duplicate
31 … 0x0008 // duplicate
32 … 0x0009 // duplicate
33 … 0x000a // duplicate
34 … 0x000b // duplicate
35 … 0x000c // duplicate
[all …]