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/openbmc/linux/arch/arm64/boot/dts/arm/
H A Dfoundation-v8-gicv3.dtsi13 ranges = <0x0 0x0 0x2f000000 0x100000>;
15 reg = <0x0 0x2f000000 0x0 0x10000>,
16 <0x0 0x2f100000 0x0 0x200000>,
17 <0x0 0x2c000000 0x0 0x2000>,
18 <0x0 0x2c010000 0x0 0x2000>,
19 <0x0 0x2c02f000 0x0 0x2000>;
26 reg = <0x20000 0x20000>;
H A Dfvp-base-revc.dts15 /memreserve/ 0x80000000 0x00010000;
43 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0 0x000>;
50 i-cache-size = <0x8000>;
53 d-cache-size = <0x8000>;
61 reg = <0x0 0x100>;
63 i-cache-size = <0x8000>;
66 d-cache-size = <0x8000>;
74 reg = <0x0 0x200>;
[all …]
/openbmc/u-boot/include/configs/
H A Dvexpress_aemv8a.h23 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
25 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
31 #define V2M_PA_CS0 0x00000000
32 #define V2M_PA_CS1 0x14000000
33 #define V2M_PA_CS2 0x18000000
34 #define V2M_PA_CS3 0x1c000000
35 #define V2M_PA_CS4 0x0c000000
36 #define V2M_PA_CS5 0x10000000
43 #define V2M_BASE 0x80000000
52 #define V2M_UART0 0x7ff80000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml33 enum: [ 0, 1, 2 ]
46 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
51 SPI interrupts are in the range [0-987]. PPI interrupts are in the
52 range [0-15]. Extended SPI interrupts are in the range [0-1023].
53 Extended PPI interrupts are in the range [0-127].
56 bits[3:0] trigger type and level flags.
68 of 0 if present.
83 ARMv8.0 architecture such as Cortex-A32, A34, A35, A53, A57, A72 and
99 multipleOf: 0x10000
100 exclusiveMinimum: 0
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