/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/ |
H A D | diu.txt | 20 reg = <0x2c000 100>; 28 reg = <0x2100 0x100>; 29 interrupts = <64 0x8>;
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/openbmc/linux/Documentation/devicetree/bindings/slimbus/ |
H A D | qcom,slim-ngd.yaml | 32 const: 0 49 "^slim@[0-9a-f]+$": 79 reg = <0x171c0000 0x2c000>; 84 iommus = <&apps_smmu 0x1806 0x0>; 86 #size-cells = <0>; 91 #size-cells = <0>; 93 codec@1,0 { 95 reg = <1 0>; 104 #clock-cells = <0>;
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/openbmc/u-boot/arch/arm/include/asm/arch-mx6/ |
H A D | imx-regs.h | 11 #define ROMCP_ARB_BASE_ADDR 0x00000000 12 #define ROMCP_ARB_END_ADDR 0x000FFFFF 15 #define GPU_2D_ARB_BASE_ADDR 0x02200000 16 #define GPU_2D_ARB_END_ADDR 0x02203FFF 17 #define OPENVG_ARB_BASE_ADDR 0x02204000 18 #define OPENVG_ARB_END_ADDR 0x02207FFF 20 #define CAAM_ARB_BASE_ADDR 0x00100000 21 #define CAAM_ARB_END_ADDR 0x00107FFF 22 #define GPU_ARB_BASE_ADDR 0x01800000 23 #define GPU_ARB_END_ADDR 0x01803FFF [all …]
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/openbmc/linux/arch/powerpc/boot/dts/fsl/ |
H A D | b4si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x200000 */ 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 71 reg = <0 0 0 0 0>; 72 interrupts = <20 2 0 0>; [all …]
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H A D | t2081si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t2080-pcie", "fsl,qoriq-pcie-v3.0", "fsl,qoriq-pcie"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 66 pcie@0 { 67 reg = <0 0 0 0 0>; [all …]
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H A D | t4240si-post.dtsi | 37 alloc-ranges = <0 0 0x10000 0>; 42 alloc-ranges = <0 0 0x10000 0>; 47 alloc-ranges = <0 0 0x10000 0>; 54 interrupts = <25 2 0 0>; 57 /* controller at 0x240000 */ 59 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0"; 63 bus-range = <0x0 0xff>; 64 interrupts = <20 2 0 0>; 65 pcie@0 { 70 reg = <0 0 0 0 0>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | qcom,ipa.yaml | 216 qcom,local-pid = <0>; 238 iommus = <&apps_smmu 0x440 0x0>, 239 <&apps_smmu 0x442 0x0>; 240 reg = <0x1e40000 0x7000>, 241 <0x1e47000 0x2000>, 242 <0x1e04000 0x2c000>; 249 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 260 <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 261 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, 262 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; [all …]
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/openbmc/linux/arch/powerpc/boot/dts/ |
H A D | mpc8308rdb.dts | 26 #size-cells = <0>; 28 PowerPC,8308@0 { 30 reg = <0x0>; 35 timebase-frequency = <0>; // from bootloader 36 bus-frequency = <0>; // from bootloader 37 clock-frequency = <0>; // from bootloader 43 reg = <0x00000000 0x08000000>; // 128MB at 0 50 reg = <0xe0005000 0x1000>; 51 interrupts = <77 0x8>; 57 ranges = <0x0 0x0 0xfe000000 0x00800000 [all …]
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H A D | mpc8308_p1m.dts | 25 #size-cells = <0>; 27 PowerPC,8308@0 { 29 reg = <0x0>; 34 timebase-frequency = <0>; // from bootloader 35 bus-frequency = <0>; // from bootloader 36 clock-frequency = <0>; // from bootloader 42 reg = <0x00000000 0x08000000>; // 128MB at 0 49 reg = <0xe0005000 0x1000>; 50 interrupts = <77 0x8>; 53 ranges = <0x0 0x0 0xfc000000 0x04000000 [all …]
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/openbmc/linux/drivers/net/ethernet/marvell/octeon_ep/ |
H A D | octep_regs_cn9k_pf.h | 12 #define CN93_RST_BOOT 0x000087E006001600ULL 13 #define CN93_RST_CORE_DOMAIN_W1S 0x000087E006001820ULL 14 #define CN93_RST_CORE_DOMAIN_W1C 0x000087E006001828ULL 16 #define CN93_CONFIG_XPANSION_BAR 0x38 17 #define CN93_CONFIG_PCIE_CAP 0x70 18 #define CN93_CONFIG_PCIE_DEVCAP 0x74 19 #define CN93_CONFIG_PCIE_DEVCTL 0x78 20 #define CN93_CONFIG_PCIE_LINKCAP 0x7C 21 #define CN93_CONFIG_PCIE_LINKCTL 0x80 22 #define CN93_CONFIG_PCIE_SLOTCAP 0x84 [all …]
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/ |
H A D | dpu_9_0_sm8550.h | 12 .max_mixer_blendstages = 0xb, 24 .base = 0, .len = 0x494, 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, [all …]
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/openbmc/linux/include/linux/soundwire/ |
H A D | sdw_intel.h | 14 #define SDW_SHIM_BASE 0x2C000 15 #define SDW_ALH_BASE 0x2C800 16 #define SDW_SHIM_BASE_ACE 0x38000 17 #define SDW_ALH_BASE_ACE 0x24000 18 #define SDW_LINK_BASE 0x30000 19 #define SDW_LINK_SIZE 0x10000 23 #define SDW_SHIM_LCAP 0x0 24 #define SDW_SHIM_LCAP_LCOUNT_MASK GENMASK(2, 0) 27 #define SDW_SHIM_LCTL 0x4 29 #define SDW_SHIM_LCTL_SPA BIT(0) [all …]
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/openbmc/linux/drivers/gpu/drm/lima/ |
H A D | lima_device.c | 52 LIMA_IP_DESC(pmu, false, false, 0x02000, 0x02000, pmu, "pmu"), 53 LIMA_IP_DESC(l2_cache0, true, true, 0x01000, 0x10000, l2_cache, NULL), 54 LIMA_IP_DESC(l2_cache1, false, true, -1, 0x01000, l2_cache, NULL), 55 LIMA_IP_DESC(l2_cache2, false, false, -1, 0x11000, l2_cache, NULL), 56 LIMA_IP_DESC(gp, true, true, 0x00000, 0x00000, gp, "gp"), 57 LIMA_IP_DESC(pp0, true, true, 0x08000, 0x08000, pp, "pp0"), 58 LIMA_IP_DESC(pp1, false, false, 0x0A000, 0x0A000, pp, "pp1"), 59 LIMA_IP_DESC(pp2, false, false, 0x0C000, 0x0C000, pp, "pp2"), 60 LIMA_IP_DESC(pp3, false, false, 0x0E000, 0x0E000, pp, "pp3"), 61 LIMA_IP_DESC(pp4, false, false, -1, 0x28000, pp, "pp4"), [all …]
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/openbmc/u-boot/include/configs/ |
H A D | MPC8610HPCD.h | 14 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ 20 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) 26 #define CONFIG_SYS_DIAG_ADDR 0xff800000 33 #define CONFIG_SYS_SCRATCH_VA 0xc0000000 53 #define L2_INIT 0 54 #define L2_ENABLE (L2CR_L2E |0x00100000 ) 57 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) 60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 61 #define CONFIG_SYS_MEMTEST_END 0x00400000 67 #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ [all …]
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/openbmc/linux/drivers/clk/qcom/ |
H A D | gcc-sdx55.c | 33 { 249600000, 2000000000, 0 }, 37 .offset = 0x0, 42 .enable_reg = 0x6d000, 43 .enable_mask = BIT(0), 56 { 0x0, 1 }, 57 { 0x1, 2 }, 58 { 0x3, 4 }, 59 { 0x7, 8 }, 64 .offset = 0x0, 81 .offset = 0x76000, [all …]
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H A D | gcc-msm8916.c | 45 .l_reg = 0x21004, 46 .m_reg = 0x21008, 47 .n_reg = 0x2100c, 48 .config_reg = 0x21010, 49 .mode_reg = 0x21000, 50 .status_reg = 0x2101c, 63 .enable_reg = 0x45000, 64 .enable_mask = BIT(0), 76 .l_reg = 0x20004, 77 .m_reg = 0x20008, [all …]
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H A D | gcc-msm8996.c | 49 .offset = 0x00000, 52 .enable_reg = 0x52000, 53 .enable_mask = BIT(0), 79 .offset = 0x00000, 94 .enable_reg = 0x5200c, 95 .enable_mask = BIT(0), 111 .enable_reg = 0x5200c, 126 .offset = 0x77000, 129 .enable_reg = 0x52000, 143 .offset = 0x77000, [all …]
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H A D | gcc-msm8998.c | 27 #define GCC_MMSS_MISC 0x0902C 28 #define GCC_GPU_MISC 0x71028 31 { 250000000, 2000000000, 0 }, 36 .offset = 0x0, 41 .enable_reg = 0x52000, 42 .enable_mask = BIT(0), 55 .offset = 0x0, 68 .offset = 0x0, 81 .offset = 0x0, 94 .offset = 0x0, [all …]
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/openbmc/linux/drivers/rapidio/devices/ |
H A D | tsi721.h | 13 DBG_NONE = 0, 14 DBG_INIT = BIT(0), /* driver init */ 26 DBG_ALL = ~0, 36 } while (0) 53 #define DEFAULT_HOPCOUNT 0xff 54 #define DEFAULT_DESTID 0xff 57 #define PCI_DEVICE_ID_TSI721 0x80ab 59 #define BAR_0 0 67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */ 68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */ [all …]
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/openbmc/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-sdx55.dtsi | 20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>; 25 reg = <0 0>; 31 #clock-cells = <0>; 38 #clock-cells = <0>; 44 #clock-cells = <0>; 51 #size-cells = <0>; 53 cpu0: cpu@0 { 56 reg = <0x0>; 108 reg = <0x8fc00000 0x80000>; 113 reg = <0x8fc80000 0x40000>; [all …]
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/ |
H A D | regs.h | 6 #define MT_HW_REV 0x1000 7 #define MT_HW_CHIPID 0x1008 8 #define MT_TOP_MISC2 0x1134 10 #define MT_MCU_BASE 0x2000 13 #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500) 14 #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0) 17 #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504) 18 #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0) 21 #define MT_HIF_BASE 0x4000 24 #define MT_INT_SOURCE_CSR MT_HIF(0x200) [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra7-l4.dtsi | 1 &l4_cfg { /* 0x4a000000 */ 4 clocks = <&l4cfg_clkctrl DRA7_L4CFG_L4_CFG_CLKCTRL 0>; 6 reg = <0x4a000000 0x800>, 7 <0x4a000800 0x800>, 8 <0x4a001000 0x1000>; 12 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */ 13 <0x00100000 0x4a100000 0x100000>, /* segment 1 */ 14 <0x00200000 0x4a200000 0x100000>; /* segment 2 */ 17 segment@0 { /* 0x4a000000 */ 21 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */ [all …]
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | sdm845.dtsi | 77 #clock-cells = <0>; 84 #clock-cells = <0>; 91 #size-cells = <0>; 93 CPU0: cpu@0 { 96 reg = <0x0 0x0>; 97 clocks = <&cpufreq_hw 0>; 101 qcom,freq-domain = <&cpufreq_hw 0>; 125 reg = <0x0 0x100>; 126 clocks = <&cpufreq_hw 0>; 130 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
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H A D | msm8996.dtsi | 28 #clock-cells = <0>; 35 #clock-cells = <0>; 43 #size-cells = <0>; 45 CPU0: cpu@0 { 48 reg = <0x0 0x0>; 52 clocks = <&kryocc 0>; 67 reg = <0x0 0x1>; 71 clocks = <&kryocc 0>; 81 reg = <0x0 0x100>; 100 reg = <0x0 0x101>; [all …]
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/openbmc/linux/tools/perf/util/ |
H A D | machine.c | 65 for (i = 0; i < THREADS__TABLE_SIZE; i++) { in machine__threads_init() 69 threads->nr = 0; in machine__threads_init() 98 machine->pid) < 0) in machine__set_mmap_name() 101 return machine->mmap_name ? 0 : -ENOMEM; in machine__set_mmap_name() 109 thread__set_comm(thread, comm, 0); in thread__set_guest_comm() 116 memset(machine, 0, sizeof(*machine)); in machine__init() 131 machine->id_hdr_size = 0; in machine__init() 134 machine->kernel_start = 0; in machine__init() 156 err = 0; in machine__init() 164 return 0; in machine__init() [all …]
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