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/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/
H A Dhclge_ptp.h14 #define HCLGE_PTP_REG_OFFSET 0x29000
16 #define HCLGE_PTP_TX_TS_SEQID_REG 0x0
17 #define HCLGE_PTP_TX_TS_NSEC_REG 0x4
18 #define HCLGE_PTP_TX_TS_NSEC_MASK GENMASK(29, 0)
19 #define HCLGE_PTP_TX_TS_SEC_L_REG 0x8
20 #define HCLGE_PTP_TX_TS_SEC_H_REG 0xC
21 #define HCLGE_PTP_TX_TS_SEC_H_MASK GENMASK(15, 0)
22 #define HCLGE_PTP_TX_TS_CNT_REG 0x30
24 #define HCLGE_PTP_TIME_SEC_H_REG 0x50
25 #define HCLGE_PTP_TIME_SEC_H_MASK GENMASK(15, 0)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,lpass-cpu.yaml78 const: 0
81 "^dai-link@[0-9a-f]+$":
254 reg = <0 0x62d87000 0 0x68000>,
255 <0 0x62f00000 0 0x29000>;
258 iommus = <&apps_smmu 0x1020 0>,
259 <&apps_smmu 0x1032 0>;
260 power-domains = <&lpass_hm 0>;
273 interrupts = <0 160 1>,
274 <0 268 1>;
280 #size-cells = <0>;
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-nsp.dtsi54 #size-cells = <0>;
56 cpu0: cpu@0 {
60 reg = <0x0>;
68 secondary-boot-reg = <0xffff0fec>;
69 reg = <0x1>;
82 ranges = <0x00000000 0x19000000 0x00023000>;
86 a9pll: arm_clk@0 {
87 #clock-cells = <0>;
90 reg = <0x00000 0x1000>;
95 reg = <0x20200 0x100>;
[all …]
/openbmc/linux/drivers/rapidio/devices/
H A Dtsi721.h13 DBG_NONE = 0,
14 DBG_INIT = BIT(0), /* driver init */
26 DBG_ALL = ~0,
36 } while (0)
53 #define DEFAULT_HOPCOUNT 0xff
54 #define DEFAULT_DESTID 0xff
57 #define PCI_DEVICE_ID_TSI721 0x80ab
59 #define BAR_0 0
67 #define TSI721_MAINT_WIN 0 /* Window for outbound maintenance requests */
68 #define IDB_QUEUE 0 /* Inbound Doorbell Queue to use */
[all …]
/openbmc/linux/lib/
H A Dkunit_iov_iter.c26 { 0x00002, 0x00002 },
27 { 0x00027, 0x03000 },
28 { 0x05193, 0x18794 },
29 { 0x20000, 0x20000 },
30 { 0x20000, 0x24000 },
31 { 0x24000, 0x27001 },
32 { 0x29000, 0xffffb },
33 { 0xffffd, 0xffffe },
39 return x & 0xff; in pattern()
78 size_t size = 0; in iov_kunit_load_kvec()
[all …]
/openbmc/linux/drivers/net/wireless/intersil/orinoco/
H A Dhw.c34 {110, 1, 3, 15}, /* Entry 0 is the default */
35 {10, 0, 1, 1},
37 {20, 0, 2, 2},
39 {55, 0, 4, 4},
41 {110, 0, 5, 8},
52 if (nic_id->id < 0x8000) in determine_firmware_type()
54 else if (nic_id->id == 0x8000 && nic_id->major == 0) in determine_firmware_type()
96 *hw_ver = (((nic_id.id & 0xff) << 24) | in determine_fw_capabilities()
97 ((nic_id.variant & 0xff) << 16) | in determine_fw_capabilities()
98 ((nic_id.major & 0xff) << 8) | in determine_fw_capabilities()
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-sdx75.c67 .offset = 0x0,
70 .enable_reg = 0x7d000,
71 .enable_mask = BIT(0),
84 { 0x1, 2 },
89 .offset = 0x0,
106 .offset = 0x4000,
109 .enable_reg = 0x7d000,
123 .offset = 0x5000,
126 .enable_reg = 0x7d000,
140 .offset = 0x6000,
[all …]
H A Dgcc-msm8916.c45 .l_reg = 0x21004,
46 .m_reg = 0x21008,
47 .n_reg = 0x2100c,
48 .config_reg = 0x21010,
49 .mode_reg = 0x21000,
50 .status_reg = 0x2101c,
63 .enable_reg = 0x45000,
64 .enable_mask = BIT(0),
76 .l_reg = 0x20004,
77 .m_reg = 0x20008,
[all …]
H A Dgcc-msm8996.c49 .offset = 0x00000,
52 .enable_reg = 0x52000,
53 .enable_mask = BIT(0),
79 .offset = 0x00000,
94 .enable_reg = 0x5200c,
95 .enable_mask = BIT(0),
111 .enable_reg = 0x5200c,
126 .offset = 0x77000,
129 .enable_reg = 0x52000,
143 .offset = 0x77000,
[all …]
H A Dgcc-msm8998.c27 #define GCC_MMSS_MISC 0x0902C
28 #define GCC_GPU_MISC 0x71028
31 { 250000000, 2000000000, 0 },
36 .offset = 0x0,
41 .enable_reg = 0x52000,
42 .enable_mask = BIT(0),
55 .offset = 0x0,
68 .offset = 0x0,
81 .offset = 0x0,
94 .offset = 0x0,
[all …]
H A Dgcc-ipq5018.c61 .offset = 0x21000,
64 .enable_reg = 0x0b000,
65 .enable_mask = BIT(0),
76 .offset = 0x4a000,
79 .enable_reg = 0x0b000,
91 .offset = 0x24000,
94 .enable_reg = 0x0b000,
106 .offset = 0x25000,
109 .enable_reg = 0x0b000,
121 .offset = 0x21000,
[all …]
H A Dgcc-ipq5332.c51 .offset = 0x20000,
54 .enable_reg = 0xb000,
55 .enable_mask = BIT(0),
78 .offset = 0x20000,
91 .offset = 0x21000,
94 .enable_reg = 0xb000,
106 .offset = 0x21000,
119 .offset = 0x22000,
122 .enable_reg = 0xb000,
145 .offset = 0x22000,
[all …]
H A Dgcc-msm8939.c53 .l_reg = 0x21004,
54 .m_reg = 0x21008,
55 .n_reg = 0x2100c,
56 .config_reg = 0x21010,
57 .mode_reg = 0x21000,
58 .status_reg = 0x2101c,
71 .enable_reg = 0x45000,
72 .enable_mask = BIT(0),
84 .l_reg = 0x20004,
85 .m_reg = 0x20008,
[all …]
H A Dgcc-ipq9574.c55 { P_XO, 0 },
67 .offset = 0x20000,
70 .enable_reg = 0x0b000,
71 .enable_mask = BIT(0),
95 .offset = 0x20000,
109 .offset = 0x22000,
112 .enable_reg = 0x0b000,
124 .offset = 0x22000,
138 .offset = 0x21000,
141 .enable_reg = 0x0b000,
[all …]
H A Dgcc-ipq6018.c50 .offset = 0x21000,
53 .enable_reg = 0x0b000,
54 .enable_mask = BIT(0),
79 .offset = 0x21000,
98 { P_XO, 0 },
104 .offset = 0x25000,
108 .enable_reg = 0x0b000,
122 .offset = 0x25000,
136 .offset = 0x37000,
139 .enable_reg = 0x0b000,
[all …]
H A Dgcc-ipq8074.c52 .offset = 0x21000,
55 .enable_reg = 0x0b000,
56 .enable_mask = BIT(0),
82 .offset = 0x21000,
95 .offset = 0x4a000,
98 .enable_reg = 0x0b000,
114 .offset = 0x4a000,
127 .offset = 0x24000,
130 .enable_reg = 0x0b000,
146 .offset = 0x24000,
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap4-l4.dtsi2 &l4_cfg { /* 0x4a000000 */
5 clocks = <&l4_cfg_clkctrl OMAP4_L4_CFG_CLKCTRL 0>;
7 reg = <0x4a000000 0x800>,
8 <0x4a000800 0x800>,
9 <0x4a001000 0x1000>;
13 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
14 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
15 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
16 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
17 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_dump.h22 #define DRV_DUMP_XSTORM_WAITP_ADDRESS 0x2b8a80
23 #define DRV_DUMP_TSTORM_WAITP_ADDRESS 0x1b8a80
24 #define DRV_DUMP_USTORM_WAITP_ADDRESS 0x338a80
25 #define DRV_DUMP_CSTORM_WAITP_ADDRESS 0x238a80
45 #define BNX2X_DUMP_VERSION 0x61111111
65 static const u32 page_vals_e2[] = {0, 128};
68 {0x58000, 4608, DUMP_CHIP_E2, 0x30}
74 static const u32 page_vals_e3[] = {0, 128};
77 {0x58000, 4608, DUMP_CHIP_E3A0 | DUMP_CHIP_E3B0, 0x30}
81 { 0x2000, 1, 0x1f, 0xfff},
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Devergreen.c49 #define DC_HPDx_CONTROL(x) (DC_HPD1_CONTROL + (x * 0xc))
50 #define DC_HPDx_INT_CONTROL(x) (DC_HPD1_INT_CONTROL + (x * 0xc))
51 #define DC_HPDx_INT_STATUS_REG(x) (DC_HPD1_INT_STATUS + (x * 0xc))
62 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_rreg()
73 WREG32(EVERGREEN_CG_IND_ADDR, ((reg) & 0xffff)); in eg_cg_wreg()
84 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_rreg()
95 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); in eg_pif_phy0_wreg()
106 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_rreg()
117 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); in eg_pif_phy1_wreg()
136 0x98fc,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]