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/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-usb2-dr-0.dtsi2 * PQ3 USB DR device tree stub [ controller @ offset 0x22000 ]
37 reg = <0x22000 0x1000>;
39 #size-cells = <0>;
40 interrupts = <28 0x2 0 0>;
H A Dmpc8536si-post.dtsi39 interrupts = <19 2 0 0>;
42 /* controller at 0x8000 */
46 interrupts = <24 0x2 0 0>;
47 bus-range = <0 0xff>;
53 /* controller at 0x9000 */
59 bus-range = <0 255>;
61 interrupts = <25 2 0 0>;
63 pcie@0 {
64 reg = <0 0 0 0 0>;
69 interrupts = <25 2 0 0>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dq6sstop-qcs404.c23 .halt_reg = 0x1b004,
26 .enable_reg = 0x1b004,
27 .enable_mask = BIT(0),
36 .halt_reg = 0x22000,
39 .enable_reg = 0x22000,
40 .enable_mask = BIT(0),
49 .halt_reg = 0x1c000,
52 .enable_reg = 0x1c000,
53 .enable_mask = BIT(0),
62 .halt_reg = 0x22004,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-370-xp-pmsu.txt19 reg = <0x22000 0x1000>;
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Dam57-pruss.dtsi11 reg = <0x4b226000 0x4>,
12 <0x4b226004 0x4>;
23 clocks = <&l4per2_clkctrl DRA7_L4PER2_PRUSS1_CLKCTRL 0>;
27 ranges = <0x00000000 0x4b200000 0x80000>;
29 pruss1: pruss@0 {
31 reg = <0x0 0x80000>;
36 pruss1_mem: memories@0 {
37 reg = <0x0 0x2000>,
38 <0x2000 0x2000>,
39 <0x10000 0x8000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,pru-rproc.yaml19 The K3 SoCs containing ICSSG v1.0 (eg: AM65x SR1.0) also have two Auxiliary
21 containing the revised ICSSG v1.1 (eg: J721E, AM65x SR2.0) have an extra two
46 - ti,am654-tx-pru # for Tx_PRUs in K3 AM65x SR2.0 SoCs
79 pattern: "^rtu@[0-9a-f]+$"
91 pattern: "^txpru@[0-9a-f]+"
95 pattern: "^pru@[0-9a-f]+$"
108 pruss_tm: target-module@300000 { /* 0x4a300000, ap 9 04.0 */
112 ranges = <0x0 0x300000 0x80000>;
114 pruss: pruss@0 {
116 reg = <0x0 0x80000>;
[all …]
H A Dqcom,sdm845-adsp-pil.yaml125 reg = <0x17300000 0x40c>;
128 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
153 qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
157 qcom,smem-states = <&adsp_smp2p_out 0>;
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-davinci.txt32 reg = <0x22000 0x1000>;
37 #size-cells = <0>;
41 reg = <0x48>;
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmmio.c15 [MT_TOP_CFG_BASE] = 0x01000,
16 [MT_HW_BASE] = 0x01000,
17 [MT_PCIE_REMAP_2] = 0x02504,
18 [MT_ARB_BASE] = 0x20c00,
19 [MT_HIF_BASE] = 0x04000,
20 [MT_CSR_BASE] = 0x07000,
21 [MT_PLE_BASE] = 0x08000,
22 [MT_PSE_BASE] = 0x0c000,
23 [MT_CFG_BASE] = 0x20200,
24 [MT_AGG_BASE] = 0x20a00,
[all …]
/openbmc/u-boot/arch/arc/dts/
H A Daxs10x_mb.dtsi15 ranges = <0x00000000 0xe0000000 0x10000000>;
25 #clock-cells = <0>;
31 #clock-cells = <0>;
38 reg = < 0x18000 0x2000 >;
46 ehci@0x40000 {
48 reg = < 0x40000 0x100 >;
51 ohci@0x60000 {
53 reg = < 0x60000 0x100 >;
58 reg = <0x22000 0x100>;
64 spi0: spi@0 {
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
H A Dbcm-ns.dtsi19 ranges = <0x00000000 0x18000000 0x00001000>;
25 reg = <0x0300 0x100>;
33 reg = <0x0400 0x100>;
37 pinctrl-0 = <&pinmux_uart1>;
44 ranges = <0x00000000 0x19000000 0x00023000>;
50 reg = <0x20000 0x100>;
55 reg = <0x20200 0x100>;
62 reg = <0x20600 0x20>;
71 #address-cells = <0>;
73 reg = <0x21000 0x1000>,
[all …]
/openbmc/linux/arch/arc/boot/dts/
H A Dvdk_axs10x_mb.dtsi13 ranges = <0x00000000 0xe0000000 0x10000000>;
20 #clock-cells = <0>;
26 #clock-cells = <0>;
30 #clock-cells = <0>;
39 reg = < 0x18000 0x2000 >;
43 snps,phy-addr = < 0 >; // VDK model phy address is 0
51 reg = < 0x40000 0x100 >;
57 reg = <0x20000 0x100>;
67 reg = <0x21000 0x100>;
77 reg = <0x22000 0x100>;
[all …]
H A Daxs10x_mb.dtsi17 ranges = <0x00000000 0x0 0xe0000000 0x10000000>;
23 reg = <0x11220 0x4>;
28 reg = <0x100a0 0x10>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
62 #clock-cells = <0>;
68 reg = <0x10080 0x10>, <0x110 0x10>;
69 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_4_0_offset.h27 // base address: 0x22000
28 …VCE_STATUS 0x0a01
29 …ne mmVCE_STATUS_BASE_IDX 0
30 …VCE_VCPU_CNTL 0x0a05
31 …ne mmVCE_VCPU_CNTL_BASE_IDX 0
32 …VCE_VCPU_CACHE_OFFSET0 0x0a09
33 …ne mmVCE_VCPU_CACHE_OFFSET0_BASE_IDX 0
34 …VCE_VCPU_CACHE_SIZE0 0x0a0a
35 …ne mmVCE_VCPU_CACHE_SIZE0_BASE_IDX 0
36 …VCE_VCPU_CACHE_OFFSET1 0x0a0b
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml36 0x0, but also has access to a secondary Data RAM (primary to the other PRU
37 core) at its address 0x2000. A shared Data RAM, if present, can be accessed
60 pattern: "^(pruss|icssg)@[0-9a-f]+$"
65 - ti,am4376-pruss0 # for AM437x SoC family and PRUSS unit 0
161 const: 0
175 const: 0
209 const: 0
297 "^(pru|rtu|txpru)@[0-9a-f]+$":
350 pruss: pruss@0 {
352 reg = <0x0 0x80000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/ti-common/
H A Dkeystone_net.h18 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00090000)
19 #define EMAC_EMACSL_BASE_ADDR (GBETH_BASE + 0x900)
20 #define EMAC_MDIO_BASE_ADDR (GBETH_BASE + 0x300)
21 #define EMAC_SGMII_BASE_ADDR (GBETH_BASE + 0x100)
22 #define DEVICE_EMACSL_BASE(x) (EMAC_EMACSL_BASE_ADDR + (x) * 0x040)
25 #define CPGMACSL_REG_CTL 0x04
26 #define CPGMACSL_REG_STATUS 0x08
27 #define CPGMACSL_REG_RESET 0x0c
28 #define CPGMACSL_REG_MAXLEN 0x10
32 #define GBETH_BASE (CONFIG_KSNET_NETCP_BASE + 0x00200000)
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_83xx.h36 u8 res0[0x04];
38 u8 res1[0x14];
40 u8 res2[0x20];
42 u8 res3[0x10];
44 u8 res4[0x10];
46 u8 res5[0x50];
50 u8 res6[0x04];
54 u8 res7[0x04];
55 u32 sidcr0; /* System I/O Delay Configuration Register 0 */
60 u8 res8[0xC];
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dasp834x-redboot.dts25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x8000000>; // 128MB at 0
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
56 0 0 0xf0000000 0x02000000
[all …]
H A Dmpc8349emitx.dts27 #size-cells = <0>;
29 PowerPC,8349@0 {
31 reg = <0x0>;
36 timebase-frequency = <0>; // from bootloader
37 bus-frequency = <0>; // from bootloader
38 clock-frequency = <0>; // from bootloader
44 reg = <0x00000000 0x10000000>;
52 ranges = <0x0 0xe0000000 0x00100000>;
53 reg = <0xe0000000 0x00000200>;
54 bus-frequency = <0>; // from bootloader
[all …]
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-370-xp.dtsi29 #size-cells = <0>;
30 cpu@0 {
33 reg = <0>;
47 pcie-mem-aperture = <0xf8000000 0x7e00000>;
48 pcie-io-aperture = <0xffe00000 0x100000>;
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
56 clocks = <&coreclk 0>;
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Darmada-370-xp.dtsi68 #size-cells = <0>;
69 cpu@0 {
72 reg = <0>;
86 pcie-mem-aperture = <0xf8000000 0x7e00000>;
87 pcie-io-aperture = <0xffe00000 0x100000>;
91 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
92 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
95 clocks = <&coreclk 0>;
101 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
102 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
[all …]
/openbmc/qemu/tests/unit/
H A Dtest-resv-mem.c16 #define DEBUG 0
22 int i = 0; in print_ranges()
31 printf("%s rev[%i] = [0x%"PRIx64",0x%"PRIx64"]\n", in print_ranges()
95 in = insert_sorted_range(in, 0x10000, UINT64_MAX); in check_range_reverse_array()
96 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
97 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
101 in = insert_sorted_range(in, 0x10000, 0xFFFFFFFFFFFF); in check_range_reverse_array()
102 expected = insert_sorted_range(expected, 0x0, 0xFFFF); in check_range_reverse_array()
103 expected = insert_sorted_range(expected, 0x1000000000000, UINT64_MAX); in check_range_reverse_array()
104 run_range_inverse_array("test1", &in, &expected, 0x0, UINT64_MAX); in check_range_reverse_array()
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]

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