Searched +full:0 +full:x1c1000 (Results 1 – 4 of 4) sorted by relevance
130 reg = <0x01380000 0x27200>;137 reg = <0x01740000 0x1c1000>;
10 #define DSPXRAM_START 0x00000011 #define DSPXRAM_END 0x013FFC12 #define DSPAXRAM_START 0x02000013 #define DSPAXRAM_END 0x023FFC14 #define DSPYRAM_START 0x04000015 #define DSPYRAM_END 0x04FFFC16 #define DSPAYRAM_START 0x02000017 #define DSPAYRAM_END 0x063FFC18 #define DSPMICRO_START 0x08000019 #define DSPMICRO_END 0x0B3FFC[all …]
43 #define AR9170_UART_REG_BASE 0x1c000046 #define AR9170_UART_REG_RX_BUFFER (AR9170_UART_REG_BASE + 0x000)47 #define AR9170_UART_REG_TX_HOLDING (AR9170_UART_REG_BASE + 0x004)48 #define AR9170_UART_REG_FIFO_CONTROL (AR9170_UART_REG_BASE + 0x010)49 #define AR9170_UART_FIFO_CTRL_RESET_RX_FIFO 0x0250 #define AR9170_UART_FIFO_CTRL_RESET_TX_FIFO 0x0452 #define AR9170_UART_REG_LINE_CONTROL (AR9170_UART_REG_BASE + 0x014)53 #define AR9170_UART_REG_MODEM_CONTROL (AR9170_UART_REG_BASE + 0x018)54 #define AR9170_UART_MODEM_CTRL_DTR_BIT 0x0155 #define AR9170_UART_MODEM_CTRL_RTS_BIT 0x02[all …]
21 memset(buf, 0, size); in sja1105_spi_message_pack()38 u8 hdr_buf[SJA1105_SIZE_SPI_MSG_HEADER] = {0}; in sja1105_xfer()40 struct spi_transfer xfers[2] = {0}; in sja1105_xfer()45 int rc, i = 0; in sja1105_xfer()53 hdr_xfer = &xfers[0]; in sja1105_xfer()56 for (i = 0; i < num_chunks; i++) { in sja1105_xfer()67 msg.read_count = 0; in sja1105_xfer()106 if (rc < 0) { in sja1105_xfer()112 return 0; in sja1105_xfer()139 sja1105_pack(packed_buf, value, 63, 0, 8); in sja1105_xfer_u64()[all …]