/openbmc/u-boot/drivers/usb/gadget/ |
H A D | ci_udc.h | 13 u32 usbcmd; /* 0x130 */ 14 u32 usbsts; /* 0x134 */ 16 u32 devaddr; /* 0x144 */ 17 u32 epinitaddr; /* 0x148 */ 19 u32 portsc; /* 0x174 */ 20 u32 pad178[(0x1b4 - (0x174 + 4)) / 4]; 21 u32 hostpc1_devlc; /* 0x1b4 */ 22 u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4]; 23 u32 usbmode; /* 0x1f8 */ 24 u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4]; [all …]
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/openbmc/linux/arch/arm/mach-s3c/ |
H A D | regs-gpio-memport-s3c64xx.h | 14 #define S3C64XX_MEM0CONSTOP S3C64XX_GPIOREG(0x1B0) 15 #define S3C64XX_MEM1CONSTOP S3C64XX_GPIOREG(0x1B4) 17 #define S3C64XX_MEM0CONSLP0 S3C64XX_GPIOREG(0x1C0) 18 #define S3C64XX_MEM0CONSLP1 S3C64XX_GPIOREG(0x1C4) 19 #define S3C64XX_MEM1CONSLP S3C64XX_GPIOREG(0x1C8) 21 #define S3C64XX_MEM0DRVCON S3C64XX_GPIOREG(0x1D0) 22 #define S3C64XX_MEM1DRVCON S3C64XX_GPIOREG(0x1D4)
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/openbmc/linux/drivers/media/platform/chips-media/ |
H A D | coda_regs.h | 14 #define CODA_REG_BIT_CODE_RUN 0x000 15 #define CODA_REG_RUN_ENABLE (1 << 0) 16 #define CODA_REG_BIT_CODE_DOWN 0x004 17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16) 18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff) 19 #define CODA_REG_BIT_HOST_IN_REQ 0x008 20 #define CODA_REG_BIT_INT_CLEAR 0x00c 21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1 22 #define CODA_REG_BIT_INT_STATUS 0x010 23 #define CODA_REG_BIT_CODE_RESET 0x014 [all …]
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/ |
H A D | amlogic,meson6-efuse.yaml | 42 efuse: efuse@0 { 44 reg = <0x0 0x2000>; 51 reg = <0x1b4 0x6>; 55 reg = <0x1f4 0x4>;
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/openbmc/linux/drivers/phy/qualcomm/ |
H A D | phy-qcom-qmp-qserdes-pll.h | 10 #define QSERDES_PLL_BG_TIMER 0x00c 11 #define QSERDES_PLL_SSC_PER1 0x01c 12 #define QSERDES_PLL_SSC_PER2 0x020 13 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 14 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 15 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 16 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 17 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 18 #define QSERDES_PLL_CLK_ENABLE1 0x040 19 #define QSERDES_PLL_SYS_CLK_CTRL 0x044 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v6.h | 11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00 12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04 13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10 14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14 15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18 16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c 17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20 18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24 19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28 20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c [all …]
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H A D | phy-qcom-qmp-qserdes-txrx-v5_20.h | 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80 15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90 16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0 17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc 20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c [all …]
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H A D | phy-qcom-qmp-qserdes-com-v5.h | 10 #define QSERDES_V5_COM_ATB_SEL1 0x000 11 #define QSERDES_V5_COM_ATB_SEL2 0x004 12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008 13 #define QSERDES_V5_COM_BG_TIMER 0x00c 14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_V5_COM_SSC_PER1 0x01c 18 #define QSERDES_V5_COM_SSC_PER2 0x020 19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com-v4.h | 10 #define QSERDES_V4_COM_ATB_SEL1 0x000 11 #define QSERDES_V4_COM_ATB_SEL2 0x004 12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008 13 #define QSERDES_V4_COM_BG_TIMER 0x00c 14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_V4_COM_SSC_PER1 0x01c 18 #define QSERDES_V4_COM_SSC_PER2 0x020 19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 [all …]
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H A D | phy-qcom-qmp-pcs-v3.h | 10 #define QPHY_V3_PCS_SW_RESET 0x000 11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 12 #define QPHY_V3_PCS_START_CONTROL 0x008 13 #define QPHY_V3_PCS_TXMGN_V0 0x00c 14 #define QPHY_V3_PCS_TXMGN_V1 0x010 15 #define QPHY_V3_PCS_TXMGN_V2 0x014 16 #define QPHY_V3_PCS_TXMGN_V3 0x018 17 #define QPHY_V3_PCS_TXMGN_V4 0x01c 18 #define QPHY_V3_PCS_TXMGN_LS 0x020 19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 [all …]
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H A D | phy-qcom-qmp-qserdes-com.h | 10 #define QSERDES_COM_ATB_SEL1 0x000 11 #define QSERDES_COM_ATB_SEL2 0x004 12 #define QSERDES_COM_FREQ_UPDATE 0x008 13 #define QSERDES_COM_BG_TIMER 0x00c 14 #define QSERDES_COM_SSC_EN_CENTER 0x010 15 #define QSERDES_COM_SSC_ADJ_PER1 0x014 16 #define QSERDES_COM_SSC_ADJ_PER2 0x018 17 #define QSERDES_COM_SSC_PER1 0x01c 18 #define QSERDES_COM_SSC_PER2 0x020 19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 [all …]
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H A D | phy-qcom-qmp-pcs-v4.h | 10 #define QPHY_V4_PCS_SW_RESET 0x000 11 #define QPHY_V4_PCS_REVISION_ID0 0x004 12 #define QPHY_V4_PCS_REVISION_ID1 0x008 13 #define QPHY_V4_PCS_REVISION_ID2 0x00c 14 #define QPHY_V4_PCS_REVISION_ID3 0x010 15 #define QPHY_V4_PCS_PCS_STATUS1 0x014 16 #define QPHY_V4_PCS_PCS_STATUS2 0x018 17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 18 #define QPHY_V4_PCS_PCS_STATUS4 0x020 19 #define QPHY_V4_PCS_PCS_STATUS5 0x024 [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000 17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000 19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000 20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000 21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000 23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000 24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000 25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000 26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000 28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000 [all …]
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H A D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000 17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0 18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0 19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1 20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0 21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0 22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0 24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0 25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0 26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1 [all …]
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/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
H A D | cpucfg.h | 17 u32 rst; /* base + 0x0 */ 18 u32 ctrl; /* base + 0x4 */ 19 u32 status; /* base + 0x8 */ 20 u8 res[0x34]; /* base + 0xc */ 24 u8 res0[0x40]; /* 0x000 */ 25 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */ 26 u8 res1[0x44]; /* 0x140 */ 27 u32 gen_ctrl; /* 0x184 */ 28 u32 l2_status; /* 0x188 */ 29 u8 res2[0x4]; /* 0x18c */ [all …]
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/openbmc/linux/include/linux/mfd/ |
H A D | idt82p33_reg.h | 10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f)) 13 #define DPLL1_TOD_CNFG 0x134 14 #define DPLL2_TOD_CNFG 0x1B4 16 #define DPLL1_TOD_STS 0x10B 17 #define DPLL2_TOD_STS 0x18B 19 #define DPLL1_TOD_TRIGGER 0x115 20 #define DPLL2_TOD_TRIGGER 0x195 22 #define DPLL1_OPERATING_MODE_CNFG 0x120 23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0 25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C [all …]
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/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 [all …]
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H A D | imx8mn-pinfunc.h | 14 …ne MX8MN_IOMUXC_BOOT_MODE2_CCMSRCGPCMIX_BOOT_MODE2 0x020 0x25C 0x000 0x0 0x0 15 …ne MX8MN_IOMUXC_BOOT_MODE2_I2C1_SCL 0x020 0x25C 0x55C 0x1 0x3 16 …ne MX8MN_IOMUXC_BOOT_MODE3_CCMSRCGPCMIX_BOOT_MODE3 0x024 0x260 0x000 0x0 0x0 17 …ne MX8MN_IOMUXC_BOOT_MODE3_I2C1_SDA 0x024 0x260 0x56C 0x1 0x3 18 …ne MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0x0 19 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x000 0x1 0x0 20 …ne MX8MN_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0x0 21 …ne MX8MN_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0x0 22 …ne MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0x0 23 …ne MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0x0 [all …]
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H A D | imx8mm-pinfunc.h | 14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0… 15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0… 16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0… 17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0… 18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0… 19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0… 20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0… 21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0… 22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0… 23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0… [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-pic32.h | 12 #define ANSEL_REG 0x00 13 #define TRIS_REG 0x10 14 #define PORT_REG 0x20 15 #define LAT_REG 0x30 16 #define ODCU_REG 0x40 17 #define CNPU_REG 0x50 18 #define CNPD_REG 0x60 19 #define CNCON_REG 0x70 20 #define CNEN_REG 0x80 21 #define CNSTAT_REG 0x90 [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | g12a.h | 20 #define HHI_MIPI_CNTL0 0x000 21 #define HHI_MIPI_CNTL1 0x004 22 #define HHI_MIPI_CNTL2 0x008 23 #define HHI_MIPI_STS 0x00C 24 #define HHI_GP0_PLL_CNTL0 0x040 25 #define HHI_GP0_PLL_CNTL1 0x044 26 #define HHI_GP0_PLL_CNTL2 0x048 27 #define HHI_GP0_PLL_CNTL3 0x04C 28 #define HHI_GP0_PLL_CNTL4 0x050 29 #define HHI_GP0_PLL_CNTL5 0x054 [all …]
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/openbmc/linux/arch/arm/boot/dts/ti/omap/ |
H A D | dra72x-mmc-iodelay.dtsi | 37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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H A D | motorola-mapphone-common.dtsi | 24 reg = <0x80000000 0x3fd00000>; /* 1021 MB */ 30 pinctrl-0 = <&poweroff_gpio>; 37 pinctrl-0 = <&hdmi_hpd_gpio>; 69 pinctrl-0 = <&usb_mdm6600_pins>; 85 #phy-cells = <0>; 91 #phy-cells = <0>; 100 gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>; /* gpio96 */ 138 pinctrl-0 = <&vibrator_direction_pin>; 143 ti,clock-source = <0x01>; 148 pinctrl-0 = <&vibrator_enable_pin>; [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | dra72x-mmc-iodelay.dtsi | 45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ [all …]
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/openbmc/linux/drivers/thermal/ti-soc-thermal/ |
H A D | omap5xxx-bandgap.h | 29 #define OMAP5430_FUSE_OPP_BGAP_GPU 0x0 30 #define OMAP5430_TEMP_SENSOR_GPU_OFFSET 0x150 31 #define OMAP5430_BGAP_THRESHOLD_GPU_OFFSET 0x1A8 32 #define OMAP5430_BGAP_TSHUT_GPU_OFFSET 0x1B4 33 #define OMAP5430_BGAP_DTEMP_GPU_1_OFFSET 0x1F8 34 #define OMAP5430_BGAP_DTEMP_GPU_2_OFFSET 0x1FC 37 #define OMAP5430_FUSE_OPP_BGAP_MPU 0x4 38 #define OMAP5430_TEMP_SENSOR_MPU_OFFSET 0x14C 39 #define OMAP5430_BGAP_THRESHOLD_MPU_OFFSET 0x1A4 40 #define OMAP5430_BGAP_TSHUT_MPU_OFFSET 0x1B0 [all …]
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