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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_3_0_msm8998.h12 .max_mixer_blendstages = 0x7,
26 .base = 0x0, .len = 0x458,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dintel,pinctrl-keembay.yaml45 '^gpio@[0-9a-f]*$':
78 0 - Fast(~100MHz)
80 enum: [0, 1]
99 gpio@0 {
101 reg = <0x600b0000 0x88>,
102 <0x600b0190 0x1ac>;
104 ngpios = <0x50>;
105 #gpio-cells = <0x2>;
121 reg = <0x600c0000 0x88>,
122 <0x600c0190 0x1ac>;
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun20i-d1-r.c26 r_ahb_apb0_parents, 0x000,
27 0, 5, /* M */
30 0);
34 r_ahb_apb0_parents, 0x00c,
35 0, 5, /* M */
38 0);
42 0x11c, BIT(0), 0);
44 0x12c, BIT(0), 0);
46 0x1ac, BIT(0), 0);
53 r_ir_rx_parents, 0x1c0,
[all …]
/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-pcs-pcie-v6_20.h10 #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
11 #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
12 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
13 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
14 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
15 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
16 #define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
17 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
18 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
19 #define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
[all …]
H A Dphy-qcom-qmp-pcs-v2.h10 #define QPHY_V2_PCS_SW_RESET 0x000
11 #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_START_CONTROL 0x008
13 #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x024
14 #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x028
15 #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x054
16 #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x058
17 #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x060
18 #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x064
19 #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x06c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v6.h11 #define QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1 0x00
12 #define QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1 0x04
13 #define QSERDES_V6_COM_CP_CTRL_MODE1 0x10
14 #define QSERDES_V6_COM_PLL_RCTRL_MODE1 0x14
15 #define QSERDES_V6_COM_PLL_CCTRL_MODE1 0x18
16 #define QSERDES_V6_COM_CORECLK_DIV_MODE1 0x1c
17 #define QSERDES_V6_COM_LOCK_CMP1_MODE1 0x20
18 #define QSERDES_V6_COM_LOCK_CMP2_MODE1 0x24
19 #define QSERDES_V6_COM_DEC_START_MODE1 0x28
20 #define QSERDES_V6_COM_DEC_START_MSB_MODE1 0x2c
[all …]
H A Dphy-qcom-qmp-qserdes-txrx-v5_20.h10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30
11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34
12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78
13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c
14 #define QSERDES_V5_20_TX_LANE_MODE_3 0x80
15 #define QSERDES_V5_20_TX_RCV_DETECT_LVL_2 0x90
16 #define QSERDES_V5_20_TX_VMODE_CTRL1 0xb0
17 #define QSERDES_V5_20_TX_PI_QEC_CTRL 0xcc
20 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008
21 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c
[all …]
H A Dphy-qcom-qmp-qserdes-com-v5.h10 #define QSERDES_V5_COM_ATB_SEL1 0x000
11 #define QSERDES_V5_COM_ATB_SEL2 0x004
12 #define QSERDES_V5_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V5_COM_BG_TIMER 0x00c
14 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V5_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V5_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V5_COM_SSC_PER1 0x01c
18 #define QSERDES_V5_COM_SSC_PER2 0x020
19 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com-v4.h10 #define QSERDES_V4_COM_ATB_SEL1 0x000
11 #define QSERDES_V4_COM_ATB_SEL2 0x004
12 #define QSERDES_V4_COM_FREQ_UPDATE 0x008
13 #define QSERDES_V4_COM_BG_TIMER 0x00c
14 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_V4_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_V4_COM_SSC_PER1 0x01c
18 #define QSERDES_V4_COM_SSC_PER2 0x020
19 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v3.h10 #define QPHY_V3_PCS_SW_RESET 0x000
11 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V3_PCS_START_CONTROL 0x008
13 #define QPHY_V3_PCS_TXMGN_V0 0x00c
14 #define QPHY_V3_PCS_TXMGN_V1 0x010
15 #define QPHY_V3_PCS_TXMGN_V2 0x014
16 #define QPHY_V3_PCS_TXMGN_V3 0x018
17 #define QPHY_V3_PCS_TXMGN_V4 0x01c
18 #define QPHY_V3_PCS_TXMGN_LS 0x020
19 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024
[all …]
H A Dphy-qcom-qmp-qserdes-com.h10 #define QSERDES_COM_ATB_SEL1 0x000
11 #define QSERDES_COM_ATB_SEL2 0x004
12 #define QSERDES_COM_FREQ_UPDATE 0x008
13 #define QSERDES_COM_BG_TIMER 0x00c
14 #define QSERDES_COM_SSC_EN_CENTER 0x010
15 #define QSERDES_COM_SSC_ADJ_PER1 0x014
16 #define QSERDES_COM_SSC_ADJ_PER2 0x018
17 #define QSERDES_COM_SSC_PER1 0x01c
18 #define QSERDES_COM_SSC_PER2 0x020
19 #define QSERDES_COM_SSC_STEP_SIZE1 0x024
[all …]
H A Dphy-qcom-qmp-pcs-v4.h10 #define QPHY_V4_PCS_SW_RESET 0x000
11 #define QPHY_V4_PCS_REVISION_ID0 0x004
12 #define QPHY_V4_PCS_REVISION_ID1 0x008
13 #define QPHY_V4_PCS_REVISION_ID2 0x00c
14 #define QPHY_V4_PCS_REVISION_ID3 0x010
15 #define QPHY_V4_PCS_PCS_STATUS1 0x014
16 #define QPHY_V4_PCS_PCS_STATUS2 0x018
17 #define QPHY_V4_PCS_PCS_STATUS3 0x01c
18 #define QPHY_V4_PCS_PCS_STATUS4 0x020
19 #define QPHY_V4_PCS_PCS_STATUS5 0x024
[all …]
/openbmc/linux/drivers/media/platform/chips-media/
H A Dcoda_regs.h14 #define CODA_REG_BIT_CODE_RUN 0x000
15 #define CODA_REG_RUN_ENABLE (1 << 0)
16 #define CODA_REG_BIT_CODE_DOWN 0x004
17 #define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
18 #define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
19 #define CODA_REG_BIT_HOST_IN_REQ 0x008
20 #define CODA_REG_BIT_INT_CLEAR 0x00c
21 #define CODA_REG_BIT_INT_CLEAR_SET 0x1
22 #define CODA_REG_BIT_INT_STATUS 0x010
23 #define CODA_REG_BIT_CODE_RESET 0x014
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpucfg.h17 u32 rst; /* base + 0x0 */
18 u32 ctrl; /* base + 0x4 */
19 u32 status; /* base + 0x8 */
20 u8 res[0x34]; /* base + 0xc */
24 u8 res0[0x40]; /* 0x000 */
25 struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */
26 u8 res1[0x44]; /* 0x140 */
27 u32 gen_ctrl; /* 0x184 */
28 u32 l2_status; /* 0x188 */
29 u8 res2[0x4]; /* 0x18c */
[all …]
/openbmc/linux/include/linux/mfd/
H A Didt82p33_reg.h10 #define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
13 #define DPLL1_TOD_CNFG 0x134
14 #define DPLL2_TOD_CNFG 0x1B4
16 #define DPLL1_TOD_STS 0x10B
17 #define DPLL2_TOD_STS 0x18B
19 #define DPLL1_TOD_TRIGGER 0x115
20 #define DPLL2_TOD_TRIGGER 0x195
22 #define DPLL1_OPERATING_MODE_CNFG 0x120
23 #define DPLL2_OPERATING_MODE_CNFG 0x1A0
25 #define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,ls-extirq.yaml39 const: 0
77 - const: 0x7
78 - const: 0
96 - const: 0xf
97 - const: 0
107 #address-cells = <0>;
109 reg = <0x1ac 4>;
111 <0 0 &gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
112 <1 0 &gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
113 <2 0 &gic GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/drivers/usb/fotg210/
H A Dfotg210-udc.h14 /* Global Mask of HC/OTG/DEV interrupt Register(0xC4) */
15 #define FOTG210_GMIR 0xC4
16 #define GMIR_INT_POLARITY 0x8 /*Active High*/
17 #define GMIR_MHC_INT 0x4
18 #define GMIR_MOTG_INT 0x2
19 #define GMIR_MDEV_INT 0x1
21 /* Device Main Control Register(0x100) */
22 #define FOTG210_DMCR 0x100
29 #define DMCR_CAP_RMWAKUP (1 << 0)
31 /* Device Address Register(0x104) */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-pinfunc.h14 #define MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x028 0x290 0x000 0x0 0…
15 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT 0x028 0x290 0x4C0 0x1 0…
16 #define MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x028 0x290 0x000 0x5 0…
17 #define MX8MM_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1 0x028 0x290 0x000 0x6 0…
18 #define MX8MM_IOMUXC_GPIO1_IO00_SJC_FAIL 0x028 0x290 0x000 0x7 0…
19 #define MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x02C 0x294 0x000 0x0 0…
20 #define MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x02C 0x294 0x000 0x1 0…
21 #define MX8MM_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M 0x02C 0x294 0x4BC 0x5 0…
22 #define MX8MM_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2 0x02C 0x294 0x000 0x6 0…
23 #define MX8MM_IOMUXC_GPIO1_IO01_SJC_ACTIVE 0x02C 0x294 0x000 0x7 0…
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx50-pinfunc.h13 #define MX50_PAD_KEY_COL0__KPP_COL_0 0x020 0x2cc 0x000 0x0 0x0
14 #define MX50_PAD_KEY_COL0__GPIO4_0 0x020 0x2cc 0x000 0x1 0x0
15 #define MX50_PAD_KEY_COL0__EIM_NANDF_CLE 0x020 0x2cc 0x000 0x2 0x0
16 #define MX50_PAD_KEY_COL0__CTI_TRIGIN7 0x020 0x2cc 0x000 0x6 0x0
17 #define MX50_PAD_KEY_COL0__USBPHY1_TXREADY 0x020 0x2cc 0x000 0x7 0x0
18 #define MX50_PAD_KEY_ROW0__KPP_ROW_0 0x024 0x2d0 0x000 0x0 0x0
19 #define MX50_PAD_KEY_ROW0__GPIO4_1 0x024 0x2d0 0x000 0x1 0x0
20 #define MX50_PAD_KEY_ROW0__EIM_NANDF_ALE 0x024 0x2d0 0x000 0x2 0x0
21 #define MX50_PAD_KEY_ROW0__CTI_TRIGIN_ACK7 0x024 0x2d0 0x000 0x6 0x0
22 #define MX50_PAD_KEY_ROW0__USBPHY1_RXVALID 0x024 0x2d0 0x000 0x7 0x0
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dgp_padctrl.h14 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
15 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
16 u32 reserved0[22]; /* 0x08 - 0x5C: */
17 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
18 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
19 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
20 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
21 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
22 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
23 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra114/
H A Dgp_padctrl.h13 u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
14 u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
15 u32 reserved0[22]; /* 0x08 - 0x5C: */
16 u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
17 u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
18 u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
19 u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
20 u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
21 u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
22 u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-am62p5-sk.dts29 reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
30 <0x00000008 0x80000000 0x00000001 0x80000000>;
40 reg = <0x00 0x9e780000 0x00 0x80000>;
45 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
51 reg = <0x00 0x9c900000 0x00 0x01e00000>;
61 AM62PX_IOPAD(0x1c8, PIN_INPUT, 0) /* (A22) UART0_RXD */
62 AM62PX_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (B22) UART0_TXD */
63 AM62PX_IOPAD(0x1d0, PIN_INPUT, 0) /* (A23) UART0_CTSn */
64 AM62PX_IOPAD(0x1d4, PIN_OUTPUT, 0) /* (C22) UART0_RTSn */
71 AM62PX_IOPAD(0x194, PIN_INPUT, 2) /* (D25) MCASP0_AXR3 */
[all …]
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72x-mmc-iodelay.dtsi37 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
38 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
39 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
40 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
41 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
42 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
48 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
49 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
50 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
51 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Ddra72x-mmc-iodelay.dtsi45 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
46 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
47 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
48 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
49 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
50 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
56 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
57 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
58 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
59 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
[all …]

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