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/openbmc/u-boot/arch/mips/dts/
H A Dar934x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
53 reg = <0x1b000100 0x100>;
60 reg = <0x18020000 0x20>;
66 gmac0: eth@0x19000000 {
68 reg = <0x19000000 0x200>;
76 #size-cells = <0>;
77 phy0: ethernet-phy@0 {
[all …]
H A Dar933x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
43 reg = <0x18040000 0x100>;
62 reg = <0x1b000100 0x100>;
69 reg = <0x18020000 0x20>;
74 gmac0: eth@0x19000000 {
76 reg = <0x19000000 0x200>;
84 #size-cells = <0>;
[all …]
H A Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x13450000 0x1000>;
61 reg = <0x13460000 0x1000>;
71 reg = <0x10030000 0x100>;
85 reg = <0x10031000 0x100>;
99 reg = <0x10032000 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/openbmc/u-boot/configs/
H A Dvexpress_ca15_tc2_defconfig3 CONFIG_SYS_TEXT_BASE=0x80800000
30 CONFIG_SMC911X_BASE=0x1a000000
33 CONFIG_CONS_INDEX=0
H A Dvexpress_ca5x2_defconfig3 CONFIG_SYS_TEXT_BASE=0x80800000
29 CONFIG_SMC911X_BASE=0x1a000000
32 CONFIG_CONS_INDEX=0
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,camsys.txt22 reg = <0 0x1a000000 0 0x1000>;
H A Dmediatek,ssusbsys.txt22 reg = <0 0x1a000000 0 0x1000>;
H A Dmediatek,hifsys.txt23 reg = <0 0x1a000000 0 0x1000>;
H A Dmediatek,mt8192-clock.yaml56 reg = <0x10720000 0x1000>;
63 reg = <0x11007000 0x1000>;
70 reg = <0x11cb1000 0x1000>;
77 reg = <0x11d03000 0x1000>;
84 reg = <0x11d23000 0x1000>;
91 reg = <0x11e01000 0x1000>;
98 reg = <0x11f02000 0x1000>;
105 reg = <0x11f10000 0x1000>;
112 reg = <0x13fbf000 0x1000>;
119 reg = <0x15020000 0x1000>;
[all …]
H A Dmediatek,mt8195-clock.yaml68 reg = <0x10720000 0x1000>;
75 reg = <0x11d03000 0x1000>;
82 reg = <0x11e05000 0x1000>;
89 reg = <0x13fbf000 0x1000>;
96 reg = <0x14e00000 0x1000>;
103 reg = <0x14e02000 0x1000>;
110 reg = <0x14e03000 0x1000>;
117 reg = <0x15000000 0x1000>;
124 reg = <0x15110000 0x1000>;
131 reg = <0x15130000 0x1000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Drs780e-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000
9 0 0x40000000 0 0x40000000 0 0x40000000
10 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
18 reg = <0 0x1a000000 0 0x02000000>;
20 ranges = <0x01000000 0 0x00004000 0 0x18004000 0 0x0000c000>,
21 <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
28 ranges = <1 0 0 0x18000000 0x4000>;
32 reg = <1 0x70 0x8>;
39 reg = <1 0x800 0x100>;
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dloongson.yaml56 reg = <0x0 0x1a000000 0x0 0x2000000>;
59 ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
60 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
60 reg = <0x13410000 0x10000>;
63 ranges = <1 0 0x1b000000 0x1000000>,
64 <2 0 0x1a000000 0x1000000>,
65 <3 0 0x19000000 0x1000000>,
66 <4 0 0x18000000 0x1000000>,
67 <5 0 0x17000000 0x1000000>,
68 <6 0 0x16000000 0x1000000>;
77 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dk3-am654-base-board-ddr4-1600MHz.dtsi13 #define DDRCTL_MSTR 0x41040010
14 #define DDRCTL_RFSHCTL0 0x00210070
15 #define DDRCTL_ECCCFG0 0x00000000
16 #define DDRCTL_RFSHTMG 0x0061008C
17 #define DDRCTL_CRCPARCTL0 0x00008000
18 #define DDRCTL_CRCPARCTL1 0x1A000000
19 #define DDRCTL_CRCPARCTL2 0x0048051E
20 #define DDRCTL_INIT0 0x400100C4
21 #define DDRCTL_INIT1 0x004F0000
22 #define DDRCTL_INIT3 0x02140501
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dar9331.txt26 reg = <0x19000000 0x200>;
40 reg = <0x1a000000 0x200>;
56 #size-cells = <0>;
60 #size-cells = <0>;
63 reg = <0x10>;
75 #size-cells = <0>;
77 switch_port0: port@0 {
78 reg = <0x0>;
90 reg = <0x1>;
96 reg = <0x2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar71xx.yaml78 reg = <0x19000000 0x200>;
90 reg = <0x1a000000 0x200>;
106 #size-cells = <0>;
110 reg = <0x10>;
122 #size-cells = <0>;
124 switch_port0: port@0 {
125 reg = <0x0>;
137 reg = <0x1>;
143 reg = <0x2>;
149 reg = <0x3>;
[all …]
/openbmc/linux/arch/mips/alchemy/devboards/
H A Ddb1000.c49 return 0; in db1000_board_setup()
56 if ((slot < 12) || (slot > 13) || pin == 0) in db1500_map_pci_irq()
59 return (pin == 1) ? AU1500_PCI_INTA : 0xff; in db1500_map_pci_irq()
74 [0] = {
76 .end = AU1500_PCI_PHYS_ADDR + 0xfff,
88 .id = 0,
99 [0] = {
101 .end = AU1100_LCD_PHYS_ADDR + 0x800 - 1,
113 .id = 0,
123 [0] = {
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8536ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
50 reg = <0x03000000 0x00e00000>;
56 reg = <0x03e00000 0x00200000>;
62 reg = <0x04000000 0x00400000>;
67 reg = <0x04400000 0x03b00000>;
72 reg = <0x07f00000 0x00080000>;
77 reg = <0x07f80000 0x00080000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]
/openbmc/linux/arch/mips/loongson64/
H A Denv.c26 #define HOST_BRIDGE_CONFIG_ADDR ((void __iomem *)TO_UNCAC(0x1a000000))
37 u64 loongson_chipcfg[MAX_PACKAGES] = {0xffffffffbfc00180};
93 smp_group[0] = 0x900000001fe11000; in prom_lefi_init_env()
101 smp_group[0] = 0x900000003ff01000; in prom_lefi_init_env()
102 smp_group[1] = 0x900010003ff01000; in prom_lefi_init_env()
103 smp_group[2] = 0x900020003ff01000; in prom_lefi_init_env()
104 smp_group[3] = 0x900030003ff01000; in prom_lefi_init_env()
105 loongson_chipcfg[0] = 0x900000001fe00180; in prom_lefi_init_env()
106 loongson_chipcfg[1] = 0x900010001fe00180; in prom_lefi_init_env()
107 loongson_chipcfg[2] = 0x900020001fe00180; in prom_lefi_init_env()
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6779.dtsi26 #size-cells = <0>;
28 cpu0: cpu@0 {
32 reg = <0x000>;
39 reg = <0x100>;
46 reg = <0x200>;
53 reg = <0x300>;
60 reg = <0x400>;
67 reg = <0x500>;
74 reg = <0x600>;
81 reg = <0x700>;
[all …]

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