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/openbmc/linux/arch/arm64/boot/dts/realtek/
H A Drtd129x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000001f000;
9 /memreserve/ 0x000000000001f000 0x00000000000e1000;
10 /memreserve/ 0x0000000001b00000 0x00000000004be000;
26 reg = <0x1f000 0x1000>;
30 reg = <0x1ffe000 0x4000>;
34 reg = <0x10100000 0xf00000>;
47 #clock-cells = <0>;
55 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
57 <0x80000000 0x80000000 0x80000000>;
61 reg = <0x98000000 0x200000>;
[all …]
H A Drtd139x.dtsi8 /memreserve/ 0x0000000000000000 0x000000000002f000;
9 /memreserve/ 0x000000000002f000 0x00000000000d1000;
25 reg = <0x2f000 0x1000>;
29 reg = <0x1ffe000 0x4000>;
33 reg = <0x10100000 0xf00000>;
46 #clock-cells = <0>;
54 ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
55 <0x98000000 0x98000000 0x68000000>;
59 reg = <0x98000000 0x200000>;
62 ranges = <0x0 0x98000000 0x200000>;
[all …]
H A Drtd16xx.dtsi23 reg = <0x2f000 0x1000>;
27 reg = <0x1ffe000 0x4000>;
31 reg = <0x10100000 0xf00000>;
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
51 reg = <0x100>;
59 reg = <0x200>;
67 reg = <0x300>;
75 reg = <0x400>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dfsl-sata.txt13 1 for controller @ 0x18000
14 2 for controller @ 0x19000
15 3 for controller @ 0x1a000
16 4 for controller @ 0x1b000
24 reg = <0x18000 0x1000>;
H A Data-generic.yaml42 default: 0
54 reg = <0x1a000 0x100>,
55 <0x1a100 0xf00>;
/openbmc/linux/arch/arm/boot/dts/realtek/
H A Drtd1195.dtsi6 /memreserve/ 0x00000000 0x0000a800; /* boot code */
7 /memreserve/ 0x0000a800 0x000f5800;
8 /memreserve/ 0x17fff000 0x00001000;
21 #size-cells = <0>;
23 cpu0: cpu@0 {
26 reg = <0x0>;
33 reg = <0x1>;
44 reg = <0x0000b000 0x1000>;
48 reg = <0x01b00000 0x400000>;
52 reg = <0x01ffe000 0x4000>;
[all …]
/openbmc/u-boot/include/configs/
H A Dls1021aqds.h54 #define CONFIG_SPL_TEXT_BASE 0x10000000
55 #define CONFIG_SPL_MAX_SIZE 0x1a000
56 #define CONFIG_SPL_STACK 0x1001d000
57 #define CONFIG_SPL_PAD_TO 0x1c000
61 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
62 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
63 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
64 #define CONFIG_SYS_MONITOR_LEN 0xc0000
70 #define CONFIG_SPL_TEXT_BASE 0x10000000
71 #define CONFIG_SPL_MAX_SIZE 0x1a000
[all …]
H A Dtheadorable.h35 #define CONFIG_SYS_I2C_SLAVE 0x0
56 "fdt_high=0x10000000\0" \
57 "initrd_high=0x10000000\0"
64 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
77 #define BOOTCOUNT_ADDR 0x1000
89 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
90 * 0x4000.4030 bin_hdr start address
91 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
92 * 0x4007.fffc BootROM stack top
94 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
[all …]
H A Dls1021aiot.h28 #define DDR_SDRAM_CFG 0x470c0008
29 #define DDR_CS0_BNDS 0x008000bf
30 #define DDR_CS0_CONFIG 0x80014302
31 #define DDR_TIMING_CFG_0 0x50550004
32 #define DDR_TIMING_CFG_1 0xbcb38c56
33 #define DDR_TIMING_CFG_2 0x0040d120
34 #define DDR_TIMING_CFG_3 0x010e1000
35 #define DDR_TIMING_CFG_4 0x00000001
36 #define DDR_TIMING_CFG_5 0x03401400
37 #define DDR_SDRAM_CFG_2 0x00401010
[all …]
H A Dls1043a_common.h38 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
44 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
45 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
47 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
67 #define CONFIG_SPL_TEXT_BASE 0x10000000
68 #define CONFIG_SPL_MAX_SIZE 0x17000
69 #define CONFIG_SPL_STACK 0x1001e000
70 #define CONFIG_SPL_PAD_TO 0x1d000
74 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
75 #define CONFIG_SPL_BSS_START_ADDR 0x8f000000
[all …]
H A Dls1021atwr.h29 #define DDR_SDRAM_CFG 0x470c0008
30 #define DDR_CS0_BNDS 0x008000bf
31 #define DDR_CS0_CONFIG 0x80014302
32 #define DDR_TIMING_CFG_0 0x50550004
33 #define DDR_TIMING_CFG_1 0xbcb38c56
34 #define DDR_TIMING_CFG_2 0x0040d120
35 #define DDR_TIMING_CFG_3 0x010e1000
36 #define DDR_TIMING_CFG_4 0x00000001
37 #define DDR_TIMING_CFG_5 0x03401400
38 #define DDR_SDRAM_CFG_2 0x00401010
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dnxp,sja1000.yaml50 enum: [ 0, 1, 2, 3 ]
54 <0> : bi-phase output mode
61 default: 0x02
65 <0x01> : TX0 invert
66 <0x02> : TX0 pull-down (default)
67 <0x04> : TX0 pull-up
68 <0x06> : TX0 push-pull
69 <0x08> : TX1 invert
70 <0x10> : TX1 pull-down
71 <0x20> : TX1 pull-up
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_cfg.c22 0,
35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
36 .flush_hw_mask = 0x0003ffff,
40 .base = { 0x01100, 0x01500, 0x01900 },
45 0,
49 .base = { 0x01d00, 0x02100, 0x02500 },
53 0,
57 .base = { 0x02900, 0x02d00 },
60 0,
64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
[all …]
/openbmc/linux/sound/pci/au88x0/
H A Dau88x0_a3d.h18 #define HRTF_SZ 0x38
19 #define DLINE_SZ 0x28
48 #define A3D_A_HrtfCurrent 0x18000 /* 56 ULONG */
49 #define A3D_A_GainCurrent 0x180E0
50 #define A3D_A_GainTarget 0x180E4
51 #define A3D_A_A12Current 0x180E8 /* Atmospheric current. */
52 #define A3D_A_A21Target 0x180EC /* Atmospheric target */
53 #define A3D_A_B01Current 0x180F0 /* Atmospheric current */
54 #define A3D_A_B10Target 0x180F4 /* Atmospheric target */
55 #define A3D_A_B2Current 0x180F8 /* Atmospheric current */
[all …]
/openbmc/linux/drivers/net/wireless/rsi/
H A Drsi_hal.h45 #define FLASH_SIZE_ADDR 0x04000016
46 #define PING_BUFFER_ADDRESS 0x19000
47 #define PONG_BUFFER_ADDRESS 0x1a000
48 #define SWBL_REGIN 0x41050034
49 #define SWBL_REGOUT 0x4105003c
50 #define PING_WRITE 0x1
51 #define PONG_WRITE 0x2
56 #define REGIN_VALID 0xA
57 #define REGIN_INPUT 0xA0
58 #define REGOUT_VALID 0xAB
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx51-ts4800.dts22 reg = <0x90000000 0x10000000>;
38 pinctrl-0 = <&pinctrl_enable_lcd>;
48 pwms = <&pwm1 0 78770>;
49 brightness-levels = <0 150 200 255>;
58 pinctrl-0 = <&pinctrl_lcd>;
69 vback-porch = <0>;
70 vfront-porch = <0>;
85 pinctrl-0 = <&pinctrl_esdhc1>;
86 cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
93 pinctrl-0 = <&pinctrl_fec>;
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D04625 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
60 local pattern=0
61 local cur_sec=0
63 for ((i=0;i<=$((sectors - 1));i++)); do
71 backing_io 0 32 write | $QEMU_IO "$TEST_IMG" | _filter_qemu_io
84 aio_write -P 10 0x18000 0x2000
87 aio_write -P 11 0x12000 0x2000
88 aio_write -P 12 0x1c000 0x2000
98 aio_write -P 20 0x28000 0x2000
[all …]
/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dqcom,msm8916-mss-pil.yaml253 reg = <0x04080000 0x100>, <0x04020000 0x40>;
257 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
263 qcom,smem-states = <&hexagon_smp2p_out 0>;
265 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;
277 resets = <&scm 0>;
285 qcom,smd-edge = <0>;
/openbmc/qemu/hw/m68k/
H A Dnext-cube.c35 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0)
37 #define DPRINTF(fmt, ...) do { } while (0)
43 #define ENTRY 0x0100001e
44 #define RAM_SIZE 0x4000000
116 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
117 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00,
118 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13
123 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00,
124 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00,
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Dintel_uncore.c66 uncore->debug->unclaimed_mmio_check = 0; in mmio_debug_suspend()
115 if (id >= 0 && id < FW_DOMAIN_ID_COUNT) in intel_uncore_forcewake_domain_to_str()
137 fw_clear(d, 0xefff); in fw_domain_reset()
139 fw_clear(d, 0xffff); in fw_domain_reset()
167 return __wait_for_ack(d, ack, 0); in wait_ack_clear()
183 if (fw_ack(d) == ~0) in fw_domain_wait_ack_clear()
185 "%s: MMIO unreliable (forcewake register returns 0xFFFFFFFF)!\n", in fw_domain_wait_ack_clear()
196 ACK_CLEAR = 0,
205 const u32 value = type == ACK_SET ? ack_bit : 0; in fw_domain_wait_ack_with_fallback()
238 "%s had to use fallback to %s ack, 0x%x (passes %u)\n", in fw_domain_wait_ack_with_fallback()
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc8379_rdb.dts25 #size-cells = <0>;
27 PowerPC,8379@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>;
35 bus-frequency = <0>;
36 clock-frequency = <0>;
42 reg = <0x00000000 0x10000000>; // 256MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
56 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
24 .base = 0, .len = 0x494,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa33
[all...]
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dcoredump.c19 {0x800, 0x810},
20 {0x820, 0x82C},
21 {0x830, 0x8F4},
22 {0x90C, 0x91C},
23 {0xA14, 0xA18},
24 {0xA84, 0xA94},
25 {0xAA8, 0xAD4},
26 {0xADC, 0xB40},
27 {0x1000, 0x10A4},
28 {0x10BC, 0x111C},
[all …]

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