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/openbmc/u-boot/arch/mips/dts/
H A Dar934x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
53 reg = <0x1b000100 0x100>;
60 reg = <0x18020000 0x20>;
66 gmac0: eth@0x19000000 {
68 reg = <0x19000000 0x200>;
76 #size-cells = <0>;
77 phy0: ethernet-phy@0 {
[all …]
H A Dar933x.dtsi16 #size-cells = <0>;
18 cpu@0 {
21 reg = <0>;
31 #clock-cells = <0>;
43 reg = <0x18040000 0x100>;
62 reg = <0x1b000100 0x100>;
69 reg = <0x18020000 0x20>;
74 gmac0: eth@0x19000000 {
76 reg = <0x19000000 0x200>;
84 #size-cells = <0>;
[all …]
H A Djz4780.dtsi11 #address-cells = <0>;
19 reg = <0x10001000 0x50>;
30 #clock-cells = <0>;
35 #clock-cells = <0>;
41 reg = <0x10000000 0x100>;
51 reg = <0x13450000 0x1000>;
61 reg = <0x13460000 0x1000>;
71 reg = <0x10030000 0x100>;
85 reg = <0x10031000 0x100>;
99 reg = <0x10032000 0x100>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,jpgdecsys.txt20 reg = <0 0x19000000 0 0x1000>;
H A Dmediatek,vencltsys.txt20 reg = <0 0x19000000 0 0x1000>;
H A Dmediatek,ipu.txt23 reg = <0 0x19000000 0 0x1000>;
29 reg = <0 0x19010000 0 0x1000>;
35 reg = <0 0x19180000 0 0x1000>;
41 reg = <0 0x19280000 0 0x1000>;
/openbmc/u-boot/arch/arm/include/asm/iproc-common/
H A Dsysmap.h9 #define IHOST_PROC_CLK_PLLARMA 0X19000C00
10 #define IHOST_PROC_CLK_PLLARMB 0X19000C04
13 #define IHOST_PROC_CLK_WR_ACCESS 0X19000000
14 #define IHOST_PROC_CLK_POLICY_FREQ 0X19000008
19 #define IHOST_PROC_CLK_POLICY_CTL 0X1900000C
20 #define IHOST_PROC_CLK_POLICY_CTL__GO 0
22 #define IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_R 0
25 #define IHOST_PROC_CLK_POLICY_FREQ__POLICY0_FREQ_R 0
28 #define IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_RESETB 0
29 #define IHOST_PROC_CLK_CORE0_CLKGATE 0X19000200
[all …]
/openbmc/linux/drivers/net/ethernet/renesas/
H A Drcar_gen4_ptp.h12 #define PTPTIVC_INIT 0x19000000 /* 320MHz */
14 #define RCAR_GEN4_GPTP_OFFSET_S4 0x00018000
22 #define RCAR_GEN4_RXTSTAMP_ENABLED BIT(0)
27 #define RCAR_GEN4_TXTSTAMP_ENABLED BIT(0)
29 #define PTPRO 0
32 PTPTMEC = PTPRO + 0x0010,
33 PTPTMDC = PTPRO + 0x0014,
34 PTPTIVC0 = PTPRO + 0x0020,
35 PTPTOVC00 = PTPRO + 0x0030,
36 PTPTOVC10 = PTPRO + 0x0034,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml14 pattern: "^memory-controller@[0-9a-f]+$"
40 ".*@[0-9]+$":
60 reg = <0x13410000 0x10000>;
63 ranges = <1 0 0x1b000000 0x1000000>,
64 <2 0 0x1a000000 0x1000000>,
65 <3 0 0x19000000 0x1000000>,
66 <4 0 0x18000000 0x1000000>,
67 <5 0 0x17000000 0x1000000>,
68 <6 0 0x16000000 0x1000000>;
77 pinctrl-0 = <&pins_nemc_cs6>;
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite4/recipes-yosemite4/plat-svc/files/
H A Dyosemite4-early-sys-init40 echo "1" > /sys/bus/i3c/devices/i3c-0/hotjoin
44 for host_bus in $(seq 0 7);
67 set_gpio FM_BMC_RTCRST_R 0
71 set_gpio EN_P3V_BAT_SCALED_R 0
72 set_gpio FM_BMC_SLED_CYCLE_R 0
86 devmem 0x1e78008c 32 0x19000000
89 devmem 0x1E78A604 32 0x00487006
101 exit 0
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml66 reg = <0x13410000 0x10000>;
69 ranges = <1 0 0x1b000000 0x1000000>,
70 <2 0 0x1a000000 0x1000000>,
71 <3 0 0x19000000 0x1000000>,
72 <4 0 0x18000000 0x1000000>,
73 <5 0 0x17000000 0x1000000>,
74 <6 0 0x16000000 0x1000000>;
80 reg = <1 0 0x1000000>;
83 #size-cells = <0>;
94 pinctrl-0 = <&pins_nemc>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dar9331.txt26 reg = <0x19000000 0x200>;
40 reg = <0x1a000000 0x200>;
56 #size-cells = <0>;
60 #size-cells = <0>;
63 reg = <0x10>;
75 #size-cells = <0>;
77 switch_port0: port@0 {
78 reg = <0x0>;
90 reg = <0x1>;
96 reg = <0x2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegrator.dtsi12 reg = <0x0 0x0>;
17 reg = <0x10000000 0x200>;
18 ranges = <0x0 0x10000000 0x200>;
23 led@c,0 {
25 reg = <0x0c 0x04>;
26 offset = <0x0c>;
27 mask = <0x01>;
36 reg = <0x12000000 0x100>;
40 reg = <0x13000000 0x100>;
46 reg = <0x13000100 0x100>;
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-cygnus-clock.dtsi39 #clock-cells = <0>;
46 #clock-cells = <0>;
49 reg = <0x19000000 0x1000>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
73 reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
81 #clock-cells = <0>;
90 #clock-cells = <0>;
100 reg = <0x0301d02c 0x1c>, <0x0301c020 0x4>;
109 reg = <0x180a9800 0x2c>, <0x0301c020 0x4>, <0x180aa024 0x4>;
[all …]
H A Dbcm-hr2.dtsi45 #size-cells = <0>;
47 cpu0: cpu@0 {
51 reg = <0x0>;
64 ranges = <0x00000000 0x19000000 0x00023000>;
68 a9pll: arm_clk@0 {
69 #clock-cells = <0>;
72 reg = <0x0 0x1000>;
77 reg = <0x20200 0x100>;
84 reg = <0x20600 0x20>;
92 reg = <0x20620 0x20>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar71xx.yaml78 reg = <0x19000000 0x200>;
90 reg = <0x1a000000 0x200>;
106 #size-cells = <0>;
110 reg = <0x10>;
122 #size-cells = <0>;
124 switch_port0: port@0 {
125 reg = <0x0>;
137 reg = <0x1>;
143 reg = <0x2>;
149 reg = <0x3>;
[all …]
/openbmc/linux/arch/mips/sni/
H A Da20r.c30 PORT(0x3f8, 4),
31 PORT(0x2f8, 3),
45 .start = 0x1c081ffc,
46 .end = 0x1c081fff,
59 .start = 0x18000000,
60 .end = 0x18000004,
64 .start = 0x18010000,
65 .end = 0x18010004,
69 .start = 0x1ff00000,
70 .end = 0x1ff00020,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1022ds.dtsi36 nor@0,0 {
40 reg = <0x0 0x0 0x8000000>;
44 partition@0 {
45 reg = <0x0 0x03000000>;
51 reg = <0x03000000 0x00e00000>;
57 reg = <0x03e00000 0x00200000>;
63 reg = <0x04000000 0x00400000>;
69 reg = <0x04400000 0x03b00000>;
74 reg = <0x07f00000 0x00080000>;
80 reg = <0x07f80000 0x00080000>;
[all …]
/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9331.dtsi12 #size-cells = <0>;
14 cpu@0 {
18 reg = <0>;
34 #clock-cells = <0>;
57 reg = <0x18000000 0x100>;
64 reg = <0x18020000 0x14>;
76 reg = <0x18040000 0x34>;
92 reg = <0x18050000 0x100>;
102 reg = <0x18060010 0x8>;
113 reg = <0x1806001c 0x4>;
[all …]
/openbmc/linux/arch/mips/pci/
H A Dpci-lantiq.c27 #define PCI_CR_FCI_ADDR_MAP0 0x00C0
28 #define PCI_CR_FCI_ADDR_MAP1 0x00C4
29 #define PCI_CR_FCI_ADDR_MAP2 0x00C8
30 #define PCI_CR_FCI_ADDR_MAP3 0x00CC
31 #define PCI_CR_FCI_ADDR_MAP4 0x00D0
32 #define PCI_CR_FCI_ADDR_MAP5 0x00D4
33 #define PCI_CR_FCI_ADDR_MAP6 0x00D8
34 #define PCI_CR_FCI_ADDR_MAP7 0x00DC
35 #define PCI_CR_CLK_CTRL 0x0000
36 #define PCI_CR_PCI_MOD 0x0030
[all …]
/openbmc/linux/arch/arm/mach-versatile/
H A Dintegrator-hardware.h14 #define IO_BASE 0xF0000000 // VA of IO
15 #define IO_SIZE 0x0B000000 // How much?
19 #define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
25 #define INTEGRATOR_BOOT_ROM_LO 0x00000000
26 #define INTEGRATOR_BOOT_ROM_HI 0x20000000
40 #define INTEGRATOR_SSRAM_BASE 0x00000000
41 #define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
44 #define INTEGRATOR_FLASH_BASE 0x24000000
47 #define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
53 #define INTEGRATOR_SDRAM_BASE 0x00040000
[all …]
/openbmc/u-boot/board/renesas/sh7752evb/
H A Dlowlevel_init.S43 PDCR_A: .long 0xffec0006
44 PGCR_A: .long 0xffec000c
45 PJCR_A: .long 0xffec0012
46 PTCR_A: .long 0xffec0026
47 PSEL1_A: .long 0xffec0072
48 PSEL2_A: .long 0xffec0074
49 PSEL5_A: .long 0xffec007a
51 PDCR_D: .long 0x0000
52 PGCR_D: .long 0x0004
53 PJCR_D: .long 0x0000
[all …]
/openbmc/u-boot/board/renesas/sh7753evb/
H A Dlowlevel_init.S28 mov #0, r14
39 /* If CPU runs on SDRAM (PC=0x5???????) or not. */
40 PC_MASK: .long 0x20000000
66 cmp/eq #0, r0
200 EXPEVT_A: .long 0xff000024
201 EXPEVT_POWER_ON_RESET: .long 0x00000000
204 MRSTCR0_A: .long 0xffd50030
205 MRSTCR0_D: .long 0xfe1ffe7f
206 MRSTCR1_A: .long 0xffd50034
207 MRSTCR1_D: .long 0xfff3ffff
[all …]
/openbmc/u-boot/board/renesas/sh7757lcr/
H A Dlowlevel_init.S73 PGDR_A: .long 0xffec0040
74 PACR_A: .long 0xffec0000
75 PBCR_A: .long 0xffec0002
76 PCCR_A: .long 0xffec0004
77 PDCR_A: .long 0xffec0006
78 PECR_A: .long 0xffec0008
79 PFCR_A: .long 0xffec000a
80 PGCR_A: .long 0xffec000c
81 PHCR_A: .long 0xffec000e
82 PICR_A: .long 0xffec0010
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt6797.dtsi25 #size-cells = <0>;
27 cpu0: cpu@0 {
31 reg = <0x000>;
38 reg = <0x001>;
45 reg = <0x002>;
52 reg = <0x003>;
59 reg = <0x100>;
66 reg = <0x101>;
73 reg = <0x102>;
80 reg = <0x103>;
[all …]

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