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/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Dgaudi2_blocks_linux_driver.h16 #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull
17 #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000
18 #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000
19 #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull
20 #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000
21 #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000
22 #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull
23 #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000
24 #define DCORE0_TPC0_EML_ETF_SECTION 0x1000
25 #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dversatile.yaml38 - const: 0x1800
39 - const: 0
40 - const: 0
58 reg = <0x10001000 0x1000>,
59 <0x41000000 0x10000>,
60 <0x42000000 0x100000>;
61 bus-range = <0 0xff>;
67 <0x01000000 0 0x00000000 0x43000000 0 0x00010000>, /* downstream I/O */
68 <0x02000000 0 0x50000000 0x50000000 0 0x10000000>, /* non-prefetchable memory */
69 <0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
[all …]
H A Dintel,ixp4xx-pci.yaml54 - const: 0xf800
55 - const: 0
56 - const: 0
73 reg = <0xc0000000 0x1000>;
77 bus-range = <0x00 0xff>;
80 <0x02000000 0 0x48000000 0x48000000 0 0x04000000>,
81 <0x01000000 0 0x00000000 0x4c000000 0 0x00010000>;
83 <0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
86 interrupt-map-mask = <0xf800 0 0 7>;
88 <0x0800 0 0 1 &gpio0 11 3>, /* INT A on slot 1 is irq 11 */
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dversatile-pb.dts11 clear-mask = <0xffffffff>;
16 valid-mask = <0x7fe003ff>;
21 reg = <0x101e6000 0x1000>;
33 reg = <0x101e7000 0x1000>;
46 reg = <0x10001000 0x1000
47 0x41000000 0x10000
48 0x42000000 0x100000>;
49 bus-range = <0 0xff>;
54 ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000 /* downstream I/O */
55 0x02000000 0 0x50000000 0x50000000 0 0x10000000 /* non-prefetchable memory */
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp4xx-reference-design.dtsi9 memory@0 {
15 reg = <0x00000000 0x4000000>;
32 #size-cells = <0>;
40 reg = <0x50>;
50 nand-controller@3,0 {
62 intel,ixp4xx-eb-t1 = <0>;
63 intel,ixp4xx-eb-t2 = <0>;
65 intel,ixp4xx-eb-t4 = <0>;
66 intel,ixp4xx-eb-t5 = <0>;
67 intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
[all …]
H A Dintel-ixp42x-linksys-nslu2.dts17 memory@0 {
20 reg = <0x00000000 0x2000000>;
36 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
79 #size-cells = <0>;
83 reg = <0x6f>;
101 flash@0,0 {
105 * 8 MB of Flash in 0x20000 byte blocks
108 reg = <0 0x00000000 0x800000>;
112 /* Eraseblock at 0x7e0000 */
113 fis-index-block = <0x3f>;
[all …]
H A Dintel-ixp42x-gateworks-gw2348.dts18 memory@0 {
20 reg = <0x00000000 0x4000000>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
68 flash@0,0 {
74 reg = <0 0x00000000 0x1000000>;
78 /* Eraseblock at 0x0fe0000 */
79 fis-index-block = <0x7f>;
[all …]
H A Dintel-ixp42x-iomega-nas100d.dts17 memory@0 {
20 reg = <0x00000000 0x4000000>;
36 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
77 #size-cells = <0>;
81 reg = <0x51>;
94 flash@0,0 {
98 * 8 MB of Flash in 0x20000 byte blocks
101 reg = <0 0x00000000 0x800000>;
105 /* Eraseblock at 0x7e0000 */
106 fis-index-block = <0x3f>;
[all …]
H A Dintel-ixp42x-dlink-dsm-g600.dts22 memory@0 {
25 reg = <0x00000000 0x4000000>;
41 gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
87 #size-cells = <0>;
91 reg = <0x51>;
104 flash@0,0 {
108 * 16 MB of Flash in 128 0x20000 sized blocks
111 reg = <0 0x00000000 0x1000000>;
116 * A boot log says the directory is at 0xfe0000
117 * 0x7f * 0x20000 = 0xfe0000
[all …]
H A Dintel-ixp43x-gateworks-gw2358.dts16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 gpios = <&pld1 0 GPIO_ACTIVE_LOW>;
47 #size-cells = <0>;
51 reg = <0x28>;
55 reg = <0x68>;
59 reg = <0x51>;
66 reg = <0x56>;
73 reg = <0x57>;
81 flash@0,0 {
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/catalog/
H A Ddpu_4_0_sdm845.h12 .max_mixer_blendstages = 0xb,
26 .base = 0x0, .len = 0x45c,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_6_0_sm8250.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_5_0_sm8150.h12 .max_mixer_blendstages = 0xb,
26 .base = 0x0, .len = 0x45c,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_5_1_sc8180x.h12 .max_mixer_blendstages = 0xb,
26 .base = 0x0, .len = 0x45c,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_9_0_sm8550.h12 .max_mixer_blendstages = 0xb,
24 .base = 0, .len = 0x494,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 },
[all …]
H A Ddpu_8_1_sm8450.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_7_0_sm8350.h12 .max_mixer_blendstages = 0xb,
24 .base = 0x0, .len = 0x494,
26 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
27 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
28 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
29 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
30 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
31 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
32 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
33 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
[all …]
H A Ddpu_3_0_msm8998.h12 .max_mixer_blendstages = 0x7,
26 .base = 0x0, .len = 0x458,
29 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
36 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 12 },
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3399-dmc.txt22 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
25 reg = <0x0 0xffa80000 0x0 0x0800
26 0x0 0xffa80800 0x0 0x1800
27 0x0 0xffa82000 0x0 0x2000
28 0x0 0xffa84000 0x0 0x1000
29 0x0 0xffa88000 0x0 0x0800
30 0x0 0xffa88800 0x0 0x1800
31 0x0 0xffa8a000 0x0 0x2000
32 0x0 0xffa8c000 0x0 0x1000>;
37 0x2
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dholly.dts23 #size-cells =<0>;
24 PowerPC,750CL@0 {
26 reg = <0x00000000>;
39 memory@0 {
41 reg = <0x00000000 0x20000000>;
49 ranges = <0x00000000 0xc0000000 0x00010000>;
50 reg = <0xc0000000 0x00010000>;
56 interrupts = <0xe 0x2>;
57 reg = <0x00007000 0x00000400>;
62 reg = <0x00006000 0x00000050>;
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_smx.h14 #define L3_COMPONENT 0x000
15 #define L3_CORE 0x018
16 #define L3_AGENT_CONTROL 0x020
17 #define L3_AGENT_STATUS 0x028
18 #define L3_ERROR_LOG 0x058
23 #define L3_ERROR_LOG_ADDR 0x060
26 #define L3_SI_CONTROL 0x020
27 #define L3_SI_FLAG_STATUS_0 0x510
31 #define L3_STATUS_0_MPUIA_BRST (shift << 0)
95 #define L3_SI_FLAG_STATUS_1 0x530
[all …]
/openbmc/linux/arch/xtensa/boot/dts/
H A Dvirt.dts14 memory@0 {
16 reg = <0x00000000 0x80000000>;
21 #size-cells = <0>;
22 cpu@0 {
24 reg = <0>;
31 #clock-cells = <0>;
40 * two cells: second cell == 0: internal irq number
43 #address-cells = <0>;
53 #interrupt-cells = <0x1>;
55 bus-range = <0x0 0x3e>;
[all …]
/openbmc/linux/include/linux/mfd/wm831x/
H A Dregulator.h14 * R16462 (0x404E) - Current Sink 1
16 #define WM831X_CS1_ENA 0x8000 /* CS1_ENA */
17 #define WM831X_CS1_ENA_MASK 0x8000 /* CS1_ENA */
20 #define WM831X_CS1_DRIVE 0x4000 /* CS1_DRIVE */
21 #define WM831X_CS1_DRIVE_MASK 0x4000 /* CS1_DRIVE */
24 #define WM831X_CS1_SLPENA 0x1000 /* CS1_SLPENA */
25 #define WM831X_CS1_SLPENA_MASK 0x1000 /* CS1_SLPENA */
28 #define WM831X_CS1_OFF_RAMP_MASK 0x0C00 /* CS1_OFF_RAMP - [11:10] */
31 #define WM831X_CS1_ON_RAMP_MASK 0x0300 /* CS1_ON_RAMP - [9:8] */
34 #define WM831X_CS1_ISEL_MASK 0x003F /* CS1_ISEL - [5:0] */
[all …]
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64v_4core_virtio.dts12 #address-cells = <0>;
22 ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
23 0 0x3ff00000 0 0x3ff00000 0x100000
24 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
28 reg = <0 0x3ff01400 0x64>;
37 loongson,parent_int_map = <0x00000001>, /* int0 */
38 <0xfffffffe>, /* int1 */
39 <0x00000000>, /* int2 */
40 <0x00000000>; /* int3 */
46 reg = <0 0x1fe001e0 0x8>;
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Dibm-power9-dual.dtsi5 cfam@0,0 {
6 reg = <0 0>;
9 chip-id = <0>;
13 reg = <0x1000 0x400>;
18 reg = <0x1800 0x400>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
23 reg = <0>;
85 reg = <0x2400 0x400>;
87 #size-cells = <0>;
[all …]

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