Searched +full:0 +full:x14e00000 (Results 1 – 6 of 6) sorted by relevance
12 reg = <0x14e00000 0x4>;14 #size-cells = <0>;17 cpu@0 {20 reg = <0>;38 #clock-cells = <0>;52 reg = <0x12000000 0x1000>;58 reg = <0x14e00294 0x1c>;70 reg = <0x14e00500 0x18>;78 reg = <0x14e002d0 0xc>;84 reg = <0x14e002dc 0xc>;[all …]
19 reg = <0x14e00000 0x4>;21 #size-cells = <0>;24 cpu@0 {27 reg = <0>;47 #clock-cells = <0>;54 reg = <0x14e00004 0x4>;60 reg = <0x14e00008 0x4>;73 reg = <0x12000000 0x1000>;79 reg = <0x14e0008c 0x4>;85 reg = <0x14e00090 0x4>;[all …]
68 reg = <0x10720000 0x1000>;75 reg = <0x11d03000 0x1000>;82 reg = <0x11e05000 0x1000>;89 reg = <0x13fbf000 0x1000>;96 reg = <0x14e00000 0x1000>;103 reg = <0x14e02000 0x1000>;110 reg = <0x14e03000 0x1000>;117 reg = <0x15000000 0x1000>;124 reg = <0x15110000 0x1000>;131 reg = <0x15130000 0x1000>;[all …]
16 #size-cells = <0>;20 cpu@0 {23 reg = <0>;62 reg = <0x0c000000 0x600000>;63 ranges = <0x0 0x0c000000 0x600000>;68 reg = <0x5f0000 0x8000>;78 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 0: dsp0 */79 0xa40 8 0xa40 8 0x840 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 1: dsp1 */80 0xa44 8 0xa44 8 0x844 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 2: dsp2 */81 0xa48 8 0xa48 8 0x848 8 (ASSERT_CLEAR | DEASSERT_SET | STATUS_CLEAR) /* 3: dsp3 */[all …]
45 #clock-cells = <0>;50 #size-cells = <0>;52 cpu_atlas0: cpu@0 {55 reg = <0x0>;57 i-cache-size = <0xc000>;60 d-cache-size = <0x8000>;69 reg = <0x1>;71 i-cache-size = <0xc000>;74 d-cache-size = <0x8000>;83 reg = <0x2>;[all …]
51 #size-cells = <0>;53 cpu0: cpu@0 {56 reg = <0x000>;58 performance-domains = <&performance 0>;75 reg = <0x100>;77 performance-domains = <&performance 0>;94 reg = <0x200>;96 performance-domains = <&performance 0>;113 reg = <0x300>;115 performance-domains = <&performance 0>;[all …]