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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-jozacp.dts25 led-0 {
28 function-enumerator = <0>;
29 pwms = <&pwm1 0 10000000 0>;
37 pwms = <&pwm3 0 10000000 0>;
45 pwms = <&pwm5 0 10000000 0>;
59 pwms = <&pwm2 0 10000000 0>;
67 pwms = <&pwm4 0 10000000 0>;
75 pwms = <&pwm6 0 10000000 0>;
98 pinctrl-0 = <&pinctrl_vbus>;
110 pinctrl-0 = <&pinctrl_wifi_npd>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Dmarvell,mv64xxx-i2c.yaml118 reg = <0x11000 0x20>;
126 reg = <0x11000 0x100>;
134 reg = <0x701000 0x20>;
/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dsrio.txt9 Revision Register (SRIO IPBRR1) Major ID equal to 0x01c0.
20 be set to 0x11000.
83 reg = <0xf 0xfe0c0000 0 0x11000>;
94 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
102 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
H A Dmpc5121-psc.txt55 cell-index = <0>;
56 reg = <0x11000 0x100>;
57 interrupts = <40 0x8>;
66 reg = <0x11100 0x100>;
67 interrupts = <40 0x8>;
75 reg = <0x11f00 0x100>;
76 interrupts = <40 0x8>;
/openbmc/linux/drivers/media/pci/cx25821/
H A Dcx25821-sram.h12 /* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */
17 /* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */
27 /* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */
29 /* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */
37 /* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */
40 #define RX_SRAM_START 0x10000
41 #define VID_A_DOWN_CMDS 0x10000
42 #define VID_B_DOWN_CMDS 0x10050
43 #define VID_C_DOWN_CMDS 0x100A0
44 #define VID_D_DOWN_CMDS 0x100F0
[all …]
/openbmc/qemu/tests/qemu-iotests/
H A D07725 seq=`basename $0`
34 trap "_cleanup; exit \$status" 0 1 2 3 15
57 aio_write -P 10 0x200 0x200
62 off=0x1000
66 aio_write -P 10 $((off + 0x200)) 0x200
68 aio_write -P 11 $((off + 0x400)) 0x200
73 off=$((off + 0x1000))
79 aio_write -P 10 0x5000 0x200
81 aio_write -P 11 0x5200 0x200
82 aio_write -P 12 0x5400 0x200
[all …]
/openbmc/linux/sound/sh/
H A Daica.h11 #define G2_FIFO 0xa05f688c
12 #define SPU_MEMORY_BASE 0xA0800000
13 #define ARM_RESET_REGISTER 0xA0702C00
14 #define SPU_REGISTER_BASE 0xA0700000
17 #define AICA_CONTROL_POINT 0xA0810000
18 #define AICA_CONTROL_CHANNEL_SAMPLE_NUMBER 0xA0810008
19 #define AICA_CHANNEL0_CONTROL_OFFSET 0x10004
22 #define AICA_CMD_KICK 0x80000000
23 #define AICA_CMD_NONE 0
30 #define SM_16BIT 0
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dlpc32xx-mlc.txt28 reg = <0x200A8000 0x11000>;
29 interrupts = <11 0>;
44 reg = <0x00000000 0x00064000>;
/openbmc/u-boot/include/configs/
H A Dimx7_spl.h16 * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to
17 * 0x00946C00.
18 * - Set the stack at the end of the free area section, at 0x00946BB8.
21 * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000.
24 #define CONFIG_SPL_TEXT_BASE 0x00911000
25 #define CONFIG_SPL_MAX_SIZE 0x10000
26 #define CONFIG_SPL_STACK 0x00946BB8
32 #define CONFIG_SPL_PAD_TO 0x11000
49 #define CONFIG_SPL_BSS_START_ADDR 0x88200000
50 #define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
[all …]
H A Dimx6_spl.h12 * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
14 * - BOOT ROM stack is at 0x0091FFB8
16 * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
17 * fit between 0x00907000 and 0x00918000.
20 * and some padding thus 'our' max size is really 0x00908000 - 0x00918000
23 #define CONFIG_SPL_TEXT_BASE 0x00908000
24 #define CONFIG_SPL_MAX_SIZE 0x10000
25 #define CONFIG_SPL_STACK 0x0091FFB8
31 #define CONFIG_SPL_PAD_TO 0x11000
41 #define CONFIG_SPL_SATA_BOOT_DEVICE 0
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/include/mach/
H A Dorion5x.h22 #define ORION5X_DRAM_BASE (ORION5X_REGISTER(0x01500))
23 #define ORION5X_TWSI_BASE (ORION5X_REGISTER(0x11000))
24 #define ORION5X_UART0_BASE (ORION5X_REGISTER(0x12000))
25 #define ORION5X_UART1_BASE (ORION5X_REGISTER(0x12100))
26 #define ORION5X_MPP_BASE (ORION5X_REGISTER(0x10000))
27 #define ORION5X_GPIO_BASE (ORION5X_REGISTER(0x10100))
28 #define ORION5X_CPU_WIN_BASE (ORION5X_REGISTER(0x20000))
29 #define ORION5X_CPU_REG_BASE (ORION5X_REGISTER(0x20100))
30 #define ORION5X_TIMER_BASE (ORION5X_REGISTER(0x20300))
31 #define ORION5X_REG_PCI_BASE (ORION5X_REGISTER(0x30000))
[all …]
/openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/
H A Dsoc.h16 #define INTREG_BASE 0xd0000000
18 #define KW_OFFSET_REG (INTREG_BASE + 0x20080)
21 #define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470))
22 #define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478))
24 #define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500))
25 #define KW_TWSI_BASE (KW_REGISTER(0x11000))
26 #define KW_UART0_BASE (KW_REGISTER(0x12000))
27 #define KW_UART1_BASE (KW_REGISTER(0x12100))
28 #define KW_MPP_BASE (KW_REGISTER(0x10000))
29 #define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100))
[all …]
/openbmc/linux/arch/m68k/include/asm/
H A Dapollohw.h52 #define IO_BASE 0x80000000
62 #define SAU7_SIO01_PHYSADDR 0x10400
63 #define SAU7_SIO23_PHYSADDR 0x10500
64 #define SAU7_RTC_PHYSADDR 0x10900
65 #define SAU7_PICA 0x11000
66 #define SAU7_PICB 0x11100
67 #define SAU7_CPUCTRL 0x10100
68 #define SAU7_TIMER 0x010800
70 #define SAU8_SIO01_PHYSADDR 0x8400
71 #define SAU8_RTC_PHYSADDR 0x8900
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/davinci/
H A Dpll.txt30 - #clock-cells: shall be 0
45 - #clock-cells: shall be 0
51 - #clock-cells: shall be 0
58 reg = <0x11000 0x1000>;
64 #clock-cells = <0>;
72 #clock-cells = <0>;
76 #clock-cells = <0>;
82 reg = <0x21a000 0x1000>;
91 #clock-cells = <0>;
/openbmc/linux/arch/powerpc/platforms/embedded6xx/
H A Dstorcenter.c34 return 0; in storcenter_device_probe()
53 hose->first_busno = bus_range ? bus_range[0] : 0; in storcenter_add_bridge()
54 hose->last_busno = bus_range ? bus_range[1] : 0xff; in storcenter_add_bridge()
56 setup_indirect_pci(hose, MPC10X_MAPB_CNFG_ADDR, MPC10X_MAPB_CNFG_DATA, 0); in storcenter_add_bridge()
63 return 0; in storcenter_add_bridge()
88 mpic = mpic_alloc(NULL, 0, 0, 16, 0, " OpenPIC "); in storcenter_init_IRQ()
93 * I2C is the second internal, so it is at 17, 0x11020. in storcenter_init_IRQ()
95 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in storcenter_init_IRQ()
96 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in storcenter_init_IRQ()
H A Dlinkstation.c32 return 0; in declare_of_platform_devices()
48 " bus 0\n", dev); in linkstation_add_bridge()
53 hose->first_busno = bus_range ? bus_range[0] : 0; in linkstation_add_bridge()
54 hose->last_busno = bus_range ? bus_range[1] : 0xff; in linkstation_add_bridge()
55 setup_indirect_pci(hose, 0xfec00000, 0xfee00000, 0); in linkstation_add_bridge()
61 return 0; in linkstation_add_bridge()
87 mpic = mpic_alloc(NULL, 0, 0, 4, 0, " EPIC "); in linkstation_init_IRQ()
91 mpic_assign_isu(mpic, 0, mpic->paddr + 0x10200); in linkstation_init_IRQ()
94 mpic_assign_isu(mpic, 1, mpic->paddr + 0x11000); in linkstation_init_IRQ()
97 mpic_assign_isu(mpic, 2, mpic->paddr + 0x11100); in linkstation_init_IRQ()
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Db4860qds.dts50 board-control@3,0 {
79 reg = <0x1e>;
84 reg = <0x1f>;
92 reg = <0x7>;
98 reg = <0x6>;
106 reg = <0xf 0xfe0c0000 0 0x11000>;
109 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
112 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
H A Dppa8548.dts22 reg = <0 0 0x0 0x40000000>;
26 reg = <0xf 0xe0005000 0 0x1000>;
27 ranges = <0x0 0x0 0xf 0xff800000 0x00800000>;
31 ranges = <0 0xf 0xe0000000 0x100000>;
50 reg = <0xf 0xe00c0000 0x0 0x11000>;
52 ranges = <0x0 0x0 0x0 0x80000000 0x0 0x40000000>;
58 nor@0 {
62 reg = <0x0 0x0 0x00800000>;
66 partition@0 {
67 reg = <0x0 0x7A0000>;
[all …]
H A Dt2080rdb.dts46 reg = <0xf 0xfe0c0000 0 0x11000>;
49 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
52 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
91 reg = <0x1>;
94 reg = <0x2>;
101 reg = <0xc>;
106 reg = <0xd>;
109 xg_aq1202_phy3: ethernet-phy@0 {
111 reg = <0x0>;
116 reg = <0x1>;
H A Dcyrus_p5020.dts30 size = <0 0x1000000>;
31 alignment = <0 0x1000000>;
34 size = <0 0x400000>;
35 alignment = <0 0x400000>;
38 size = <0 0x2000000>;
39 alignment = <0 0x2000000>;
44 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
48 ranges = <0x0 0xf 0xf4000000 0x200000>;
52 ranges = <0x0 0xf 0xf4200000 0x200000>;
56 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
H A Doca4080.dts58 size = <0 0x1000000>;
59 alignment = <0 0x1000000>;
62 size = <0 0x400000>;
63 alignment = <0 0x400000>;
66 size = <0 0x2000000>;
67 alignment = <0 0x2000000>;
72 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
76 ranges = <0x0 0xf 0xf4000000 0x200000>;
80 ranges = <0x0 0xf 0xf4200000 0x200000>;
84 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
[all …]
/openbmc/linux/drivers/reset/
H A Dreset-qcom-aoss.c30 [AOSS_CC_MSS_RESTART] = {0x10000},
31 [AOSS_CC_CAMSS_RESTART] = {0x11000},
32 [AOSS_CC_VENUS_RESTART] = {0x12000},
33 [AOSS_CC_GPU_RESTART] = {0x13000},
34 [AOSS_CC_DISPSS_RESTART] = {0x14000},
35 [AOSS_CC_WCSS_RESTART] = {0x20000},
36 [AOSS_CC_LPASS_RESTART] = {0x30000},
59 return 0; in qcom_aoss_control_assert()
68 writel(0, data->base + map->reg); in qcom_aoss_control_deassert()
71 return 0; in qcom_aoss_control_deassert()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dcpu_sun9i.h12 #define REGS_AHB0_BASE 0x01C00000
13 #define REGS_AHB1_BASE 0x00800000
14 #define REGS_AHB2_BASE 0x03000000
15 #define REGS_APB0_BASE 0x06000000
16 #define REGS_APB1_BASE 0x07000000
17 #define REGS_RCPUS_BASE 0x08000000
19 #define SUNXI_SRAM_D_BASE 0x08100000
22 #define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000)
23 #define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000)
25 #define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000)
[all …]
/openbmc/linux/arch/mips/include/asm/sn/sn0/
H A Dkldir.h28 * 0x2000000 (32M) +-----------------------------------------+
30 * 0x1F80000 (31.5M) +-----------------------------------------+
32 * 0x1C00000 (30M) +-----------------------------------------+
34 * 0x0800000 (28M) +-----------------------------------------+
36 * 0x1B00000 (27M) +-----------------------------------------+
38 * 0x1A00000 (26M) +-----------------------------------------+
40 * 0x1800000 (24M) +-----------------------------------------+
42 * 0x1600000 (22M) +-----------------------------------------+
48 * 0x190000 (2M--) +-----------------------------------------+
51 * 0x34000 (208K) +-----------------------------------------+
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dmx2x.h16 #define MX2x_AIPI_BASE_ADDR 0x10000000
18 #define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
19 #define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
20 #define MX2x_GPT1_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x03000)
21 #define MX2x_GPT2_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x04000)
22 #define MX2x_GPT3_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x05000)
23 #define MX2x_PWM_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x06000)
24 #define MX2x_RTC_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x07000)
25 #define MX2x_KPP_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x08000)
26 #define MX2x_OWIRE_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x09000)
[all …]

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