Home
last modified time | relevance | path

Searched +full:0 +full:x0c300000 (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,aoss-qmp.yaml61 const: 0
97 reg = <0x0c300000 0x100000>;
99 mboxes = <&apss_shared 0>;
101 #clock-cells = <0>;
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dlowlevel_init.S16 * 0x10: TO1
17 * 0x20: TO2
18 * 0x30: TO3
23 cmp \ret, #0x00
27 addne \ret, \ret, #0x10
34 str r1, [r0, #0x00]
36 str r1, [r0, #0x04]
38 str r1, [r0, #0x08]
47 bic r1, r1, #0x00000FF00
48 bic r1, r1, #0x0000000FF
[all …]
/openbmc/u-boot/include/configs/
H A DBSC9132QDS.h16 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
21 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
26 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
35 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
37 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
38 #define CONFIG_SPL_RELOC_STACK 0x00100000
39 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
40 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
41 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
42 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
[all …]
H A DUCP1020.h27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
80 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
86 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
89 #define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
92 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
118 #define CONFIG_SYS_MEMTEST_END 0x1fffffff
120 #define CONFIG_SYS_CCSRBAR 0xffe00000
140 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
146 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
[all …]
H A Dp1_p2_rdb_pc.h16 #define __SW_BOOT_MASK 0x03
17 #define __SW_BOOT_NOR 0xe4
18 #define __SW_BOOT_SD 0x54
24 #define __SW_BOOT_MASK 0x03
25 #define __SW_BOOT_NOR 0xe0
26 #define __SW_BOOT_SD 0x50
35 #define __SW_BOOT_MASK 0x03
36 #define __SW_BOOT_NOR 0x5c
37 #define __SW_BOOT_SPI 0x1c
38 #define __SW_BOOT_SD 0x9c
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8996.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
52 clocks = <&kryocc 0>;
67 reg = <0x0 0x1>;
71 clocks = <&kryocc 0>;
81 reg = <0x0 0x100>;
100 reg = <0x0 0x101>;
[all …]
H A Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc8180x.dtsi27 #clock-cells = <0>;
33 #clock-cells = <0>;
41 #size-cells = <0>;
43 CPU0: cpu@0 {
46 reg = <0x0 0x0>;
50 qcom,freq-domain = <&cpufreq_hw 0>;
57 clocks = <&cpufreq_hw 0>;
75 reg = <0x0 0x100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
86 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8350.dtsi36 #clock-cells = <0>;
44 #clock-cells = <0>;
50 #size-cells = <0>;
52 CPU0: cpu@0 {
55 reg = <0x0 0x0>;
56 clocks = <&cpufreq_hw 0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7180.dtsi63 #clock-cells = <0>;
69 #clock-cells = <0>;
75 #size-cells = <0>;
77 cpu0: cpu@0 {
80 reg = <0x0 0x0>;
81 clocks = <&cpufreq_hw 0>;
92 qcom,freq-domain = <&cpufreq_hw 0>;
109 reg = <0x0 0x100>;
110 clocks = <&cpufreq_hw 0>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsm8550.dtsi36 #clock-cells = <0>;
41 #clock-cells = <0>;
45 #clock-cells = <0>;
53 #clock-cells = <0>;
62 #clock-cells = <0>;
68 #size-cells = <0>;
70 CPU0: cpu@0 {
73 reg = <0 0>;
74 clocks = <&cpufreq_hw 0>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
[all …]
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]