/openbmc/u-boot/drivers/clk/sunxi/ |
H A D | clk_a10.c | 16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)), 17 [CLK_AHB_EHCI0] = GATE(0x060, BIT(1)), 18 [CLK_AHB_OHCI0] = GATE(0x060, BIT(2)), 19 [CLK_AHB_EHCI1] = GATE(0x060, BIT(3)), 20 [CLK_AHB_OHCI1] = GATE(0x060, BIT(4)), 21 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), 22 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), 23 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), 24 [CLK_AHB_MMC3] = GATE(0x060, BIT(11)), 25 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), [all …]
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H A D | clk_r40.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)), 23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)), 24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)), 25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), [all …]
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H A D | clk_h3.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), 25 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)), [all …]
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H A D | clk_a31.c | 16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)), 20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)), 21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)), 22 [CLK_AHB1_SPI1] = GATE(0x060, BIT(21)), 23 [CLK_AHB1_SPI2] = GATE(0x060, BIT(22)), 24 [CLK_AHB1_SPI3] = GATE(0x060, BIT(23)), 25 [CLK_AHB1_OTG] = GATE(0x060, BIT(24)), [all …]
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H A D | clk_a10s.c | 16 [CLK_AHB_OTG] = GATE(0x060, BIT(0)), 17 [CLK_AHB_EHCI] = GATE(0x060, BIT(1)), 18 [CLK_AHB_OHCI] = GATE(0x060, BIT(2)), 19 [CLK_AHB_MMC0] = GATE(0x060, BIT(8)), 20 [CLK_AHB_MMC1] = GATE(0x060, BIT(9)), 21 [CLK_AHB_MMC2] = GATE(0x060, BIT(10)), 22 [CLK_AHB_EMAC] = GATE(0x060, BIT(17)), 23 [CLK_AHB_SPI0] = GATE(0x060, BIT(20)), 24 [CLK_AHB_SPI1] = GATE(0x060, BIT(21)), 25 [CLK_AHB_SPI2] = GATE(0x060, BIT(22)), [all …]
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H A D | clk_a64.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(23)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)), 25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)), [all …]
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H A D | clk_a83t.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)), 20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 22 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 23 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)), 24 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)), 25 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)), [all …]
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H A D | clk_a23.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)), 21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 22 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)), 23 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)), 25 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 26 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), [all …]
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H A D | clk_v3s.c | 16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), 17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), 18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), 19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), 20 [CLK_BUS_OTG] = GATE(0x060, BIT(24)), 22 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), 23 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), 24 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), 26 [CLK_SPI0] = GATE(0x0a0, BIT(31)), 28 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), [all …]
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/openbmc/linux/drivers/pinctrl/samsung/ |
H A D | pinctrl-exynos-arm64.c | 24 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 29 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 35 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 40 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 49 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 58 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 67 EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 68 EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04), 69 EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08), 70 EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c), [all …]
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H A D | pinctrl-exynos-arm.c | 27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, }, 32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, }, 36 #define S5P_OTHERS 0xE000 73 clk_base = of_iomap(np, 0); in s5pv210_retention_init() 93 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00), 94 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04), 95 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08), 96 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c), 97 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10), 98 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14), [all …]
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/openbmc/linux/drivers/pinctrl/mediatek/ |
H A D | pinctrl-mt8183.c | 13 * iocfg[0]:0x10005000, iocfg[1]:0x11F20000, iocfg[2]:0x11E80000, 14 * iocfg[3]:0x11E70000, iocfg[4]:0x11E90000, iocfg[5]:0x11D30000, 15 * iocfg[6]:0x11D20000, iocfg[7]:0x11C50000, iocfg[8]:0x11F30000. 21 _x_bits, 32, 0) 28 PIN_FIELD(0, 192, 0x300, 0x10, 0, 4), 32 PIN_FIELD(0, 192, 0x0, 0x10, 0, 1), 36 PIN_FIELD(0, 192, 0x200, 0x10, 0, 1), 40 PIN_FIELD(0, 192, 0x100, 0x10, 0, 1), 44 PINS_FIELD_BASE(0, 3, 6, 0x000, 0x10, 3, 1), 45 PINS_FIELD_BASE(4, 7, 6, 0x000, 0x10, 5, 1), [all …]
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H A D | pinctrl-mt8195.c | 13 * iocfg[0]:0x10005000, iocfg[1]:0x11d10000, iocfg[2]:0x11d30000, 14 * iocfg[3]:0x11d40000, iocfg[4]:0x11e20000, iocfg[5]:0x11eb0000, 15 * iocfg[6]:0x11f40000. 21 32, 0) 28 PIN_FIELD(0, 144, 0x300, 0x10, 0, 4), 32 PIN_FIELD(0, 144, 0x0, 0x10, 0, 1), 36 PIN_FIELD(0, 144, 0x200, 0x10, 0, 1), 40 PIN_FIELD(0, 144, 0x100, 0x10, 0, 1), 44 PIN_FIELD_BASE(0, 0, 4, 0x040, 0x10, 0, 1), 45 PIN_FIELD_BASE(1, 1, 4, 0x040, 0x10, 1, 1), [all …]
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/openbmc/linux/drivers/clk/sunxi-ng/ |
H A D | ccu-sun4i-a10.c | 32 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), 34 .m = _SUNXI_CCU_DIV(0, 2), 37 .reg = 0x000, 41 0), 57 #define SUN4I_PLL_AUDIO_REG 0x008 60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 66 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), 67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), 68 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0, [all …]
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H A D | ccu-sun50i-a64.c | 31 .m = _SUNXI_CCU_DIV(0, 2), 34 .reg = 0x000, 54 #define SUN50I_A64_PLL_AUDIO_REG 0x008 57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 62 "osc24M", 0x008, 64 0, 5, /* M */ 66 0x284, BIT(31), 72 "osc24M", 0x010, 76 0, 4, /* M */ [all …]
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H A D | ccu-sun8i-h3.c | 29 "osc24M", 0x000, 32 0, 2, /* M */ 50 #define SUN8I_H3_PLL_AUDIO_REG 0x008 53 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 54 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 58 "osc24M", 0x008, 60 0, 5, /* M */ 62 0x284, BIT(31), 68 "osc24M", 0x0010, 72 0, 4, /* M */ [all …]
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H A D | ccu-sun6i-a31.c | 33 "osc24M", 0x000, 36 0, 2, /* M */ 39 0); 53 #define SUN6I_A31_PLL_AUDIO_REG 0x008 56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 61 "osc24M", 0x008, 63 0, 5, /* M */ 65 0x284, BIT(31), 71 "osc24M", 0x010, [all …]
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H A D | ccu-sun8i-a83t.c | 24 #define CCU_SUN8I_A83T_LOCK_REG 0x20c 33 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000 34 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004 38 .lock = BIT(0), 39 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 53 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0), 68 * which is d1 = 0, d2 = 1. 70 #define SUN8I_A83T_PLL_AUDIO_REG 0x008 74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 }, 75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 }, [all …]
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H A D | ccu-sun5i.c | 28 .n = _SUNXI_CCU_MULT_OFFSET(8, 5, 0), 30 .m = _SUNXI_CCU_DIV(0, 2), 33 .reg = 0x000, 37 0), 53 #define SUN5I_PLL_AUDIO_REG 0x008 56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 62 .n = _SUNXI_CCU_MULT_OFFSET(8, 7, 0), 68 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0), 69 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, 0, [all …]
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H A D | ccu-sun8i-r40.c | 33 .m = _SUNXI_CCU_DIV(0, 2), 36 .reg = 0x000, 56 #define SUN8I_R40_PLL_AUDIO_REG 0x008 59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 64 "osc24M", 0x008, 66 0, 5, /* M */ 68 0x284, BIT(31), 74 "osc24M", 0x0010, 78 0, 4, /* M */ [all …]
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H A D | ccu-sun8i-a33.c | 32 .m = _SUNXI_CCU_DIV(0, 2), 36 .reg = 0x000, 39 0), 55 #define SUN8I_A33_PLL_AUDIO_REG 0x008 58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 63 "osc24M", 0x008, 65 0, 5, /* M */ 67 0x284, BIT(31), 73 "osc24M", 0x010, [all …]
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H A D | ccu-sun8i-a23.c | 34 .m = _SUNXI_CCU_DIV(0, 2), 38 .reg = 0x000, 41 0), 57 #define SUN8I_A23_PLL_AUDIO_REG 0x008 60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 65 "osc24M", 0x008, 67 0, 5, /* M */ 69 0x284, BIT(31), 75 "osc24M", 0x010, [all …]
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H A D | ccu-sun8i-v3s.c | 31 "osc24M", 0x000, 34 0, 2, /* M */ 38 0); 52 #define SUN8I_V3S_PLL_AUDIO_REG 0x008 55 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 }, 56 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 }, 60 "osc24M", 0x008, 62 0, 5, /* M */ 64 0x284, BIT(31), 70 "osc24M", 0x0010, [all …]
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/openbmc/linux/sound/pci/oxygen/ |
H A D | wm8785.h | 5 #define WM8785_R0 0 11 #define WM8785_MCR_MASK 0x007 12 #define WM8785_MCR_SLAVE 0x000 13 #define WM8785_MCR_MASTER_128 0x001 14 #define WM8785_MCR_MASTER_192 0x002 15 #define WM8785_MCR_MASTER_256 0x003 16 #define WM8785_MCR_MASTER_384 0x004 17 #define WM8785_MCR_MASTER_512 0x005 18 #define WM8785_MCR_MASTER_768 0x006 19 #define WM8785_OSR_MASK 0x018 [all …]
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H A D | wm8766.h | 5 #define WM8766_LDA1 0x00 6 #define WM8766_RDA1 0x01 7 #define WM8766_DAC_CTRL 0x02 8 #define WM8766_INT_CTRL 0x03 9 #define WM8766_LDA2 0x04 10 #define WM8766_RDA2 0x05 11 #define WM8766_LDA3 0x06 12 #define WM8766_RDA3 0x07 13 #define WM8766_MASTDA 0x08 14 #define WM8766_DAC_CTRL2 0x09 [all …]
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