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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd938x-sdw.yaml50 #size-cells = <0>;
51 reg = <0x03210000 0x2000>;
52 wcd938x_rx: codec@0,4 {
54 reg = <0 4>;
61 #size-cells = <0>;
62 reg = <0x03230000 0x2000>;
63 wcd938x_tx: codec@0,3 {
65 reg = <0 3>;
H A Dqcom,wcd938x.yaml83 minimum: 0
88 minimum: 0
118 reset-gpios = <&tlmm 32 0>;
136 #size-cells = <0>;
137 reg = <0x03210000 0x2000>;
138 wcd938x_rx: codec@0,4 {
140 reg = <0 4>;
147 #size-cells = <0>;
148 reg = <0x03230000 0x2000>;
149 wcd938x_tx: codec@0,3 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soundwire/
H A Dqcom,soundwire.yaml64 const: 0
80 Value of 0xff indicates that this option is not implemented
91 Value of 0xff indicates that this option is not implemented
102 Value of 0xffff indicates that this option is not implemented
113 Value of 0xff indicates that this option is not implemented
124 Value of 0xff indicates that this option is not implemented
135 Value of 0xff indicates that this option is not implemented
145 0 to indicate Blocks are per Channel
148 Value of 0xff indicates that this option is not implemented
155 - minimum: 0
[all …]
/openbmc/linux/arch/arm/mach-rpc/
H A Decard.c94 return v[0] | v[1] << 8; in ecard_getu16()
99 return v[0] | v[1] << 8 | v[2] << 16 | ((v[2] & 0x80) ? 0xff000000 : 0); in ecard_gets24()
159 * If we are reading offset 0, or our current index is in ecard_task_readbytes()
162 if (off == 0 || index > off) { in ecard_task_readbytes()
163 writeb(0, base); in ecard_task_readbytes()
164 index = 0; in ecard_task_readbytes()
198 *(unsigned long *)0x108 = 0; in ecard_task_readbytes()
220 * 0x03000000 0x03000000 in ecard_init_pgtables()
221 * 0x03010000 unmapped in ecard_init_pgtables()
222 * 0x03210000 0x03210000 in ecard_init_pgtables()
[all …]
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x
[all...]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsm8450.dtsi36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x10
[all...]
H A Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x10
[all...]
H A Dsc7280.dtsi78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x60000
[all...]
H A Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
[all...]