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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
13 reg = <0x4>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
27 reg = <0x4>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
[all …]
H A Domap2420-clocks.dtsi10 #clock-cells = <0>;
14 reg = <0x0070>;
18 #clock-cells = <0>;
22 reg = <0x0070>;
26 #clock-cells = <0>;
32 #clock-cells = <0>;
37 reg = <0x0070>;
42 #clock-cells = <0>;
46 reg = <0x0810>;
50 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/clk/qcom/
H A Dmmcc-msm8960.c45 .l_reg = 0x320,
46 .m_reg = 0x324,
47 .n_reg = 0x328,
48 .config_reg = 0x32c,
49 .mode_reg = 0x31c,
50 .status_reg = 0x334,
63 .l_reg = 0x33c,
64 .m_reg = 0x340,
65 .n_reg = 0x344,
66 .config_reg = 0x348,
[all …]
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dgdb-config.c.inc23 XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x0100,pc, 0,0,0,0,0,0)
24 XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
25 XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
26 XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
27 XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
28 XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
29 XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
30 XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
31 XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
32 XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
[all …]
/openbmc/linux/drivers/clk/mediatek/
H A Dclk-mt7986-apmixed.c43 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x0, PLL_AO, 32,
44 0x0200, 4, 0, 0x0204, 0),
45 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x0, 0, 32,
46 0x0210, 4, 0, 0x0214, 0),
47 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x0, 0, 32,
48 0x0220, 4, 0, 0x0224, 0),
49 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x0, 0, 32,
50 0x0230, 4, 0, 0x0234, 0),
51 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x0, 0,
52 32, 0x0240, 4, 0, 0x0244, 0),
[all …]
H A Dclk-mt7981-apmixed.c45 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,
46 32, 0x0200, 4, 0, 0x0204, 0),
47 PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
48 0x0210, 4, 0, 0x0214, 0),
49 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
50 0x0220, 4, 0, 0x0224, 0),
51 PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,
52 0x0230, 4, 0, 0x0234, 0),
53 PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,
54 0x0240, 4, 0, 0x0244, 0),
[all …]
H A Dclk-mt2712-apmixedsys.c53 { .div = 0, .freq = MT2712_PLL_FMAX },
62 { .div = 0, .freq = MT2712_PLL_FMAX },
71 { .div = 0, .freq = MT2712_PLL_FMAX },
80 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x0230, 0x023C, 0xf0000100,
81 HAVE_RST_BAR, 31, 0x0230, 4, 0, 0, 0, 0x0234, 0),
82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x0240, 0x024C, 0xfe000100,
83 HAVE_RST_BAR, 31, 0x0240, 4, 0, 0, 0, 0x0244, 0),
84 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x0320, 0x032C, 0xc0000100,
85 0, 31, 0x0320, 4, 0, 0, 0, 0x0324, 0),
86 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x0280, 0x028C, 0x00000100,
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h13 #define MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x01B0 0x03D8 0x0 0x0
14 #define MX93_PAD_DAP_TDI__MQS2_LEFT 0x0000 0x01B0 0x0000 0x1 0x0
15 #define MX93_PAD_DAP_TDI__CAN2_TX 0x0000 0x01B0 0x0000 0x3 0x0
16 #define MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30 0x0000 0x01B0 0x0000 0x4 0x0
17 #define MX93_PAD_DAP_TDI__GPIO3_IO28 0x0000 0x01B0 0x0000 0x5 0x0
18 #define MX93_PAD_DAP_TDI__LPUART5_RX 0x0000 0x01B0 0x0430 0x6 0x0
19 #define MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x01B4 0x03DC 0x0 0x0
20 #define MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31 0x0004 0x01B4 0x0000 0x4 0x0
21 #define MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29 0x0004 0x01B4 0x0000 0x5 0x0
22 #define MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x01B4 0x0000 0x6 0x0
[all …]
/openbmc/linux/drivers/media/platform/mediatek/jpeg/
H A Dmtk_jpeg_dec_reg.h14 #define BIT_INQST_MASK_ERROR_BS 0x20
15 #define BIT_INQST_MASK_PAUSE 0x10
16 #define BIT_INQST_MASK_OVERFLOW 0x04
17 #define BIT_INQST_MASK_UNDERFLOW 0x02
18 #define BIT_INQST_MASK_EOF 0x01
19 #define BIT_INQST_MASK_ALLIRQ 0x37
21 #define JPGDEC_REG_RESET 0x0090
22 #define JPGDEC_REG_BRZ_FACTOR 0x00f8
23 #define JPGDEC_REG_DU_NUM 0x00fc
24 #define JPGDEC_REG_DEST_ADDR0_Y 0x0140
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dcm2_7xx.h23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
/openbmc/qemu/util/
H A Dcrc-ccitt.c20 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
24 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
25 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
26 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
27 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
28 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
29 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
30 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
31 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
32 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
/openbmc/linux/lib/
H A Dcrc-ccitt.c13 * be seen in entry 128, 0x8408. This corresponds to x^0 + x^5 + x^12.
17 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
18 0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
19 0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
20 0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
21 0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
22 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
23 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
24 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
25 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa320.c26 MFP_ADDR_X(GPIO0, GPIO4, 0x0124),
27 MFP_ADDR_X(GPIO5, GPIO9, 0x028C),
28 MFP_ADDR(GPIO10, 0x0458),
29 MFP_ADDR_X(GPIO11, GPIO26, 0x02A0),
30 MFP_ADDR_X(GPIO27, GPIO48, 0x0400),
31 MFP_ADDR_X(GPIO49, GPIO62, 0x045C),
32 MFP_ADDR_X(GPIO63, GPIO73, 0x04B4),
33 MFP_ADDR_X(GPIO74, GPIO98, 0x04F0),
34 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
35 MFP_ADDR_X(GPIO0_2, GPIO5_2, 0x0674),
[all …]
H A Dpxa300.c26 MFP_ADDR_X(GPIO0, GPIO2, 0x00b4),
27 MFP_ADDR_X(GPIO3, GPIO26, 0x027c),
28 MFP_ADDR_X(GPIO27, GPIO98, 0x0400),
29 MFP_ADDR_X(GPIO99, GPIO127, 0x0600),
30 MFP_ADDR_X(GPIO0_2, GPIO1_2, 0x0674),
31 MFP_ADDR_X(GPIO2_2, GPIO6_2, 0x02dc),
33 MFP_ADDR(nBE0, 0x0204),
34 MFP_ADDR(nBE1, 0x0208),
36 MFP_ADDR(nLUA, 0x0244),
37 MFP_ADDR(nLLA, 0x0254),
[all …]
/openbmc/linux/drivers/gpu/drm/arm/
H A Dhdlcd_regs.h15 #define HDLCD_REG_VERSION 0x0000 /* ro */
16 #define HDLCD_REG_INT_RAWSTAT 0x0010 /* rw */
17 #define HDLCD_REG_INT_CLEAR 0x0014 /* wo */
18 #define HDLCD_REG_INT_MASK 0x0018 /* rw */
19 #define HDLCD_REG_INT_STATUS 0x001c /* ro */
20 #define HDLCD_REG_FB_BASE 0x0100 /* rw */
21 #define HDLCD_REG_FB_LINE_LENGTH 0x0104 /* rw */
22 #define HDLCD_REG_FB_LINE_COUNT 0x0108 /* rw */
23 #define HDLCD_REG_FB_LINE_PITCH 0x010c /* rw */
24 #define HDLCD_REG_BUS_OPTIONS 0x0110 /* rw */
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxbf_gige/
H A Dmlxbf_gige_regs.h13 #define MLXBF_GIGE_VERSION 0x0000
14 #define MLXBF_GIGE_VERSION_BF2 0x0
15 #define MLXBF_GIGE_VERSION_BF3 0x1
16 #define MLXBF_GIGE_STATUS 0x0010
17 #define MLXBF_GIGE_STATUS_READY BIT(0)
18 #define MLXBF_GIGE_INT_STATUS 0x0028
19 #define MLXBF_GIGE_INT_STATUS_RX_RECEIVE_PACKET BIT(0)
28 #define MLXBF_GIGE_INT_EN 0x0030
29 #define MLXBF_GIGE_INT_EN_RX_RECEIVE_PACKET BIT(0)
38 #define MLXBF_GIGE_INT_MASK 0x0038
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dti,am65-pci-host.yaml88 reg = <0x5500000 0x1000>,
89 <0x5501000 0x1000>,
90 <0x10000000 0x2000>,
91 <0x5506000 0x1000>;
96 ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
97 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
98 ti,syscon-pcie-id = <&scm_conf 0x0210>;
99 ti,syscon-pcie-mode = <&scm_conf 0x4060>;
100 bus-range = <0x0 0xff>;
104 msi-map = <0x0 &gic_its 0x0 0x10000>;
/openbmc/linux/drivers/pmdomain/mediatek/
H A Dmtk-pm-domains.h6 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0)
16 #define SPM_VDE_PWR_CON 0x0210
17 #define SPM_MFG_PWR_CON 0x0214
18 #define SPM_VEN_PWR_CON 0x0230
19 #define SPM_ISP_PWR_CON 0x0238
20 #define SPM_DIS_PWR_CON 0x023c
21 #define SPM_CONN_PWR_CON 0x0280
22 #define SPM_VEN2_PWR_CON 0x0298
23 #define SPM_AUDIO_PWR_CON 0x029c
24 #define SPM_MFG_2D_PWR_CON 0x02c0
[all …]
/openbmc/linux/drivers/hwtracing/intel_th/
H A Dmsu.h12 REG_MSU_MSUPARAMS = 0x0000,
13 REG_MSU_MSUSTS = 0x0008,
14 REG_MSU_MINTCTL = 0x0004, /* MSU-global interrupt control */
15 REG_MSU_MSC0CTL = 0x0100, /* MSC0 control */
16 REG_MSU_MSC0STS = 0x0104, /* MSC0 status */
17 REG_MSU_MSC0BAR = 0x0108, /* MSC0 output base address */
18 REG_MSU_MSC0SIZE = 0x010c, /* MSC0 output size */
19 REG_MSU_MSC0MWP = 0x0110, /* MSC0 write pointer */
20 REG_MSU_MSC0NWSA = 0x011c, /* MSC0 next window start address */
22 REG_MSU_MSC1CTL = 0x0200, /* MSC1 control */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmux.h23 * M0 - Mode 0
28 #define IDIS (0 << 8)
30 #define PTD (0 << 4)
32 #define DIS (0 << 3)
41 #define M0 0
56 #define CONTROL_PADCONF_SDRC_D0 0x0030
57 #define CONTROL_PADCONF_SDRC_D1 0x0032
58 #define CONTROL_PADCONF_SDRC_D2 0x0034
59 #define CONTROL_PADCONF_SDRC_D3 0x0036
60 #define CONTROL_PADCONF_SDRC_D4 0x0038
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl5039.h26 …_SET_OBJECT 0x0000
27 …_SET_OBJECT_POINTER 15:0
29 …_NO_OPERATION 0x0100
30 …_NO_OPERATION_V 31:0
32 …_SET_CONTEXT_DMA_NOTIFY 0x0180
33 …_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0
35 …_SET_CONTEXT_DMA_BUFFER_IN 0x0184
36 …_SET_CONTEXT_DMA_BUFFER_IN_HANDLE 31:0
38 …_SET_CONTEXT_DMA_BUFFER_OUT 0x0188
39 …_SET_CONTEXT_DMA_BUFFER_OUT_HANDLE 31:0
[all …]
/openbmc/qemu/hw/dma/
H A Drc4030.c52 #define DMA_FLAG_ENABLE 0x0001
53 #define DMA_FLAG_MEM_TO_DEV 0x0002
54 #define DMA_FLAG_TC_INTR 0x0100
55 #define DMA_FLAG_MEM_INTR 0x0200
56 #define DMA_FLAG_ADDR_INTR 0x0400
67 uint32_t config; /* 0x0000: RC4030 config register */
68 uint32_t revision; /* 0x0008: RC4030 Revision register */
69 uint32_t invalid_address_register; /* 0x0010: Invalid Address register */
73 uint32_t dma_tl_base; /* 0x0018: DMA transl. table base */
74 uint32_t dma_tl_limit; /* 0x0020: DMA transl. table limit */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6sll-pinfunc.h17 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
18 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
19 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
20 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
25 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
26 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6sll-pinfunc.h15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
/openbmc/libmctp/
H A Dcrc-16-ccitt.c12 0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf, 0x8c48,
13 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7, 0x1081, 0x0108,
14 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e, 0x9cc9, 0x8d40, 0xbfdb,
15 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876, 0x2102, 0x308b, 0x0210, 0x1399,
16 0x6726, 0x76af, 0x4434, 0x55bd, 0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e,
17 0xfae7, 0xc87c, 0xd9f5, 0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e,
18 0x54b5, 0x453c, 0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd,
19 0xc974, 0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
20 0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3, 0x5285,
21 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a, 0xdecd, 0xcf44,
[all …]

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