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/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dfsl,flexcan.yaml94 maximum: 0xff
96 maximum: 0x1f
104 0: clock source 0 (oscillator clock)
108 minimum: 0
123 minimum: 0
140 reg = <0x1c000 0x1000>;
141 interrupts = <48 0x2>;
144 fsl,clk-source = /bits/ 8 <0>;
151 reg = <0x02090000 0x4000>;
152 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
[all …]
/openbmc/qemu/include/hw/arm/
H A Dfsl-imx6ul.h97 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
116 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
118 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
120 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
121 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
[all …]
H A Dfsl-imx6.h86 #define FSL_IMX6_MMDC_ADDR 0x10000000
87 #define FSL_IMX6_MMDC_SIZE 0xF0000000
88 #define FSL_IMX6_EIM_MEM_ADDR 0x08000000
89 #define FSL_IMX6_EIM_MEM_SIZE 0x8000000
90 #define FSL_IMX6_IPU_2_ADDR 0x02800000
91 #define FSL_IMX6_IPU_2_SIZE 0x400000
92 #define FSL_IMX6_IPU_1_ADDR 0x02400000
93 #define FSL_IMX6_IPU_1_SIZE 0x400000
94 #define FSL_IMX6_MIPI_HSI_ADDR 0x02208000
95 #define FSL_IMX6_MIPI_HSI_SIZE 0x4000
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6ul.dtsi55 #size-cells = <0>;
57 cpu0: cpu@0 {
60 reg = <0>;
98 reg = <0x00a01000 0x1000>,
99 <0x00a02000 0x1000>,
100 <0x00a04000 0x2000>,
101 <0x00a06000 0x2000>;
106 #clock-cells = <0>;
113 #clock-cells = <0>;
120 #clock-cells = <0>;
[all …]
H A Dimx6qdl.dtsi56 #clock-cells = <0>;
62 #clock-cells = <0>;
63 clock-frequency = <0>;
68 #clock-cells = <0>;
76 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
84 #size-cells = <0>;
89 lvds-channel@0 {
91 #size-cells = <0>;
92 reg = <0>;
95 port@0 {
[all …]
H A Dimx6sx.dtsi56 #size-cells = <0>;
58 cpu0: cpu@0 {
61 reg = <0>;
94 reg = <0x00a01000 0x1000>,
95 <0x00a00100 0x100>;
101 #size-cells = <0>;
103 ckil: clock@0 {
105 reg = <0>;
106 #clock-cells = <0>;
114 #clock-cells = <0>;
[all …]
H A Dimx6ull.dtsi53 #size-cells = <0>;
55 cpu0: cpu@0 {
58 reg = <0>;
90 reg = <0x00a01000 0x1000>,
91 <0x00a02000 0x100>;
96 #size-cells = <0>;
98 ckil: clock@0 {
100 reg = <0>;
101 #clock-cells = <0>;
109 #clock-cells = <0>;
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7915/
H A Dsoc.c18 #define MT7981_CON_INFRA_VERSION 0x02090000
19 #define MT7986_CON_INFRA_VERSION 0x02070000
22 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0
23 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4
27 #define MT_INFRACFG_TX_EN_MASK BIT(0)
30 #define MT_TOP_POS_FAST_CTRL 0x114
33 #define MT_TOP_POS_SKU 0x21c
56 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0); in mt76_wmac_spi_read()
66 return 0; in mt76_wmac_spi_read()
118 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0); in mt7986_wmac_adie_efuse_read()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul.dtsi58 #size-cells = <0>;
60 cpu0: cpu@0 {
63 reg = <0>;
108 #clock-cells = <0>;
115 #clock-cells = <0>;
122 #clock-cells = <0>;
123 clock-frequency = <0>;
129 #clock-cells = <0>;
130 clock-frequency = <0>;
149 reg = <0x00900000 0x20000>;
[all …]
H A Dimx6qdl.dtsi59 #clock-cells = <0>;
65 #clock-cells = <0>;
66 clock-frequency = <0>;
71 #clock-cells = <0>;
78 #size-cells = <0>;
83 lvds-channel@0 {
85 #size-cells = <0>;
86 reg = <0>;
89 port@0 {
90 reg = <0>;
[all …]
H A Dimx6sx.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
66 reg = <0>;
100 #clock-cells = <0>;
107 #clock-cells = <0>;
114 #clock-cells = <0>;
115 clock-frequency = <0>;
121 #clock-cells = <0>;
122 clock-frequency = <0>;
128 #clock-cells = <0>;
[all …]