Searched +full:0 +full:x01e60000 (Results 1 – 13 of 13) sorted by relevance
84 port@0:95 - port@0175 reg = <0x01e60000 0x10000>;185 #size-cells = <0>;187 port@0 {189 #size-cells = <0>;190 reg = <0>;192 endpoint@0 {193 reg = <0>;205 #size-cells = <0>;[all …]
11 #define SUNXI_SRAM_A1_BASE 0x0000000014 #define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */15 #define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */16 #define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */17 #define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */18 #define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */20 #define SUNXI_DE2_BASE 0x0100000023 #define SUNXI_CPUCFG_BASE 0x0170000026 #define SUNXI_SRAMC_BASE 0x01c0000027 #define SUNXI_DRAMC_BASE 0x01c01000[all …]
127 cpu@0 {201 sound-dai = <&codec 0>;208 reg = <0x01c0e000 0x1000>;219 reg = <0x01c15000 0x1000>;228 #sound-dai-cells = <0>;230 reg = <0x01c22c00 0x200>;243 reg = <0x01c22e00 0x400>;252 reg = <0x01c25000 0x100>;253 #thermal-sensor-cells = <0>;254 #io-channel-cells = <0>;[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;97 #clock-cells = <0>;104 #clock-cells = <0>;119 size = <0x6000000>;120 alloc-ranges = <0x40000000 0x10000000>;135 reg = <0x01c00000 0x30>;140 sram_a: sram@0 {142 reg = <0x00000000 0xc000>;[all …]
91 #size-cells = <0>;93 cpu0: cpu@0 {96 reg = <0>;112 #clock-cells = <0>;120 #clock-cells = <0>;136 reg = <0x01c00000 0x30>;143 reg = <0x01d00000 0x80000>;146 ranges = <0 0x01d00000 0x80000>;148 ve_sram: sram-section@0 {151 reg = <0x000000 0x80000>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;166 #clock-cells = <0>;173 #clock-cells = <0>;199 size = <0x6000000>;200 alloc-ranges = <0x40000000 0x10000000>;214 reg = <0x01c00000 0x30>;219 sram_a: sram@0 {221 reg = <0x00000000 0xc000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;213 #clock-cells = <0>;221 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;252 #clock-cells = <0>;254 reg = <0x01c200d0 0x4>;274 reg = <0x01c02000 0x1000>;[all …]
101 #size-cells = <0>;103 cpu0: cpu@0 {106 reg = <0>;181 size = <0x6000000>;182 alloc-ranges = <0x40000000 0x10000000>;208 #clock-cells = <0>;215 #clock-cells = <0>;231 #clock-cells = <0>;238 #clock-cells = <0>;245 #clock-cells = <0>;[all …]
127 cpu@0 {181 reg = <0x40000000 0x80000000>;193 "Left DAC", "AIF1 Slot 0 Left",194 "Right DAC", "AIF1 Slot 0 Right";209 reg = <0x01c0c000 0x1000>;222 #size-cells = <0>;224 tcon0_in: port@0 {226 #size-cells = <0>;227 reg = <0>;229 tcon0_in_drc0: endpoint@0 {[all …]
56 #size-cells = <0>;58 cpu0: cpu@0 {61 reg = <0x0>;71 framebuffer@0 {97 #clock-cells = <0>;103 osc32k: clk@0 {104 #clock-cells = <0>;119 reg = <0x01c00000 0x30>;124 sram_a: sram@0 {126 reg = <0x00000000 0xc000>;[all …]
111 #size-cells = <0>;112 cpu0: cpu@0 {115 reg = <0x0>;167 #clock-cells = <0>;174 #clock-cells = <0>;195 reg = <0x01c00000 0x30>;200 sram_a: sram@0 {202 reg = <0x00000000 0xc000>;205 ranges = <0 0x00000000 0xc000>;209 reg = <0x8000 0x4000>;[all …]
65 framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;161 reg = <0x40000000 0x80000000>;184 #clock-cells = <0>;190 osc32k: clk@0 {191 #clock-cells = <0>;207 #clock-cells = <0>;214 #clock-cells = <0>;[all …]
65 simplefb_hdmi: framebuffer@0 {100 #size-cells = <0>;102 cpu0: cpu@0 {105 reg = <0>;170 reg = <0x40000000 0x80000000>;187 #clock-cells = <0>;192 osc32k: clk@0 {193 #clock-cells = <0>;209 #clock-cells = <0>;216 #clock-cells = <0>;[all …]