Home
last modified time | relevance | path

Searched +full:0 +full:x01200000 (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/cache/
H A Dqcom,llcc.yaml162 reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
163 <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
164 <0 0x01300000 0 0x50000>;
/openbmc/u-boot/board/freescale/m547xevb/
H A DREADME77 CONFIG_SYS_UART_PORT -- define UART port number, start with 0, 1 and 2
135 Flash: 0xFF800000-0xFFFFFFFF (8MB)
136 DDR: 0x00000000-0x3FFFFFFF (1024MB)
137 SRAM: 0xF2000000-0xF2000FFF (4KB)
138 PCI: 0x70000000-0x8FFFFFFF (512MB)
139 IP: 0xF0000000-0xFFFFFFFF (256MB)
179 ethaddr=00:e0:0c:bc:e5:60
180 eth1addr=00:e0:0c:bc:e5:61
200 memstart = 0x00000000
201 memsize = 0x04000000
[all …]
/openbmc/linux/arch/arm/probes/
H A Ddecode.h42 if (pcv & 0x1) { in bx_write_pc()
44 pcv &= ~0x1; in bx_write_pc()
47 pcv &= ~0x2; /* Avoid UNPREDICTABLE address allignment */ in bx_write_pc()
107 * if P (bit 24) == 0 or W (bit 21) == 1
109 #define is_writeback(insn) ((insn ^ 0x01000000) & 0x01200000)
189 * REGS(0, ANY, NOPC, 0, ANY)
197 * bits 3.. 0 any register allowed here
212 * DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
213 * REGS(ANY, ANY, NOPC, 0, ANY)),
242 REG_TYPE_NONE = 0, /* Not a register, ignore */
[all …]
/openbmc/qemu/tests/tcg/xtensa/
H A Dtest_mmu.S6 #define BASE 0x20000000
7 #define TLB_BASE 0x80000000
23 clean_tlb_way 0, 0x00001000, 4
24 clean_tlb_way 1, 0x00001000, 4
25 clean_tlb_way 2, 0x00001000, 4
26 clean_tlb_way 3, 0x00001000, 4
27 clean_tlb_way 4, 0x00100000, 4
28 movi a2, 0x00000007
30 movi a2, 0x00000008
32 movi a2, 0x00000009
[all …]
/openbmc/linux/sound/soc/sh/rcar/
H A Dsrc.c50 for ((i) = 0; \
68 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_activation()
75 rsnd_mod_write(mod, SRC_SWRSR, 0); in rsnd_src_halt()
97 return 0; in rsnd_src_convert_rate()
119 unsigned int rate = 0; in rsnd_src_get_rate()
147 0x01800000, /* 6 - 1/6 */
148 0x01000000, /* 6 - 1/4 */
149 0x00c00000, /* 6 - 1/3 */
150 0x00800000, /* 6 - 1/2 */
151 0x00600000, /* 6 - 2/3 */
[all …]
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c92 /* Bit[15] is RES1, Bit[13] and Bits[11:0] are RES0. */ in aa32_max_features()
93 t = 0x00008000; in aa32_max_features()
102 t = 0; in aa32_max_features()
106 t = FIELD_DP32(t, DBGDEVID, VECTORCATCH, 0); in aa32_max_features()
109 t = FIELD_DP32(t, DBGDEVID, AUXREGS, 0); in aa32_max_features()
110 t = FIELD_DP32(t, DBGDEVID, CIDMASK, 0); in aa32_max_features()
114 t = 0; in aa32_max_features()
134 cpu->midr = 0x41069265; in arm926_initfn()
135 cpu->reset_fpsid = 0x41011090; in arm926_initfn()
136 cpu->ctr = 0x1dd20d2; in arm926_initfn()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-a83t.dtsi61 #size-cells = <0>;
63 cpu0: cpu@0 {
71 reg = <0>;
109 reg = <0x100>;
118 reg = <0x101>;
127 reg = <0x102>;
136 reg = <0x103>;
155 #clock-cells = <0>;
168 #clock-cells = <0>;
175 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsun8i-a83t.dtsi62 #size-cells = <0>;
64 cpu0: cpu@0 {
71 reg = <0>;
115 reg = <0x100>;
126 reg = <0x101>;
137 reg = <0x102>;
148 reg = <0x103>;
168 #clock-cells = <0>;
181 #clock-cells = <0>;
188 #clock-cells = <0>;
[all …]
H A Dsun8i-r40.dtsi64 #clock-cells = <0>;
72 #clock-cells = <0>;
82 #size-cells = <0>;
84 cpu0: cpu@0 {
87 reg = <0>;
130 polling-delay-passive = <0>;
131 polling-delay = <0>;
132 thermal-sensors = <&ths 0>;
143 hysteresis = <0>;
161 polling-delay-passive = <0>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-apq8064.dtsi25 reg = <0x80000000 0x200000>;
30 reg = <0x8f000000 0x700000>;
37 #size-cells = <0>;
39 CPU0: cpu@0 {
43 reg = <0>;
100 memory@0 {
102 reg = <0x0 0x0>;
111 coefficients = <1199 0>;
132 coefficients = <1132 0>;
153 coefficients = <1199 0>;
[all …]
/openbmc/qemu/tcg/riscv/
H A Dtcg-target.c.inc105 tcg_debug_assert(slot >= 0 && slot <= 1);
109 #define TCG_CT_CONST_ZERO 0x100
110 #define TCG_CT_CONST_S12 0x200
111 #define TCG_CT_CONST_N12 0x400
112 #define TCG_CT_CONST_M12 0x800
113 #define TCG_CT_CONST_J12 0x1000
114 #define TCG_CT_CONST_S5 0x2000
115 #define TCG_CT_CONST_CMP_VI 0x4000
117 #define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32)
119 #define ALL_DVECTOR_REG_GROUPS 0x5555555500000000
[all …]
/openbmc/linux/drivers/ptp/
H A Dptp_ocp.c27 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
28 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30 #define PCI_VENDOR_ID_CELESTICA 0x18d4
31 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33 #define PCI_VENDOR_ID_OROLIA 0x1ad7
34 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
65 #define OCP_CTRL_ENABLE BIT(0)
73 #define OCP_STATUS_IN_SYNC BIT(0)
76 #define OCP_SELECT_CLK_NONE 0
77 #define OCP_SELECT_CLK_REG 0xfe
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdm845.dtsi77 #clock-cells = <0>;
84 #clock-cells = <0>;
91 #size-cells = <0>;
93 CPU0: cpu@0 {
96 reg = <0x0 0x0>;
97 clocks = <&cpufreq_hw 0>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
125 reg = <0x0 0x100>;
126 clocks = <&cpufreq_hw 0>;
130 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]