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/openbmc/linux/Documentation/devicetree/bindings/power/supply/
H A Dbq24735.yaml40 The POR value is 0x0000h. This number is in mA (e.g. 8192).
41 See spec for more information about the ChargeCurrent (0x14h) register.
48 The POR value is 0x0000h. This number is in mV (e.g. 19200).
49 See spec for more information about the ChargeVoltage (0x15h) register.
56 The POR value is 0x1000h. This number is in mA (e.g. 8064).
57 See the spec for more information about the InputCurrent (0x3fh) register.
82 #size-cells = <0>;
86 reg = <0x9>;
87 ti,ac-detect-gpios = <&gpio 72 0x1>;
/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h14 /* 0x0000h ~ 0x00FFh System Configuration */
17 #define REG_RSV_CTRL_8723B 0x001C /* 3 Byte */
18 #define REG_BT_WIFI_ANTENNA_SWITCH_8723B 0x0038
19 #define REG_HSISR_8723B 0x005c
20 #define REG_PAD_CTRL1_8723B 0x0064
21 #define REG_AFE_CTRL_4_8723B 0x0078
22 #define REG_HMEBOX_DBG_0_8723B 0x0088
23 #define REG_HMEBOX_DBG_1_8723B 0x008A
24 #define REG_HMEBOX_DBG_2_8723B 0x008C
25 #define REG_HMEBOX_DBG_3_8723B 0x008E
[all …]
H A Dhal_com_reg.h16 #define TXPKT_BUF_SELECT 0x69
17 #define RXPKT_BUF_SELECT 0xA5
18 #define DISABLE_TRXPKT_BUF_ACCESS 0x0
26 /* 0x0000h ~ 0x00FFh System Configuration */
29 #define REG_SYS_ISO_CTRL 0x0000
30 #define REG_SYS_FUNC_EN 0x0002
31 #define REG_APS_FSMCO 0x0004
32 #define REG_SYS_CLKR 0x0008
33 #define REG_9346CR 0x000A
34 #define REG_SYS_EEPROM_CTRL 0x000A
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dreg.h8 /* 0x0000h ~ 0x00FFh System Configuration */
10 #define REG_SYS_ISO_CTRL 0x0000
11 #define REG_SYS_FUNC_EN 0x0002
12 #define REG_APS_FSMCO 0x0004
13 #define REG_SYS_CLKR 0x0008
14 #define REG_9346CR 0x000A
15 #define REG_EE_VPD 0x000C
16 #define REG_AFE_MISC 0x0010
17 #define REG_SPS0_CTRL 0x0011
18 #define REG_POWER_OFF_IN_PROCESS 0x0017
[all …]
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h28 /* 0x0000h ~ 0x00FFh System Configuration */
31 #define REG_SYS_ISO_CTRL_8723B 0x0000 /* 2 Byte */
32 #define REG_SYS_FUNC_EN_8723B 0x0002 /* 2 Byte */
33 #define REG_APS_FSMCO_8723B 0x0004 /* 4 Byte */
34 #define REG_SYS_CLKR_8723B 0x0008 /* 2 Byte */
35 #define REG_9346CR_8723B 0x000A /* 2 Byte */
36 #define REG_EE_VPD_8723B 0x000C /* 2 Byte */
37 #define REG_AFE_MISC_8723B 0x0010 /* 1 Byte */
38 #define REG_SPS0_CTRL_8723B 0x0011 /* 7 Byte */
39 #define REG_SPS_OCP_CFG_8723B 0x0018 /* 4 Byte */
[all …]
H A Drtl8723b_hal_init.c17 u8 tmp, count = 0; in _FWDownloadEnable()
22 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04); in _FWDownloadEnable()
25 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); in _FWDownloadEnable()
29 if (tmp & 0x01) in _FWDownloadEnable()
31 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); in _FWDownloadEnable()
37 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); in _FWDownloadEnable()
41 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe); in _FWDownloadEnable()
52 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; in _BlockWrite()
53 u32 remainSize_p1 = 0, remainSize_p2 = 0; in _BlockWrite()
55 u32 i = 0, offset = 0; in _BlockWrite()
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