| /openbmc/linux/drivers/net/wireless/realtek/rtw89/ |
| H A D | rtw8852c_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
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| H A D | rtw8852a_rfk_table.c | 8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
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| H A D | rtw8851b_rfk_table.c | 8 RTW89_DECL_RFK_WM(0xc210, 0x003fc000, 0x80),
9 RTW89_DECL_RFK_WM(0xc224, 0x003fc000, 0x80),
10 RTW89_DECL_RFK_WM(0xc0f8, 0x30000000, 0x3),
11 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
12 RTW89_DECL_RFK_WM(0x030c, 0x1f000000, 0x1f),
13 RTW89_DECL_RFK_WM(0x032c, 0xc0000000, 0x0),
14 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x0),
15 RTW89_DECL_RFK_WM(0x032c, BIT(22), 0x1),
16 RTW89_DECL_RFK_WM(0x032c, BIT(16), 0x0),
17 RTW89_DECL_RFK_WM(0x032c, BIT(20), 0x1),
[all …]
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| /openbmc/u-boot/arch/m68k/include/asm/coldfire/ |
| H A D | lcd.h | 14 u32 ssar; /* 0x00 Screen Start Address Register */
15 u32 sr; /* 0x04 LCD Size Register */
16 u32 vpw; /* 0x08 Virtual Page Width Register */
17 u32 cpr; /* 0x0C Cursor Position Register */
18 u32 cwhb; /* 0x10 Cursor Width Height and Blink Register */
19 u32 ccmr; /* 0x14 Color Cursor Mapping Register */
20 u32 pcr; /* 0x18 Panel Configuration Register */
21 u32 hcr; /* 0x1C Horizontal Configuration Register */
22 u32 vcr; /* 0x20 Vertical Configuration Register */
23 u32 por; /* 0x24 Panning Offset Register */
[all …]
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| /openbmc/linux/drivers/net/wireless/ath/ath9k/ |
| H A D | reg.h | 22 #define AR_CR 0x0008
23 #define AR_CR_RXE(_ah) (AR_SREV_9300_20_OR_LATER(_ah) ? 0x0000000c : 0x00000004)
24 #define AR_CR_RXD 0x00000020
25 #define AR_CR_SWI 0x00000040
27 #define AR_RXDP 0x000C
29 #define AR_CFG 0x0014
30 #define AR_CFG_SWTD 0x00000001
31 #define AR_CFG_SWTB 0x00000002
32 #define AR_CFG_SWRD 0x00000004
33 #define AR_CFG_SWRB 0x00000008
[all …]
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| /openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/ |
| H A D | ps7_init_gpl.c | 9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
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| /openbmc/u-boot/arch/arm/mach-socfpga/include/mach/ |
| H A D | clock_manager_arria10.h | 103 #define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
104 #define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
109 #define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
110 #define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
111 #define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
112 #define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
113 #define CLKMGR_PERPLL_VCO0_RESET 0x00010053
114 #define CLKMGR_PERPLL_VCO1_RESET 0x00010001
115 #define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
116 #define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
[all …]
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| H A D | sdram_gen5.h | 22 #define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
29 u32 dram_timing4; /* 0x10 */
34 u32 dram_addrw; /* 0x2c */
35 u32 dram_if_width; /* 0x30 */
39 u32 sbe_count; /* 0x40 */
43 u32 drop_addr; /* 0x50 */
47 u32 ctrl_width; /* 0x60 */
51 u32 rfifo_cmap; /* 0x70 */
55 u32 fpgaport_rst; /* 0x80 */
59 u32 prot_rule_addr; /* 0x90 */
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_11_0_0_default.h | 28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]
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| H A D | gc_10_1_0_default.h | 26 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
27 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
28 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
29 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
32 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
33 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
34 #define mmSDMA0_CHICKEN_BITS_DEFAULT 0x01af0107
35 #define mmSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000044
[all …]
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| H A D | gc_10_3_0_default.h | 27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
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| /openbmc/u-boot/include/ |
| H A D | lcdvideo.h | 11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
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| /openbmc/linux/drivers/net/wireless/ath/ath5k/ |
| H A D | reg.h | 46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
52 #define AR5K_CR 0x0008 /* Register Address */
53 #define AR5K_CR_TXE0 0x00000001 /* TX Enable for queue 0 on 5210 */
54 #define AR5K_CR_TXE1 0x00000002 /* TX Enable for queue 1 on 5210 */
55 #define AR5K_CR_RXE 0x00000004 /* RX Enable */
56 #define AR5K_CR_TXD0 0x00000008 /* TX Disable for queue 0 on 5210 */
57 #define AR5K_CR_TXD1 0x00000010 /* TX Disable for queue 1 on 5210 */
58 #define AR5K_CR_RXD 0x00000020 /* RX Disable */
59 #define AR5K_CR_SWI 0x00000040 /* Software Interrupt */
[all …]
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| /openbmc/u-boot/board/aristainetos/ |
| H A D | clocks.cfg | 17 DATA 4, CCM_CCGR0, 0x00c03f3f
18 DATA 4, CCM_CCGR1, 0x0030fcff
19 DATA 4, CCM_CCGR2, 0x0fffcfc0
20 DATA 4, CCM_CCGR3, 0x3ff0300f
21 DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */
22 DATA 4, CCM_CCGR5, 0x0f0000c3
23 DATA 4, CCM_CCGR6, 0x000003ff
|
| /openbmc/u-boot/board/advantech/dms-ba16/ |
| H A D | clocks.cfg | 2 DATA 4, CCM_CCGR0, 0x00C03F3F
3 DATA 4, CCM_CCGR1, 0x0030FC03
4 DATA 4, CCM_CCGR2, 0x0FFFC000
5 DATA 4, CCM_CCGR3, 0x3FF00000
6 DATA 4, CCM_CCGR4, 0x00FFF300
7 DATA 4, CCM_CCGR5, 0x0F0000C3
8 DATA 4, CCM_CCGR6, 0x000003FF
11 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
12 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
13 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
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| H A D | sdma0_4_0_default.h | 26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
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| /openbmc/u-boot/board/tqc/tqma6/ |
| H A D | clocks.cfg | 11 DATA 4, CCM_CCGR0, 0x00C03F3F
12 DATA 4, CCM_CCGR1, 0x0030FC03
13 DATA 4, CCM_CCGR2, 0x0FFFC000
14 DATA 4, CCM_CCGR3, 0x3FF00000
15 DATA 4, CCM_CCGR4, 0x00FFF300
16 DATA 4, CCM_CCGR5, 0x0F0000C3
17 DATA 4, CCM_CCGR6, 0x000003FF
20 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
21 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
22 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
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| /openbmc/linux/arch/riscv/include/asm/ |
| H A D | kvm_aia_aplic.h | 14 #define APLIC_DOMAINCFG 0x0000
15 #define APLIC_DOMAINCFG_RDONLY 0x80000000
18 #define APLIC_DOMAINCFG_BE BIT(0)
20 #define APLIC_SOURCECFG_BASE 0x0004
22 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
23 #define APLIC_SOURCECFG_SM_MASK 0x00000007
24 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
25 #define APLIC_SOURCECFG_SM_DETACH 0x1
26 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
27 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
[all …]
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| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/ |
| H A D | sdma1_4_0_default.h | 26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | clocks.cfg | 17 DATA 4, CCM_CCGR0, 0x00C03F3F
18 DATA 4, CCM_CCGR1, 0x0030FC03
19 DATA 4, CCM_CCGR2, 0x0FFFC000
20 DATA 4, CCM_CCGR3, 0x3FF00000
21 DATA 4, CCM_CCGR4, 0x00FFF300
22 DATA 4, CCM_CCGR5, 0x0F0000C3
23 DATA 4, CCM_CCGR6, 0x000003FF
26 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
27 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
28 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
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| /openbmc/u-boot/board/toradex/apalis_imx6/ |
| H A D | clocks.cfg | 18 DATA 4, CCM_CCGR0, 0x00C03F3F
19 DATA 4, CCM_CCGR1, 0x0030FC03
20 DATA 4, CCM_CCGR2, 0x0FFFC000
21 DATA 4, CCM_CCGR3, 0x3FF00000
22 DATA 4, CCM_CCGR4, 0x00FFF300
23 DATA 4, CCM_CCGR5, 0x0F0000C3
24 DATA 4, CCM_CCGR6, 0x000003FF
27 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
29 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
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| /openbmc/u-boot/board/toradex/colibri_imx6/ |
| H A D | clocks.cfg | 18 DATA 4, CCM_CCGR0, 0x00C03F3F
19 DATA 4, CCM_CCGR1, 0x0030FC03
20 DATA 4, CCM_CCGR2, 0x0FFFC000
21 DATA 4, CCM_CCGR3, 0x3FF00000
22 DATA 4, CCM_CCGR4, 0x00FFF300
23 DATA 4, CCM_CCGR5, 0x0F0000C3
24 DATA 4, CCM_CCGR6, 0x000003FF
27 DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
28 /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
29 DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
[all …]
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| /openbmc/u-boot/board/freescale/mx6qarm2/ |
| H A D | imximage.cfg | 34 DATA 4 0x020C4018 0x60324
36 DATA 4 0x020E05a8 0x00003038
37 DATA 4 0x020E05b0 0x00003038
38 DATA 4 0x020E0524 0x00003038
39 DATA 4 0x020E051c 0x00003038
41 DATA 4 0x020E0518 0x00003038
42 DATA 4 0x020E050c 0x00003038
43 DATA 4 0x020E05b8 0x00003038
44 DATA 4 0x020E05c0 0x00003038
46 DATA 4 0x020E05ac 0x00000038
[all …]
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| /openbmc/u-boot/board/barco/platinum/ |
| H A D | platinum.h | 68 writel(0x00C03F3F, &ccm->CCGR0); in ccgr_init()
69 writel(0x0030FC03, &ccm->CCGR1); in ccgr_init()
70 writel(0x0FFFC000, &ccm->CCGR2); in ccgr_init()
71 writel(0x3FF00000, &ccm->CCGR3); in ccgr_init()
72 writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ in ccgr_init()
73 writel(0x0F0000C3, &ccm->CCGR5); in ccgr_init()
74 writel(0x000003FF, &ccm->CCGR6); in ccgr_init()
|