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/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_gen5.h135 #define CLKMGR_CTRL_SAFEMODE BIT(0)
136 #define CLKMGR_CTRL_SAFEMODE_OFFSET 0
146 #define CLKMGR_BYPASS_MAINPLL BIT(0)
147 #define CLKMGR_BYPASS_MAINPLL_OFFSET 0
156 #define CLKMGR_STAT_BUSY BIT(0)
159 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN BIT(0)
160 #define CLKMGR_MAINPLLGRP_VCO_BGPWRDN_OFFSET 0
162 #define CLKMGR_MAINPLLGRP_VCO_DENOM_MASK 0x003f0000
166 #define CLKMGR_MAINPLLGRP_VCO_NUMER_MASK 0x0000fff8
167 #define CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK 0x01000000
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
H A Drtw8852a_table.c10 {0xF0FF0001, 0x00000000},
11 {0xF03300FF, 0x00000001},
12 {0xF03500FF, 0x00000002},
13 {0xF03200FF, 0x00000003},
14 {0xF03400FF, 0x00000004},
15 {0xF03600FF, 0x00000005},
16 {0x704, 0x601E0100},
17 {0x714, 0x00000000},
18 {0x718, 0x13332333},
19 {0x714, 0x00010000},
[all …]
H A Drtw8852c_rfk_table.c8 RTW89_DECL_RFK_WM(0xc004, BIT(17), 0x1),
9 RTW89_DECL_RFK_WM(0xc024, BIT(17), 0x1),
10 RTW89_DECL_RFK_WM(0xc104, BIT(17), 0x1),
11 RTW89_DECL_RFK_WM(0xc124, BIT(17), 0x1),
17 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x0),
18 RTW89_DECL_RFK_WM(0xc000, BIT(17), 0x1),
24 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x0),
25 RTW89_DECL_RFK_WM(0xc100, BIT(17), 0x1),
31 RTW89_DECL_RFK_WM(0x12b8, BIT(30), 0x1),
32 RTW89_DECL_RFK_WM(0x030c, BIT(28), 0x1),
[all …]
H A Drtw8852b_rfk_table.c8 RTW89_DECL_RFK_WM(0xC0D4, 0xffffffff, 0x4486888c),
9 RTW89_DECL_RFK_WM(0xC0D8, 0xffffffff, 0xc6ba10e0),
10 RTW89_DECL_RFK_WM(0xc0dc, 0xffffffff, 0x30c52868),
11 RTW89_DECL_RFK_WM(0xc0e0, 0xffffffff, 0x05008128),
12 RTW89_DECL_RFK_WM(0xc0e4, 0xffffffff, 0x0000272b),
13 RTW89_DECL_RFK_WM(0xC1D4, 0xffffffff, 0x4486888c),
14 RTW89_DECL_RFK_WM(0xC1D8, 0xffffffff, 0xc6ba10e0),
15 RTW89_DECL_RFK_WM(0xc1dc, 0xffffffff, 0x30c52868),
16 RTW89_DECL_RFK_WM(0xc1e0, 0xffffffff, 0x05008128),
17 RTW89_DECL_RFK_WM(0xc1e4, 0xffffffff, 0x0000272b),
[all …]
/openbmc/linux/include/net/
H A Dieee80211_radiotap.h29 * @it_version: radiotap version, always 0
58 /* version is always 0 */
59 #define PKTHDR_RADIOTAP_VERSION 0
63 IEEE80211_RADIOTAP_TSFT = 0,
102 IEEE80211_RADIOTAP_F_CFP = 0x01,
103 IEEE80211_RADIOTAP_F_SHORTPRE = 0x02,
104 IEEE80211_RADIOTAP_F_WEP = 0x04,
105 IEEE80211_RADIOTAP_F_FRAG = 0x08,
106 IEEE80211_RADIOTAP_F_FCS = 0x10,
107 IEEE80211_RADIOTAP_F_DATAPAD = 0x20,
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h16 #define FSL_DMA_MR_CS 0x00000001 /* Channel start */
17 #define FSL_DMA_MR_CC 0x00000002 /* Channel continue */
18 #define FSL_DMA_MR_CTM 0x00000004 /* Channel xfer mode */
19 #define FSL_DMA_MR_CTM_DIRECT 0x00000004 /* Direct channel xfer mode */
20 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
21 #define FSL_DMA_MR_PRC_MASK 0x00000c00 /* PCI read command */
22 #define FSL_DMA_MR_SAHE 0x00001000 /* Source addr hold enable */
23 #define FSL_DMA_MR_DAHE 0x00002000 /* Dest addr hold enable */
24 #define FSL_DMA_MR_SAHTS_MASK 0x0000c000 /* Source addr hold xfer size */
25 #define FSL_DMA_MR_DAHTS_MASK 0x00030000 /* Dest addr hold xfer size */
[all …]
/openbmc/qemu/tests/tcg/tricore/asm/
H A Dtest_dvstep.S6 TEST_E_ED(dvstep, 1, 0x000001ff, 0xfffe5cff, 0x00000001, 0xfffffe5c, 0x0)
7 TEST_E_ED(dvstep, 2, 0x00000000, 0x000000ff, 0x00000000, 0x00000000, 0x0)
8 TEST_E_ED(dvstep, 3, 0x0000f000, 0x000000fd, 0x010000f0, 0x00000000, 0x0)
9 TEST_E_ED(dvstep, 4, 0xfffff000, 0x00000000, 0x7ffffff0, 0x00000000, 0x0)
10 TEST_E_ED(dvstep.u, 5, 0xffffff00, 0x100008ff, 0xffffffff, 0x00100008, 0x0)
11 TEST_E_ED(dvstep.u, 6, 0x00000100, 0x00000000, 0x08000001, 0x00000000, \
12 0xffffff2d)
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dgk110.c38 { 0x40415c, 1, 0x04, 0x00000000 },
39 { 0x404170, 1, 0x04, 0x00000000 },
40 { 0x4041b4, 1, 0x04, 0x00000000 },
46 { 0x405844, 1, 0x04, 0x00ffffff },
47 { 0x405850, 1, 0x04, 0x00000000 },
48 { 0x405900, 1, 0x04, 0x0000ff00 },
49 { 0x405908, 1, 0x04, 0x00000000 },
50 { 0x405928, 2, 0x04, 0x00000000 },
56 { 0x407010, 1, 0x04, 0x00000000 },
57 { 0x407040, 1, 0x04, 0x80440424 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_default.h28 #define regSDMA0_DEC_START_DEFAULT 0x00000000
29 #define regSDMA0_F32_MISC_CNTL_DEFAULT 0x00000000
30 #define regSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
31 #define regSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
32 #define regSDMA0_POWER_CNTL_DEFAULT 0x00000000
33 #define regSDMA0_CNTL_DEFAULT 0x00002440
34 #define regSDMA0_CHICKEN_BITS_DEFAULT 0x0107d186
35 #define regSDMA0_GB_ADDR_CONFIG_DEFAULT 0x00000545
36 #define regSDMA0_GB_ADDR_CONFIG_READ_DEFAULT 0x00000545
37 #define regSDMA0_RB_RPTR_FETCH_DEFAULT 0x00000000
[all …]
/openbmc/linux/sound/drivers/vx/
H A Dvx_uer.c27 rmh.Cmd[0] |= CMD_MODIFY_CLOCK_S_BIT; in vx_modify_board_clock()
39 rmh.Cmd[0] |= 1 << 0; /* reference: AUDIO 0 */ in vx_modify_board_inputs()
46 * returns 0 or 1.
56 val = (vx_inb(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
60 val = (vx_inl(chip, RUER) >> 7) & 0x01; in vx_read_one_cbit()
69 * @val: bit value, 0 or 1
73 val = !!val; /* 0 or 1 */ in vx_write_one_cbit()
76 vx_outb(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
79 vx_outl(chip, CSUER, 0); /* write */ in vx_write_one_cbit()
89 * returns the frequency of UER, or 0 if not sync,
[all …]
H A Dvx_cmd.h86 #define CODE_OP_PIPE_TIME 0x004e0000
87 #define CODE_OP_START_STREAM 0x00800000
88 #define CODE_OP_PAUSE_STREAM 0x00810000
89 #define CODE_OP_OUT_STREAM_LEVEL 0x00820000
90 #define CODE_OP_UPDATE_R_BUFFERS 0x00840000
91 #define CODE_OP_OUT_STREAM1_LEVEL_CURVE 0x00850000
92 #define CODE_OP_OUT_STREAM2_LEVEL_CURVE 0x00930000
93 #define CODE_OP_OUT_STREAM_FORMAT 0x00860000
94 #define CODE_OP_STREAM_TIME 0x008f0000
95 #define CODE_OP_OUT_STREAM_EXTRAPARAMETER 0x00910000
[all …]
/openbmc/qemu/tests/tcg/mips/include/
H A Dtest_inputs_32.h32 0xFFFFFFFF, /* 0 */
33 0x00000000,
34 0xAAAAAAAA,
35 0x55555555,
36 0xCCCCCCCC,
37 0x33333333,
38 0xE38E38E3,
39 0x1C71C71C,
40 0xF0F0F0F0, /* 8 */
41 0x0F0F0F0F,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/openbmc/linux/arch/arm/include/asm/
H A Dv7m.h5 #define V7M_SCS_ICTR IOMEM(0xe000e004)
6 #define V7M_SCS_ICTR_INTLINESNUM_MASK 0x0000000f
8 #define BASEADDR_V7M_SCB IOMEM(0xe000ed00)
10 #define V7M_SCB_CPUID 0x00
12 #define V7M_SCB_ICSR 0x04
16 #define V7M_SCB_ICSR_VECTACTIVE 0x000001ff
18 #define V7M_SCB_VTOR 0x08
20 #define V7M_SCB_AIRCR 0x0c
21 #define V7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
24 #define V7M_SCB_SCR 0x10
[all …]
/openbmc/linux/include/linux/mfd/
H A Dcs42l43-regs.h13 #define CS42L43_GEN_INT_STAT_1 0x000000C0
14 #define CS42L43_GEN_INT_MASK_1 0x000000C1
15 #define CS42L43_DEVID 0x00003000
16 #define CS42L43_REVID 0x00003004
17 #define CS42L43_RELID 0x0000300C
18 #define CS42L43_SFT_RESET 0x00003020
19 #define CS42L43_DRV_CTRL1 0x00006004
20 #define CS42L43_DRV_CTRL3 0x0000600C
21 #define CS42L43_DRV_CTRL4 0x00006010
22 #define CS42L43_DRV_CTRL_5 0x00006014
[all …]
/openbmc/u-boot/board/bitmain/antminer_s9/bitmain-antminer-s9/
H A Dps7_init_gpl.c9 EMIT_MASKWRITE(0xf8000008, 0x0000ffff, 0x0000df0d),
10 EMIT_MASKWRITE(0xf8000110, 0x003ffff0, 0x000fa220),
11 EMIT_MASKWRITE(0xf8000100, 0x0007f000, 0x00028000),
12 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000010),
13 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000001),
14 EMIT_MASKWRITE(0xf8000100, 0x00000001, 0x00000000),
15 EMIT_MASKPOLL(0xf800010c, 0x00000001),
16 EMIT_MASKWRITE(0xf8000100, 0x00000010, 0x00000000),
17 EMIT_MASKWRITE(0xf8000120, 0x1f003f30, 0x1f000200),
18 EMIT_MASKWRITE(0xf8000114, 0x003ffff0, 0x0012c220),
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt76x2/
H A Dinit.c86 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
88 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
92 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
94 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
98 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
101 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
104 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \ in mt76_write_mac_initvals()
107 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f)) in mt76_write_mac_initvals()
111 { MT_PBF_SYS_CTRL, 0x00080c00 }, in mt76_write_mac_initvals()
112 { MT_PBF_CFG, 0x1efebcff }, in mt76_write_mac_initvals()
[all …]
/openbmc/u-boot/drivers/usb/eth/
H A Dlan7x.h10 #define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
11 #define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
12 #define USB_VENDOR_REQUEST_GET_STATS 0xA2
16 #define TX_CMD_A_LEN_MASK 0x000FFFFF
20 #define RX_CMD_A_LEN_MASK 0x00003FFF
23 #define ID_REV 0x00
24 #define ID_REV_CHIP_ID_MASK 0xFFFF0000
25 #define ID_REV_CHIP_ID_7500 0x7500
26 #define ID_REV_CHIP_ID_7800 0x7800
27 #define ID_REV_CHIP_ID_7850 0x7850
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/
H A Dcl907d.h27 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004
28 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0
29 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000
30 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001
31 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014
32 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0
33 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000
34 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001
36 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000
37 #define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Drx.h14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
[all …]
/openbmc/linux/arch/mips/include/asm/mach-au1x00/
H A Dau1100_mmc.h52 #define SD0_BASE 0xB0600000
53 #define SD1_BASE 0xB0680000
59 #define SD_TXPORT (0x0000)
60 #define SD_RXPORT (0x0004)
61 #define SD_CONFIG (0x0008)
62 #define SD_ENABLE (0x000C)
63 #define SD_CONFIG2 (0x0010)
64 #define SD_BLKSIZE (0x0014)
65 #define SD_STATUS (0x0018)
66 #define SD_DEBUG (0x001C)
[all …]
/openbmc/linux/sound/pci/pcxhr/
H A Dpcxhr_core.h26 #define PCXHR_DSP_TIME_MASK 0x00ffffff
27 #define PCXHR_DSP_TIME_INVALID 0x10000000
47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */
51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */
52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */
54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */
55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */
56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */
57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */
58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */
[all …]
/openbmc/u-boot/tools/
H A Dvybridimage.c16 * NAND page 0 boot header
23 }; /* 0x00000000 - 0x000001ff */
24 uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */
25 uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */
26 uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */
42 uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; in vybridimage_sw_ecc()
43 uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; in vybridimage_sw_ecc()
44 uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; in vybridimage_sw_ecc()
45 uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; in vybridimage_sw_ecc()
46 uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; in vybridimage_sw_ecc()
[all …]
/openbmc/qemu/include/exec/
H A Dtranslation-block.h72 #define CF_COUNT_MASK 0x000001ff
73 #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */
74 #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */
75 #define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */
76 #define CF_MEMI_ONLY 0x00001000 /* Only instrument memory ops */
77 #define CF_USE_ICOUNT 0x00002000
78 #define CF_INVALID 0x00004000 /* TB is stale. Set with @jmp_lock held */
79 #define CF_PARALLEL 0x00008000 /* Generate code for a parallel context */
80 #define CF_NOIRQ 0x00010000 /* Generate an uninterruptible TB */
81 #define CF_PCREL 0x00020000 /* Opcodes in TB are PC-relative */
[all …]

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