/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/oss/ |
H A D | oss_1_0_sh_mask.h | 26 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000L 27 #define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x0000001c 28 #define CC_DRM_ID_STRAPS__DEVICE_ID_MASK 0x000ffff0L 29 #define CC_DRM_ID_STRAPS__DEVICE_ID__SHIFT 0x00000004 30 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID_MASK 0x00f00000L 31 #define CC_DRM_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x00000014 32 #define CC_DRM_ID_STRAPS__MINOR_REV_ID_MASK 0x0f000000L 33 #define CC_DRM_ID_STRAPS__MINOR_REV_ID__SHIFT 0x00000018 34 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK 0x00ff0000L 35 #define CC_SYS_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT 0x00000010 [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | rk3399-sdram-ddr3-1866.dtsi | 8 0x1 9 0xa 10 0x3 11 0x2 12 0x1 13 0x0 14 0xf 15 0xf 17 0x80181219 18 0x17050a03 [all …]
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H A D | rk3399-sdram-ddr3-1333.dtsi | 8 0x1 9 0xa 10 0x3 11 0x2 12 0x1 13 0x0 14 0xf 15 0xf 17 0x80120e12 18 0x11030802 [all …]
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H A D | rk3399-sdram-ddr3-1600.dtsi | 8 0x1 9 0xa 10 0x3 11 0x2 12 0x1 13 0x0 14 0xf 15 0xf 17 0x80151015 18 0x14040902 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/ |
H A D | gfx_6_0_sh_mask.h | 26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL 27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000 28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L 29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015 30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L 31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018 32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L 33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010 34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L 35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/ |
H A D | bif_3_0_sh_mask.h | 26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L 27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007 28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L 29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001 30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L 31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000 32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L 33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005 34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L 35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002 [all …]
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/openbmc/linux/drivers/net/wireless/ath/ath5k/ |
H A D | initvals.c | 32 * @ini_mode: 0 to write 1 to read (and clear) 39 AR5K_INI_WRITE = 0, /* Default */ 57 { AR5K_NOQCU_TXDP0, 0 }, 58 { AR5K_NOQCU_TXDP1, 0 }, 59 { AR5K_RXDP, 0 }, 60 { AR5K_CR, 0 }, 61 { AR5K_ISR, 0, AR5K_INI_READ }, 62 { AR5K_IMR, 0 }, 64 { AR5K_BSR, 0, AR5K_INI_READ }, 70 { AR5K_RPGTO, 0 }, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/ |
H A D | gmc_6_0_sh_mask.h | 26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L 27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008 28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L 29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010 30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L 31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000 32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L 33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002 34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L 35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001 [all …]
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/openbmc/linux/sound/soc/qcom/qdsp6/ |
H A D | q6dsp-errno.h | 8 #define ADSP_EOK 0x00000000 10 #define ADSP_EFAILED 0x00000001 12 #define ADSP_EBADPARAM 0x00000002 14 #define ADSP_EUNSUPPORTED 0x00000003 16 #define ADSP_EVERSION 0x00000004 18 #define ADSP_EUNEXPECTED 0x00000005 20 #define ADSP_EPANIC 0x00000006 22 #define ADSP_ENORESOURCE 0x00000007 24 #define ADSP_EHANDLE 0x00000008 26 #define ADSP_EALREADY 0x00000009 [all …]
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/openbmc/u-boot/board/warp7/ |
H A D | imximage.cfg | 33 DATA 4 0x30340004 0x4F400005 35 DATA 4 0x30391000 0x00000002 36 DATA 4 0x307a0000 0x03040008 37 DATA 4 0x307a0064 0x00200038 38 DATA 4 0x307a0490 0x00000001 39 DATA 4 0x307a00d0 0x00350001 40 DATA 4 0x307a00dc 0x00c3000a 41 DATA 4 0x307a00e0 0x00010000 42 DATA 4 0x307a00e4 0x00110006 43 DATA 4 0x307a00f4 0x0000033f [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/ |
H A D | vce_1_0_sh_mask.h | 26 #define VCE_LMI_CACHE_CTRL__VCPU_EN_MASK 0x00000001L 27 #define VCE_LMI_CACHE_CTRL__VCPU_EN__SHIFT 0x00000000 28 #define VCE_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 29 #define VCE_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x00000008 30 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 31 #define VCE_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x00000015 32 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP_MASK 0x00003ffcL 33 #define VCE_LMI_SWAP_CNTL1__RD_MC_CID_SWAP__SHIFT 0x00000002 34 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP_MASK 0x00000003L 35 #define VCE_LMI_SWAP_CNTL1__VCPU_R_MC_SWAP__SHIFT 0x00000000 [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra30-asus-nexus7-tilapia-memory-timings.dtsi | 13 emc-timings-0 { 17 nvidia,emc-auto-cal-interval = <0x001fffff>; 18 nvidia,emc-mode-1 = <0x80100002>; 19 nvidia,emc-mode-2 = <0x80200018>; 20 nvidia,emc-mode-reset = <0x80000b71>; 21 nvidia,emc-zcal-cnt-long = <0x00000040>; 25 0x0000001f /* EMC_RC */ 26 0x00000069 /* EMC_RFC */ 27 0x00000017 /* EMC_RAS */ 28 0x00000007 /* EMC_RP */ [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/ |
H A D | dce_6_0_sh_mask.h | 26 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA_MASK 0xffffffffL 27 #define ABM_TEST_DEBUG_DATA__ABM_TEST_DEBUG_DATA__SHIFT 0x00000000 28 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX_MASK 0x000000ffL 29 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_INDEX__SHIFT 0x00000000 30 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN_MASK 0x00000100L 31 #define ABM_TEST_DEBUG_INDEX__ABM_TEST_DEBUG_WRITE_EN__SHIFT 0x00000008 32 #define AFMT_60958_0__AFMT_60958_CS_A_MASK 0x00000001L 33 #define AFMT_60958_0__AFMT_60958_CS_A__SHIFT 0x00000000 34 #define AFMT_60958_0__AFMT_60958_CS_B_MASK 0x00000002L 35 #define AFMT_60958_0__AFMT_60958_CS_B__SHIFT 0x00000001 [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/ |
H A D | vega10_enum.h | 51 GDS_PERF_SEL_DS_ADDR_CONFL = 0, 184 NO_FORCE_REQUEST = 0x00000000, 185 FORCE_LIGHT_SLEEP_REQUEST = 0x00000001, 186 FORCE_DEEP_SLEEP_REQUEST = 0x00000002, 187 FORCE_SHUT_DOWN_REQUEST = 0x00000003, 195 NO_FORCE_REQ = 0x00000000, 196 FORCE_LIGHT_SLEEP_REQ = 0x00000001, 204 ENABLE_MEM_PWR_CTRL = 0x00000000, 205 DISABLE_MEM_PWR_CTRL = 0x00000001, 213 DYNAMIC_SHUT_DOWN_ENABLE = 0x00000000, [all …]
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/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_4_0_sh_mask.h | 26 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN_MASK 0x00000001L 27 #define UVD_CGC_CTRL2__DYN_OCLK_RAMP_EN__SHIFT 0x00000000 28 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN_MASK 0x00000002L 29 #define UVD_CGC_CTRL2__DYN_RCLK_RAMP_EN__SHIFT 0x00000001 30 #define UVD_CGC_CTRL2__GATER_DIV_ID_MASK 0x0000001cL 31 #define UVD_CGC_CTRL2__GATER_DIV_ID__SHIFT 0x00000002 32 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003cL 33 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x00000002 34 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007c0L 35 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x00000006 [all …]
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/openbmc/linux/sound/parisc/ |
H A D | harmony.h | 60 #define MAX_MIDI_DEVICES 0 75 #define HARMONY_ID 0x000 76 #define HARMONY_RESET 0x004 77 #define HARMONY_CNTL 0x008 78 #define HARMONY_GAINCTL 0x00c 79 #define HARMONY_PNXTADD 0x010 80 #define HARMONY_PCURADD 0x014 81 #define HARMONY_RNXTADD 0x018 82 #define HARMONY_RCURADD 0x01c 83 #define HARMONY_DSTATUS 0x020 [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | btc_dpm.c | 38 #define MC_CG_ARB_FREQ_F0 0x0a 39 #define MC_CG_ARB_FREQ_F1 0x0b 40 #define MC_CG_ARB_FREQ_F2 0x0c 41 #define MC_CG_ARB_FREQ_F3 0x0d 43 #define MC_CG_SEQ_DRAMCONF_S0 0x05 44 #define MC_CG_SEQ_DRAMCONF_S1 0x06 45 #define MC_CG_SEQ_YCLK_SUSPEND 0x04 46 #define MC_CG_SEQ_YCLK_RESUME 0x0a 48 #define SMC_RAM_END 0x8000 59 0x000008f8, 0x00000010, 0xffffffff, [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/include/nvhw/class/ |
H A D | clc57d.h | 27 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER (0x00000208) 28 #define NVC57D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 30 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS(a) (0x00001004 + (a)*0… 31 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP 0:0 32 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_FALSE (0x00000000) 33 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED1BPP_TRUE (0x00000001) 35 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_FALSE (0x00000000) 36 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED2BPP_TRUE (0x00000001) 38 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_FALSE (0x00000000) 39 #define NVC57D_WINDOW_SET_WINDOW_FORMAT_USAGE_BOUNDS_RGB_PACKED4BPP_TRUE (0x00000001) [all …]
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/openbmc/linux/arch/powerpc/include/uapi/asm/ |
H A D | termbits.h | 48 #define VINTR 0 67 #define IXON 0x0200 68 #define IXOFF 0x0400 69 #define IUCLC 0x1000 70 #define IMAXBEL 0x2000 71 #define IUTF8 0x4000 74 #define ONLCR 0x00002 75 #define OLCUC 0x00004 76 #define NLDLY 0x00300 77 #define NL0 0x00000 [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/top/ |
H A D | ga100.c | 31 int i, n, size = nvkm_rd32(device, 0x0224fc) >> 20; in ga100_top_parse() 33 for (i = 0, n = 0; i < size; i++) { in ga100_top_parse() 37 type = ~0; in ga100_top_parse() 38 inst = 0; in ga100_top_parse() 41 data = nvkm_rd32(device, 0x022800 + (i * 0x04)); in ga100_top_parse() 43 if (!data && n == 0) in ga100_top_parse() 47 case 0: in ga100_top_parse() 48 type = (data & 0x3f000000) >> 24; in ga100_top_parse() 49 inst = (data & 0x000f0000) >> 16; in ga100_top_parse() 50 info->fault = (data & 0x0000007f); in ga100_top_parse() [all …]
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H A D | gk104.c | 35 for (i = 0; i < 64; i++) { in gk104_top_parse() 39 type = ~0; in gk104_top_parse() 40 inst = 0; in gk104_top_parse() 43 data = nvkm_rd32(device, 0x022700 + (i * 0x04)); in gk104_top_parse() 45 switch (data & 0x00000003) { in gk104_top_parse() 46 case 0x00000000: /* NOT_VALID */ in gk104_top_parse() 48 case 0x00000001: /* DATA */ in gk104_top_parse() 49 inst = (data & 0x3c000000) >> 26; in gk104_top_parse() 50 info->addr = (data & 0x00fff000); in gk104_top_parse() 51 if (data & 0x00000004) in gk104_top_parse() [all …]
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/openbmc/linux/arch/alpha/include/uapi/asm/ |
H A D | termbits.h | 54 #define VEOF 0 73 #define IXON 0x0200 74 #define IXOFF 0x0400 75 #define IUCLC 0x1000 76 #define IMAXBEL 0x2000 77 #define IUTF8 0x4000 80 #define ONLCR 0x00002 81 #define OLCUC 0x00004 82 #define NLDLY 0x00300 83 #define NL0 0x00000 [all …]
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/openbmc/u-boot/board/xilinx/zynqmp/ |
H A D | tap_delays.c | 11 #define SD_DLL_CTRL 0xFF180358 12 #define SD_ITAP_DLY 0xFF180314 13 #define SD_OTAP_DLY 0xFF180318 14 #define SD0_DLL_RST_MASK 0x00000004 15 #define SD0_DLL_RST 0x00000004 16 #define SD1_DLL_RST_MASK 0x00040000 17 #define SD1_DLL_RST 0x00040000 18 #define SD0_ITAPCHGWIN_MASK 0x00000200 19 #define SD0_ITAPCHGWIN 0x00000200 20 #define SD1_ITAPCHGWIN_MASK 0x02000000 [all …]
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/openbmc/linux/drivers/net/wireless/ath/carl9170/ |
H A D | phy.c | 48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f); in carl9170_init_power_cal() 49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f); in carl9170_init_power_cal() 50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f); in carl9170_init_power_cal() 51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f); in carl9170_init_power_cal() 52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f); in carl9170_init_power_cal() 53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f); in carl9170_init_power_cal() 54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f); in carl9170_init_power_cal() 55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f); in carl9170_init_power_cal() 56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f); in carl9170_init_power_cal() 57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f); in carl9170_init_power_cal() [all …]
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/openbmc/u-boot/board/compulab/cl-som-imx7/ |
H A D | spl.c | 22 USDHC1_BASE_ADDR, 0, 4}; 38 .init1 = 0x00690000, 39 .init0 = 0x00020083, 40 .init3 = 0x09300004, 41 .init4 = 0x04080000, 42 .init5 = 0x00100004, 43 .rankctl = 0x0000033F, 44 .dramtmg1 = 0x0007020E, 45 .dramtmg2 = 0x03040407, 46 .dramtmg3 = 0x00002006, [all …]
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