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/openbmc/linux/drivers/pinctrl/spear/
H A Dpinctrl-spear300.c21 #define PMX_CONFIG_REG 0x00
22 #define MODE_CONFIG_REG 0x04
25 #define NAND_MODE (1 << 0)
43 .mask = 0x0000000F,
44 .val = 0x00,
51 .mask = 0x0000000F,
52 .val = 0x01,
59 .mask = 0x0000000F,
60 .val = 0x02,
67 .mask = 0x0000000F,
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dm5275.h16 #define MCF_GPIO_PAR_UART 0x10007c
17 #define UART0_ENABLE_MASK 0x000f
18 #define UART1_ENABLE_MASK 0x00f0
19 #define UART2_ENABLE_MASK 0x3f00
21 #define MCF_GPIO_PAR_FECI2C 0x100082
22 #define PAR_SDA_ENABLE_MASK 0x0003
23 #define PAR_SCL_ENABLE_MASK 0x000c
25 #define MCFSIM_WRRR 0x140000
26 #define MCFSIM_SDCR 0x40
33 #define MCF_SDRAMC_SDMR (*(vuint32*)(void*)(&__IPSBAR[0x000040]))
[all …]
H A Dm5227x.h13 #define INT0_LO_RSVD0 (0)
87 #define RCM_RCR_FRCRSTOUT (0x40)
88 #define RCM_RCR_SOFTRST (0x80)
91 #define RCM_RSR_LOL (0x01)
92 #define RCM_RSR_WDR_CORE (0x02)
93 #define RCM_RSR_EXT (0x04)
94 #define RCM_RSR_POR (0x08)
95 #define RCM_RSR_SOFT (0x20)
102 #define CCM_CCR_DRAMSEL (0x0100)
103 #define CCM_CCR_CSC_UNMASK (0xFF3F)
[all …]
/openbmc/linux/arch/x86/kernel/cpu/
H A Dscattered.c27 { X86_FEATURE_APERFMPERF, CPUID_ECX, 0, 0x00000006, 0 },
28 { X86_FEATURE_EPB, CPUID_ECX, 3, 0x00000006, 0 },
29 { X86_FEATURE_INTEL_PPIN, CPUID_EBX, 0, 0x00000007, 1 },
30 { X86_FEATURE_RRSBA_CTRL, CPUID_EDX, 2, 0x00000007, 2 },
31 { X86_FEATURE_BHI_CTRL, CPUID_EDX, 4, 0x00000007, 2 },
32 { X86_FEATURE_CQM_LLC, CPUID_EDX, 1, 0x0000000f, 0 },
33 { X86_FEATURE_CQM_OCCUP_LLC, CPUID_EDX, 0, 0x0000000f, 1 },
34 { X86_FEATURE_CQM_MBM_TOTAL, CPUID_EDX, 1, 0x0000000f, 1 },
35 { X86_FEATURE_CQM_MBM_LOCAL, CPUID_EDX, 2, 0x0000000f, 1 },
36 { X86_FEATURE_CAT_L3, CPUID_EBX, 1, 0x00000010, 0 },
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h26 #define BACO_CNTL__BACO_ANA_ISO_DIS_MASK 0x00000080L
27 #define BACO_CNTL__BACO_ANA_ISO_DIS__SHIFT 0x00000007
28 #define BACO_CNTL__BACO_BCLK_OFF_MASK 0x00000002L
29 #define BACO_CNTL__BACO_BCLK_OFF__SHIFT 0x00000001
30 #define BACO_CNTL__BACO_EN_MASK 0x00000001L
31 #define BACO_CNTL__BACO_EN__SHIFT 0x00000000
32 #define BACO_CNTL__BACO_HANG_PROTECTION_EN_MASK 0x00000020L
33 #define BACO_CNTL__BACO_HANG_PROTECTION_EN__SHIFT 0x00000005
34 #define BACO_CNTL__BACO_ISO_DIS_MASK 0x00000004L
35 #define BACO_CNTL__BACO_ISO_DIS__SHIFT 0x00000002
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-tf700t.dts18 port@0 {
92 reg = <0x10>;
111 mount-matrix = "1", "0", "0",
112 "0", "-1", "0",
113 "0", "0", "-1";
117 mount-matrix = "0", "1", "0",
118 "1", "0", "0",
119 "0", "0", "-1";
124 mount-matrix = "0", "-1", "0",
125 "-1", "0", "0",
[all …]
H A Dtegra124-nyan-blaze-emc.dtsi92 0x40040001
93 0x8000000a
94 0x00000001
95 0x00000001
96 0x00000002
97 0x00000000
98 0x00000002
99 0x00000001
100 0x00000002
101 0x00000008
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi104 0x40040001
105 0x8000000a
106 0x00000001
107 0x00000001
108 0x00000002
109 0x00000000
110 0x00000002
111 0x00000001
112 0x00000003
113 0x00000008
[all …]
H A Dtegra124-apalis-emc.dtsi108 0x40040001 0x8000000a
109 0x00000001 0x00000001
110 0x00000002 0x00000000
111 0x00000002 0x00000001
112 0x00000003 0x00000008
113 0x00000003 0x00000002
114 0x00000003 0x00000006
115 0x06030203 0x000a0502
116 0x77e30303 0x70000f03
117 0x001f0000
[all …]
H A Dtegra30-asus-tf300t.dts75 reg = <0x10>;
94 mount-matrix = "0", "-1", "0",
95 "-1", "0", "0",
96 "0", "0", "-1";
100 mount-matrix = "-1", "0", "0",
101 "0", "1", "0",
102 "0", "0", "-1";
107 mount-matrix = "0", "-1", "0",
108 "-1", "0", "0",
109 "0", "0", "1";
[all …]
H A Dtegra30-asus-tf300tg.dts22 <TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
171 reg = <0x10>;
190 mount-matrix = "1", "0", "0",
191 "0", "-1", "0",
192 "0", "0", "-1";
196 mount-matrix = "-1", "0", "0",
197 "0", "1", "0",
198 "0", "0", "-1";
203 mount-matrix = "0", "-1", "0",
204 "-1", "0", "0",
[all …]
/openbmc/linux/net/core/
H A Dptp_classifier.c16 * jneq #0x800, test_ipv6 ; ETH_P_IP ?
20 * jset #0x1fff, drop_ipv4 ; don't allow fragments
21 * ldxb 4*([14]&0xf) ; load IP header len
25 * and #0xf ; mask PTP_CLASS_VMASK
26 * or #0x10 ; PTP_CLASS_IPV4
28 * drop_ipv4: ret #0x0 ; PTP_CLASS_NONE
32 * jneq #0x86dd, test_8021q ; ETH_P_IPV6 ?
38 * and #0xf ; mask PTP_CLASS_VMASK
39 * or #0x20 ; PTP_CLASS_IPV6
41 * drop_ipv6: ret #0x0 ; PTP_CLASS_NONE
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_0_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
H A Dsdma0_4_1_default.h26 #define mmSDMA0_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA0_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA0_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA0_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA0_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA0_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA0_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA0_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA0_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
35 #define mmSDMA0_CONTEXT_REG_TYPE1_DEFAULT 0x003fbcff
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/sdma1/
H A Dsdma1_4_0_default.h26 #define mmSDMA1_UCODE_ADDR_DEFAULT 0x00000000
27 #define mmSDMA1_UCODE_DATA_DEFAULT 0x00000000
28 #define mmSDMA1_VM_CNTL_DEFAULT 0x00000000
29 #define mmSDMA1_VM_CTX_LO_DEFAULT 0x00000000
30 #define mmSDMA1_VM_CTX_HI_DEFAULT 0x00000000
31 #define mmSDMA1_ACTIVE_FCN_ID_DEFAULT 0x00000000
32 #define mmSDMA1_VM_CTX_CNTL_DEFAULT 0x00000000
33 #define mmSDMA1_VIRT_RESET_REQ_DEFAULT 0x00000000
34 #define mmSDMA1_VF_ENABLE_DEFAULT 0x00000000
35 #define mmSDMA1_CONTEXT_REG_TYPE0_DEFAULT 0xfffdf79f
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata_priv.h22 #define SATA_HOST_CAP_S64A 0x80000000
23 #define SATA_HOST_CAP_SNCQ 0x40000000
24 #define SATA_HOST_CAP_SSNTF 0x20000000
25 #define SATA_HOST_CAP_SMPS 0x10000000
26 #define SATA_HOST_CAP_SSS 0x08000000
27 #define SATA_HOST_CAP_SALP 0x04000000
28 #define SATA_HOST_CAP_SAL 0x02000000
29 #define SATA_HOST_CAP_SCLO 0x01000000
30 #define SATA_HOST_CAP_ISS_MASK 0x00f00000
32 #define SATA_HOST_CAP_SNZO 0x00080000
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gmc/
H A Dgmc_6_0_sh_mask.h26 #define ATC_ATS_CNTL__CREDITS_ATS_RPB_MASK 0x00003f00L
27 #define ATC_ATS_CNTL__CREDITS_ATS_RPB__SHIFT 0x00000008
28 #define ATC_ATS_CNTL__DEBUG_ECO_MASK 0x000f0000L
29 #define ATC_ATS_CNTL__DEBUG_ECO__SHIFT 0x00000010
30 #define ATC_ATS_CNTL__DISABLE_ATC_MASK 0x00000001L
31 #define ATC_ATS_CNTL__DISABLE_ATC__SHIFT 0x00000000
32 #define ATC_ATS_CNTL__DISABLE_PASID_MASK 0x00000004L
33 #define ATC_ATS_CNTL__DISABLE_PASID__SHIFT 0x00000002
34 #define ATC_ATS_CNTL__DISABLE_PRI_MASK 0x00000002L
35 #define ATC_ATS_CNTL__DISABLE_PRI__SHIFT 0x00000001
[all …]
/openbmc/linux/drivers/gpu/drm/etnaviv/
H A Dstate_hi.xml.h7 http://0x04.net/cgit/index.cgi/rules-ng-ng
8 git clone git://0x04.net/rules-ng-ng
48 #define MMU_EXCEPTION_SLAVE_NOT_PRESENT 0x00000001
49 #define MMU_EXCEPTION_PAGE_NOT_PRESENT 0x00000002
50 #define MMU_EXCEPTION_WRITE_VIOLATION 0x00000003
51 #define MMU_EXCEPTION_OUT_OF_BOUND 0x00000004
52 #define MMU_EXCEPTION_READ_SECURITY_VIOLATION 0x00000005
53 #define MMU_EXCEPTION_WRITE_SECURITY_VIOLATION 0x00000006
54 #define VIVS_HI 0x00000000
56 #define VIVS_HI_CLOCK_CONTROL 0x00000000
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c30 writel(0, &emc->config); in ddr_init()
32 writel(0x7FF, &emc->refresh); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
45 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
46 writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); in ddr_init()
47 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); in ddr_init()
52 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); in ddr_init()
[all …]
/openbmc/linux/drivers/scsi/lpfc/
H A Dlpfc_hw4.h36 * #define example_bit_field_MASK 0x03
47 * bf_set(example_bit_field, &t1, 0);
63 #define get_wqe_reqtag(x) (((x)->wqe.words[9] >> 0) & 0xFFFF)
64 #define get_wqe_tmo(x) (((x)->wqe.words[7] >> 24) & 0x00FF)
79 #define lpfc_sli_intf_valid_MASK 0x00000007
83 #define lpfc_sli_intf_sli_hint2_MASK 0x0000001F
85 #define LPFC_SLI_INTF_SLI_HINT2_NONE 0
87 #define lpfc_sli_intf_sli_hint1_MASK 0x000000FF
89 #define LPFC_SLI_INTF_SLI_HINT1_NONE 0
93 #define lpfc_sli_intf_if_type_MASK 0x0000000F
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h26 #define BCI_DEBUG_READ__DATA_MASK 0x00ffffffL
27 #define BCI_DEBUG_READ__DATA__SHIFT 0x00000000
28 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN_MASK 0x00e00000L
29 #define CB_BLEND0_CONTROL__ALPHA_COMB_FCN__SHIFT 0x00000015
30 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND_MASK 0x1f000000L
31 #define CB_BLEND0_CONTROL__ALPHA_DESTBLEND__SHIFT 0x00000018
32 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND_MASK 0x001f0000L
33 #define CB_BLEND0_CONTROL__ALPHA_SRCBLEND__SHIFT 0x00000010
34 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN_MASK 0x000000e0L
35 #define CB_BLEND0_CONTROL__COLOR_COMB_FCN__SHIFT 0x00000005
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_default.h27 #define mmSDMA0_DEC_START_DEFAULT 0x00000000
28 #define mmSDMA0_GLOBAL_TIMESTAMP_LO_DEFAULT 0x00000000
29 #define mmSDMA0_GLOBAL_TIMESTAMP_HI_DEFAULT 0x00000000
30 #define mmSDMA0_PG_CNTL_DEFAULT 0x00000000
31 #define mmSDMA0_PG_CTX_LO_DEFAULT 0x00000000
32 #define mmSDMA0_PG_CTX_HI_DEFAULT 0x00000000
33 #define mmSDMA0_PG_CTX_CNTL_DEFAULT 0x00000000
34 #define mmSDMA0_POWER_CNTL_DEFAULT 0x40000050
35 #define mmSDMA0_CLK_CTRL_DEFAULT 0x00000100
36 #define mmSDMA0_CNTL_DEFAULT 0x000000c2
[all …]
/openbmc/linux/drivers/net/wireless/ralink/rt2x00/
H A Drt2800.h49 #define RF2820 0x0001
50 #define RF2850 0x0002
51 #define RF2720 0x0003
52 #define RF2750 0x0004
53 #define RF3020 0x0005
54 #define RF2020 0x0006
55 #define RF3021 0x0007
56 #define RF3022 0x0008
57 #define RF3052 0x0009
58 #define RF2853 0x000a
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Dsi_blit_shaders.h29 0xc0066900,
30 0x00000000,
31 0x00000060, /* DB_RENDER_CONTROL */
32 0x00000000, /* DB_COUNT_CONTROL */
33 0x00000000, /* DB_DEPTH_VIEW */
34 0x0000002a, /* DB_RENDER_OVERRIDE */
35 0x00000000, /* DB_RENDER_OVERRIDE2 */
36 0x00000000, /* DB_HTILE_DATA_BASE */
38 0xc0046900,
39 0x00000008,
[all …]
H A Dcik_blit_shaders.h32 0xc0066900,
33 0x00000000,
34 0x00000060, /* DB_RENDER_CONTROL */
35 0x00000000, /* DB_COUNT_CONTROL */
36 0x00000000, /* DB_DEPTH_VIEW */
37 0x0000002a, /* DB_RENDER_OVERRIDE */
38 0x00000000, /* DB_RENDER_OVERRIDE2 */
39 0x00000000, /* DB_HTILE_DATA_BASE */
41 0xc0046900,
42 0x00000008,
[all …]

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