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/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dpixfmt-rgb.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _pixfmt-rgb:
22 (including capture queues of mem-to-mem devices) fill the alpha component in
25 but can set the alpha bit to a user-configurable value, the
26 :ref:`V4L2_CID_ALPHA_COMPONENT <v4l2-alpha-component>` control is used to
31 :ref:`Output <output>` devices (including output queues of mem-to-mem devices
44 - In all the tables that follow, bit 7 is the most significant bit in a byte.
45 - 'r', 'g' and 'b' denote bits of the red, green and blue components
54 based on the order of the RGB components as seen in a 8-, 16- or 32-bit word,
56 noted by the presence of bit 31 in the 4CC value), and on the number of bits
[all …]
H A Dpixfmt-srggb10-ipu3.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-pix-fmt-ipu3-sbggr10:
4 .. _v4l2-pix-fmt-ipu3-sgbrg10:
5 .. _v4l2-pix-fmt-ipu3-sgrbg10:
6 .. _v4l2-pix-fmt-ipu3-srggb10:
13 10-bit Bayer formats
24 In other respects this format is similar to :ref:`V4L2-PIX-FMT-SRGGB10`.
36 .. flat-table::
38 * - start + 0:
39 - B\ :sub:`0000low`
[all …]
H A Dsubdev-formats.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
23 - ``height``
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H A Dmetafmt-vsp1-hgo.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-meta-fmt-vsp1-hgo:
9 Renesas R-Car VSP1 1-D Histogram Data
15 This format describes histogram data generated by the Renesas R-Car VSP1 1-D
20 computes the minimum, maximum and sum of all pixels as well as per-channel
28 - In *64 bins normal mode*, the HGO operates on the three channels independently
29 to compute three 64-bins histograms. RGB, YCbCr and HSV image formats are
31 - In *64 bins maximum mode*, the HGO operates on the maximum of the (R, G, B)
32 channels to compute a single 64-bins histogram. Only the RGB image format is
34 - In *256 bins normal mode*, the HGO operates on the Y channel to compute a
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H A Dpixfmt-srggb14p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB14P:
4 .. _v4l2-pix-fmt-sbggr14p:
5 .. _v4l2-pix-fmt-sgbrg14p:
6 .. _v4l2-pix-fmt-sgrbg14p:
17 14-bit packed Bayer formats
29 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
30 with alternating green-red and green-blue rows. They are conventionally
45 .. flat-table::
46 :header-rows: 0
[all …]
H A Dpixfmt-srggb12p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB12P:
4 .. _v4l2-pix-fmt-sbggr12p:
5 .. _v4l2-pix-fmt-sgbrg12p:
6 .. _v4l2-pix-fmt-sgrbg12p:
13 12-bit packed Bayer formats
14 ---------------------------
26 Each n-pixel row contains n/2 green samples and n/2 blue or red
27 samples, with alternating green-red and green-blue rows. They are
37 .. flat-table::
[all …]
H A Dpixfmt-srggb10p.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _V4L2-PIX-FMT-SRGGB10P:
4 .. _v4l2-pix-fmt-sbggr10p:
5 .. _v4l2-pix-fmt-sgbrg10p:
6 .. _v4l2-pix-fmt-sgrbg10p:
16 10-bit packed Bayer formats
24 bytes. Each of the first 4 bytes contain the 8 high order bits
28 Each n-pixel row contains n/2 green samples and n/2 blue or red samples,
29 with alternating green-red and green-blue rows. They are conventionally
38 .. flat-table::
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/openbmc/linux/drivers/media/platform/samsung/exynos-gsc/
H A Dgsc-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
6 * Register definition file for Samsung G-Scaler driver
12 /* G-Scaler enable */
18 /* G-Scaler S/W reset */
22 /* G-Scaler IRQ */
29 /* G-Scaler input control */
35 #define GSC_IN_ROT_90 (4 << 16)
55 #define GSC_IN_YUV422_1P (4 << 8)
58 #define GSC_IN_TILE_TYPE_MASK (1 << 4)
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/openbmc/linux/drivers/gpu/drm/exynos/
H A Dregs-gsc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* linux/drivers/gpu/drm/exynos/regs-gsc.h
7 * Register definition file for Samsung G-Scaler driver
13 /* G-Scaler enable */
26 #define GSC_ENABLE_ON_CLEAR_MASK (1 << 4)
27 #define GSC_ENABLE_ON_CLEAR_ONESHOT (1 << 4)
33 /* G-Scaler S/W reset */
37 /* G-Scaler IRQ */
45 /* G-Scaler input control */
55 #define GSC_IN_ROT_90 (4 << 16)
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/openbmc/u-boot/include/
H A Dipu_pixfmt.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * (C) Copyright 2005-2010 Freescale Semiconductor, Inc.
31 #define IPU_PIX_FMT_RGB332 fourcc('R', 'G', 'B', '1') /*< 8 RGB-3-3-2 */
32 #define IPU_PIX_FMT_RGB555 fourcc('R', 'G', 'B', 'O') /*< 16 RGB-5-5-5 */
33 #define IPU_PIX_FMT_RGB565 fourcc('R', 'G', 'B', 'P') /*< 1 6 RGB-5-6-5 */
34 #define IPU_PIX_FMT_RGB666 fourcc('R', 'G', 'B', '6') /*< 18 RGB-6-6-6 */
35 #define IPU_PIX_FMT_BGR666 fourcc('B', 'G', 'R', '6') /*< 18 BGR-6-6-6 */
36 #define IPU_PIX_FMT_BGR24 fourcc('B', 'G', 'R', '3') /*< 24 BGR-8-8-8 */
37 #define IPU_PIX_FMT_RGB24 fourcc('R', 'G', 'B', '3') /*< 24 RGB-8-8-8 */
38 #define IPU_PIX_FMT_BGR32 fourcc('B', 'G', 'R', '4') /*< 32 BGR-8-8-8-8 */
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/openbmc/qemu/hw/display/
H A Dpl110_template.h36 #define FN_8(y) FN_4(0, y) FN_4(4, y)
45 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 7 - (x))) & 1]); in glue()
61 width -= 32; in glue()
62 src += 4; in glue()
73 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 6 - (x)*2)) & 3]); in glue()
89 width -= 16; in glue()
90 src += 4; in glue()
101 #define FN(x, y) COPY_PIXEL(d, palette[(data >> (y + 4 - (x)*4)) & 0xf]); in glue()
103 #define FN(x, y) COPY_PIXEL(d, palette[(data >> ((x)*4 + y)) & 0xf]); in glue()
117 width -= 8; in glue()
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H A Domap_lcdc.c4 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
55 if (s->frame_done && (s->interrupts & 1)) { in omap_lcd_interrupts()
56 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
60 if (s->palette_done && (s->interrupts & 2)) { in omap_lcd_interrupts()
61 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
65 if (s->sync_error) { in omap_lcd_interrupts()
66 qemu_irq_raise(s->irq); in omap_lcd_interrupts()
70 qemu_irq_lower(s->irq); in omap_lcd_interrupts()
74 * 2-bit colour
80 uint8_t v, r, g, b; in draw_line2_32() local
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H A Dvga-helpers.h28 ((uint32_t *)d)[0] = (-((font_data >> 7)) & xorcol) ^ bgcol; in vga_draw_glyph_line()
29 ((uint32_t *)d)[1] = (-((font_data >> 6) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
30 ((uint32_t *)d)[2] = (-((font_data >> 5) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
31 ((uint32_t *)d)[3] = (-((font_data >> 4) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
32 ((uint32_t *)d)[4] = (-((font_data >> 3) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
33 ((uint32_t *)d)[5] = (-((font_data >> 2) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
34 ((uint32_t *)d)[6] = (-((font_data >> 1) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
35 ((uint32_t *)d)[7] = (-((font_data >> 0) & 1) & xorcol) ^ bgcol; in vga_draw_glyph_line()
48 font_ptr += 4; in vga_draw_glyph8()
50 } while (--h); in vga_draw_glyph8()
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/openbmc/linux/include/dt-bindings/memory/
H A Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
22 * modules dma-address-region larbs-ports
23 * disp 0 ~ 4G larb0/1/2
24 * vcodec 4G ~ 8G larb4/7
25 * cam/mdp 8G ~ 12G the other larbs.
26 * N/A 12G ~ 16G
28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb14: port 4/5
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main_regs.h1 /* SPDX-License-Identifier: GPL-2.0+
7 /* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100.
21 TARGET_ANA_AC_POL = 4,
62 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4)
78 0, 1, 894472, 0, 1, 352, 52, r, 3, 4)
80 #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0)
87 #define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ argument
88 0, 1, 849920, g, 102, 16, 0, 0, 1, 4)
91 #define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ argument
92 0, 1, 849920, g, 102, 16, 4, 0, 1, 4)
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/openbmc/linux/drivers/staging/vc04_services/vchiq-mmal/
H A Dmmal-encodings.h1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define MMAL_ENCODING_H264 MMAL_FOURCC('H', '2', '6', '4')
18 #define MMAL_ENCODING_MP4V MMAL_FOURCC('M', 'P', '4', 'V')
30 #define MMAL_ENCODING_MJPEG MMAL_FOURCC('M', 'J', 'P', 'G')
32 #define MMAL_ENCODING_JPEG MMAL_FOURCC('J', 'P', 'E', 'G')
33 #define MMAL_ENCODING_GIF MMAL_FOURCC('G', 'I', 'F', ' ')
34 #define MMAL_ENCODING_PNG MMAL_FOURCC('P', 'N', 'G', ' ')
36 #define MMAL_ENCODING_TGA MMAL_FOURCC('T', 'G', 'A', ' ')
39 #define MMAL_ENCODING_I420 MMAL_FOURCC('I', '4', '2', '0')
40 #define MMAL_ENCODING_I420_SLICE MMAL_FOURCC('S', '4', '2', '0')
[all …]
/openbmc/linux/drivers/iio/accel/
H A Dbma400.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * Read-Only Registers
43 #define BMA400_INT_ENG_OVRUN_MSK BIT(4)
63 * Read-write configuration registers
81 #define BMA400_NP_OSR_SHIFT 4
86 #define BMA400_NP_OSR_MASK GENMASK(5, 4)
119 #define BMA400_TAP_QUIETDT_MSK GENMASK(5, 4)
120 #define BMA400_TAP_TIM_LIST_LEN 4
124 * converting to micro values for +-2g range.
126 * For +-2g - 1 LSB = 0.976562 milli g = 0.009576 m/s^2
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/openbmc/linux/tools/perf/bench/
H A Dnuma.c1 // SPDX-License-Identifier: GPL-2.0
5 * numa: Simulate NUMA-sensitive workload and measure their NUMA performance
10 #include <subcmd/parse-options.h>
46 * Regular printout to the terminal, suppressed if -q is specified:
48 #define tprintf(x...) do { if (g && g->p.show_details >= 0) printf(x); } while (0)
54 #define dprintf(x...) do { if (g && g->p.show_details >= 1) printf(x); } while (0)
128 /* Affinity options -C and -N: */
134 /* Global, read-writable area, accessible to all processes and threads: */
162 static struct global_info *g = NULL; variable
173 OPT_STRING('G', "mb_global" , &p0.mb_global_str, "MB", "global memory (MBs)"),
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/openbmc/linux/arch/x86/crypto/
H A Dsha256-avx2-asm.S2 # Implement fast SHA-256 with AVX2 instructions. (x86_64)
21 # - Redistributions of source code must retain the above
25 # - Redistributions in binary form must reproduce the above
41 # This code is described in an Intel White-Paper:
42 # "Fast SHA-256 Implementations on Intel Architecture Processors"
48 # This code schedules 2 blocks at a time, with 4 lanes per block
60 # Add reg to mem using reg-mem add and store
87 SHUF_00BA = %ymm10 # shuffle xBxA -> 00BA
88 SHUF_DC00 = %ymm12 # shuffle xDxC -> DC00
106 g = %r10d define
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/openbmc/qemu/tests/functional/
H A Dtest_mem_addr_space.py11 # SPDX-License-Identifier: GPL-2.0-or-later
23 # first, lets test some 32-bit processors.
24 # for all 32-bit cases, pci64_hole_size is 0.
29 at 4 GiB boundary when "above_4g_mem_size" is 0 (this would be true when
36 Note that 64-bit pci hole size is 0 in this case. If maxmem is set to
37 59.6G, QEMU should fail to start with a message "phy-bits are too low".
38 If maxmem is set to 59.5G with all other QEMU parameters identical, QEMU
41 self.vm.add_args('-S', '-machine', 'q35', '-m',
42 '512,slots=1,maxmem=59.6G',
43 '-cpu', 'pentium,pse36=on', '-display', 'none',
[all …]
/openbmc/linux/drivers/staging/most/dim2/
H A Dhal.c1 // SPDX-License-Identifier: GPL-2.0
3 * hal.c - DIM2 HAL implementation
6 * Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
25 * Number of 32-bit units for DBR map.
29 * 4: block size is 128, max allocation is 4K
37 /* -------------------------------------------------------------------------- */
50 /* -------------------------------------------------------------------------- */
64 /* -------------------------------------------------------------------------- */
84 static struct lld_global_vars_t g = { false }; variable
86 /* -------------------------------------------------------------------------- */
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/openbmc/qemu/tcg/
H A Dtcg-op-gvec.c22 #include "tcg/tcg-temp-internal.h"
23 #include "tcg/tcg-op-common.h"
24 #include "tcg/tcg-op-gvec-common.h"
25 #include "tcg/tcg-gvec-desc.h"
27 #define MAX_UNROLL 4
99 * values from the caller will not be detected, e.g. if the in simd_desc()
101 * incorrectly passes us 1 << (SIMD_DATA_BITS - 1). in simd_desc()
106 oprsz = (oprsz / 8) - 1; in simd_desc()
107 maxsz = (maxsz / 8) - 1; in simd_desc()
125 /* Generate a call to a gvec-style helper with two vector operands. */
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/openbmc/linux/drivers/net/ethernet/brocade/bna/
H A Dbfa_defs_mfg_comm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Linux network driver for QLogic BR-series Converged Network Adapter.
6 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
7 * Copyright (c) 2014-2015 QLogic Corporation
27 #define BFA_MFG_HDR_LEN 4
30 #define STRSZ(_n) (((_n) + 4) & ~3)
35 BFA_MFG_TYPE_FC8P2 = 825, /*!< 8G 2port FC card */
36 BFA_MFG_TYPE_FC8P1 = 815, /*!< 8G 1port FC card */
37 BFA_MFG_TYPE_FC4P2 = 425, /*!< 4G 2port FC card */
38 BFA_MFG_TYPE_FC4P1 = 415, /*!< 4G 1port FC card */
[all …]
/openbmc/openbmc/poky/meta/recipes-extended/unzip/unzip/
H A D11-cve-2014-8141-getzip64data.patch2 Subject: Fix CVE-2014-8141: out-of-bounds read issues in getZip64Data()
3 Bug-Debian: http://bugs.debian.org/773722
5 The patch comes from unzip_6.0-8+deb7u2.debian.tar.gz
7 Upstream-Status: Backport
8 CVE: CVE-2014-8141
10 Signed-off-by: Roy Li <rongqing.li@windriver.com>
13 --- a/fileio.c
15 @@ -176,6 +176,8 @@
24 @@ -2295,7 +2297,12 @@
25 if (readbuf(__G__ (char *)G.extra_field, length) == 0)
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/openbmc/u-boot/lib/
H A Dsha256.c1 // SPDX-License-Identifier: GPL-2.0+
3 * FIPS-180-2 compliant SHA-256 implementation
5 * Copyright (C) 2001-2003 Christophe Devine
15 #include <u-boot/sha256.h>
24 * 32-bit integer manipulation macros (big endian)
45 ctx->total[0] = 0; in sha256_starts()
46 ctx->total[1] = 0; in sha256_starts()
48 ctx->state[0] = 0x6A09E667; in sha256_starts()
49 ctx->state[1] = 0xBB67AE85; in sha256_starts()
50 ctx->state[2] = 0x3C6EF372; in sha256_starts()
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