1 /*
2 * AMD 10Gb Ethernet driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 * This file incorporates work covered by the following copyright and
25 * permission notice:
26 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
27 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
28 * Inc. unless otherwise expressly agreed to in writing between Synopsys
29 * and you.
30 *
31 * The Software IS NOT an item of Licensed Software or Licensed Product
32 * under any End User Software License Agreement or Agreement for Licensed
33 * Product with Synopsys or any supplement thereto. Permission is hereby
34 * granted, free of charge, to any person obtaining a copy of this software
35 * annotated with this license and the Software, to deal in the Software
36 * without restriction, including without limitation the rights to use,
37 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
38 * of the Software, and to permit persons to whom the Software is furnished
39 * to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
45 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
46 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
47 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
48 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
54 * THE POSSIBILITY OF SUCH DAMAGE.
55 *
56 *
57 * License 2: Modified BSD
58 *
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
60 * All rights reserved.
61 *
62 * Redistribution and use in source and binary forms, with or without
63 * modification, are permitted provided that the following conditions are met:
64 * * Redistributions of source code must retain the above copyright
65 * notice, this list of conditions and the following disclaimer.
66 * * Redistributions in binary form must reproduce the above copyright
67 * notice, this list of conditions and the following disclaimer in the
68 * documentation and/or other materials provided with the distribution.
69 * * Neither the name of Advanced Micro Devices, Inc. nor the
70 * names of its contributors may be used to endorse or promote products
71 * derived from this software without specific prior written permission.
72 *
73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
76 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
77 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
78 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
79 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
80 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
81 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
82 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
83 *
84 * This file incorporates work covered by the following copyright and
85 * permission notice:
86 * The Synopsys DWC ETHER XGMAC Software Driver and documentation
87 * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
88 * Inc. unless otherwise expressly agreed to in writing between Synopsys
89 * and you.
90 *
91 * The Software IS NOT an item of Licensed Software or Licensed Product
92 * under any End User Software License Agreement or Agreement for Licensed
93 * Product with Synopsys or any supplement thereto. Permission is hereby
94 * granted, free of charge, to any person obtaining a copy of this software
95 * annotated with this license and the Software, to deal in the Software
96 * without restriction, including without limitation the rights to use,
97 * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
98 * of the Software, and to permit persons to whom the Software is furnished
99 * to do so, subject to the following conditions:
100 *
101 * The above copyright notice and this permission notice shall be included
102 * in all copies or substantial portions of the Software.
103 *
104 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
105 * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
106 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
107 * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
108 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
109 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
110 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
111 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
112 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
113 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
114 * THE POSSIBILITY OF SUCH DAMAGE.
115 */
116
117 #include <linux/interrupt.h>
118 #include <linux/module.h>
119 #include <linux/kmod.h>
120 #include <linux/mdio.h>
121 #include <linux/phy.h>
122 #include <linux/of.h>
123 #include <linux/bitops.h>
124 #include <linux/jiffies.h>
125
126 #include "xgbe.h"
127 #include "xgbe-common.h"
128
xgbe_phy_module_eeprom(struct xgbe_prv_data * pdata,struct ethtool_eeprom * eeprom,u8 * data)129 static int xgbe_phy_module_eeprom(struct xgbe_prv_data *pdata,
130 struct ethtool_eeprom *eeprom, u8 *data)
131 {
132 if (!pdata->phy_if.phy_impl.module_eeprom)
133 return -ENXIO;
134
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data);
136 }
137
xgbe_phy_module_info(struct xgbe_prv_data * pdata,struct ethtool_modinfo * modinfo)138 static int xgbe_phy_module_info(struct xgbe_prv_data *pdata,
139 struct ethtool_modinfo *modinfo)
140 {
141 if (!pdata->phy_if.phy_impl.module_info)
142 return -ENXIO;
143
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo);
145 }
146
xgbe_an37_clear_interrupts(struct xgbe_prv_data * pdata)147 static void xgbe_an37_clear_interrupts(struct xgbe_prv_data *pdata)
148 {
149 int reg;
150
151 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
152 reg &= ~XGBE_AN_CL37_INT_MASK;
153 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
154 }
155
xgbe_an37_disable_interrupts(struct xgbe_prv_data * pdata)156 static void xgbe_an37_disable_interrupts(struct xgbe_prv_data *pdata)
157 {
158 int reg;
159
160 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
161 reg &= ~XGBE_AN_CL37_INT_MASK;
162 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
163
164 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
165 reg &= ~XGBE_PCS_CL37_BP;
166 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
167 }
168
xgbe_an37_enable_interrupts(struct xgbe_prv_data * pdata)169 static void xgbe_an37_enable_interrupts(struct xgbe_prv_data *pdata)
170 {
171 int reg;
172
173 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL);
174 reg |= XGBE_PCS_CL37_BP;
175 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_PCS_DIG_CTRL, reg);
176
177 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
178 reg |= XGBE_AN_CL37_INT_MASK;
179 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
180 }
181
xgbe_an73_clear_interrupts(struct xgbe_prv_data * pdata)182 static void xgbe_an73_clear_interrupts(struct xgbe_prv_data *pdata)
183 {
184 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, 0);
185 }
186
xgbe_an73_disable_interrupts(struct xgbe_prv_data * pdata)187 static void xgbe_an73_disable_interrupts(struct xgbe_prv_data *pdata)
188 {
189 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
190 }
191
xgbe_an73_enable_interrupts(struct xgbe_prv_data * pdata)192 static void xgbe_an73_enable_interrupts(struct xgbe_prv_data *pdata)
193 {
194 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INTMASK, XGBE_AN_CL73_INT_MASK);
195 }
196
xgbe_an_enable_interrupts(struct xgbe_prv_data * pdata)197 static void xgbe_an_enable_interrupts(struct xgbe_prv_data *pdata)
198 {
199 switch (pdata->an_mode) {
200 case XGBE_AN_MODE_CL73:
201 case XGBE_AN_MODE_CL73_REDRV:
202 xgbe_an73_enable_interrupts(pdata);
203 break;
204 case XGBE_AN_MODE_CL37:
205 case XGBE_AN_MODE_CL37_SGMII:
206 xgbe_an37_enable_interrupts(pdata);
207 break;
208 default:
209 break;
210 }
211 }
212
xgbe_an_clear_interrupts_all(struct xgbe_prv_data * pdata)213 static void xgbe_an_clear_interrupts_all(struct xgbe_prv_data *pdata)
214 {
215 xgbe_an73_clear_interrupts(pdata);
216 xgbe_an37_clear_interrupts(pdata);
217 }
218
xgbe_kr_mode(struct xgbe_prv_data * pdata)219 static void xgbe_kr_mode(struct xgbe_prv_data *pdata)
220 {
221 /* Set MAC to 10G speed */
222 pdata->hw_if.set_speed(pdata, SPEED_10000);
223
224 /* Call PHY implementation support to complete rate change */
225 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KR);
226 }
227
xgbe_kx_2500_mode(struct xgbe_prv_data * pdata)228 static void xgbe_kx_2500_mode(struct xgbe_prv_data *pdata)
229 {
230 /* Set MAC to 2.5G speed */
231 pdata->hw_if.set_speed(pdata, SPEED_2500);
232
233 /* Call PHY implementation support to complete rate change */
234 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_2500);
235 }
236
xgbe_kx_1000_mode(struct xgbe_prv_data * pdata)237 static void xgbe_kx_1000_mode(struct xgbe_prv_data *pdata)
238 {
239 /* Set MAC to 1G speed */
240 pdata->hw_if.set_speed(pdata, SPEED_1000);
241
242 /* Call PHY implementation support to complete rate change */
243 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_KX_1000);
244 }
245
xgbe_sfi_mode(struct xgbe_prv_data * pdata)246 static void xgbe_sfi_mode(struct xgbe_prv_data *pdata)
247 {
248 /* If a KR re-driver is present, change to KR mode instead */
249 if (pdata->kr_redrv)
250 return xgbe_kr_mode(pdata);
251
252 /* Set MAC to 10G speed */
253 pdata->hw_if.set_speed(pdata, SPEED_10000);
254
255 /* Call PHY implementation support to complete rate change */
256 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SFI);
257 }
258
xgbe_x_mode(struct xgbe_prv_data * pdata)259 static void xgbe_x_mode(struct xgbe_prv_data *pdata)
260 {
261 /* Set MAC to 1G speed */
262 pdata->hw_if.set_speed(pdata, SPEED_1000);
263
264 /* Call PHY implementation support to complete rate change */
265 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_X);
266 }
267
xgbe_sgmii_1000_mode(struct xgbe_prv_data * pdata)268 static void xgbe_sgmii_1000_mode(struct xgbe_prv_data *pdata)
269 {
270 /* Set MAC to 1G speed */
271 pdata->hw_if.set_speed(pdata, SPEED_1000);
272
273 /* Call PHY implementation support to complete rate change */
274 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_1000);
275 }
276
xgbe_sgmii_10_mode(struct xgbe_prv_data * pdata)277 static void xgbe_sgmii_10_mode(struct xgbe_prv_data *pdata)
278 {
279 /* Set MAC to 10M speed */
280 pdata->hw_if.set_speed(pdata, SPEED_10);
281
282 /* Call PHY implementation support to complete rate change */
283 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_10);
284 }
285
xgbe_sgmii_100_mode(struct xgbe_prv_data * pdata)286 static void xgbe_sgmii_100_mode(struct xgbe_prv_data *pdata)
287 {
288 /* Set MAC to 1G speed */
289 pdata->hw_if.set_speed(pdata, SPEED_1000);
290
291 /* Call PHY implementation support to complete rate change */
292 pdata->phy_if.phy_impl.set_mode(pdata, XGBE_MODE_SGMII_100);
293 }
294
xgbe_cur_mode(struct xgbe_prv_data * pdata)295 static enum xgbe_mode xgbe_cur_mode(struct xgbe_prv_data *pdata)
296 {
297 return pdata->phy_if.phy_impl.cur_mode(pdata);
298 }
299
xgbe_in_kr_mode(struct xgbe_prv_data * pdata)300 static bool xgbe_in_kr_mode(struct xgbe_prv_data *pdata)
301 {
302 return (xgbe_cur_mode(pdata) == XGBE_MODE_KR);
303 }
304
xgbe_change_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)305 static void xgbe_change_mode(struct xgbe_prv_data *pdata,
306 enum xgbe_mode mode)
307 {
308 switch (mode) {
309 case XGBE_MODE_KX_1000:
310 xgbe_kx_1000_mode(pdata);
311 break;
312 case XGBE_MODE_KX_2500:
313 xgbe_kx_2500_mode(pdata);
314 break;
315 case XGBE_MODE_KR:
316 xgbe_kr_mode(pdata);
317 break;
318 case XGBE_MODE_SGMII_10:
319 xgbe_sgmii_10_mode(pdata);
320 break;
321 case XGBE_MODE_SGMII_100:
322 xgbe_sgmii_100_mode(pdata);
323 break;
324 case XGBE_MODE_SGMII_1000:
325 xgbe_sgmii_1000_mode(pdata);
326 break;
327 case XGBE_MODE_X:
328 xgbe_x_mode(pdata);
329 break;
330 case XGBE_MODE_SFI:
331 xgbe_sfi_mode(pdata);
332 break;
333 case XGBE_MODE_UNKNOWN:
334 break;
335 default:
336 netif_dbg(pdata, link, pdata->netdev,
337 "invalid operation mode requested (%u)\n", mode);
338 }
339 }
340
xgbe_switch_mode(struct xgbe_prv_data * pdata)341 static void xgbe_switch_mode(struct xgbe_prv_data *pdata)
342 {
343 xgbe_change_mode(pdata, pdata->phy_if.phy_impl.switch_mode(pdata));
344 }
345
xgbe_set_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)346 static bool xgbe_set_mode(struct xgbe_prv_data *pdata,
347 enum xgbe_mode mode)
348 {
349 if (mode == xgbe_cur_mode(pdata))
350 return false;
351
352 xgbe_change_mode(pdata, mode);
353
354 return true;
355 }
356
xgbe_use_mode(struct xgbe_prv_data * pdata,enum xgbe_mode mode)357 static bool xgbe_use_mode(struct xgbe_prv_data *pdata,
358 enum xgbe_mode mode)
359 {
360 return pdata->phy_if.phy_impl.use_mode(pdata, mode);
361 }
362
xgbe_an37_set(struct xgbe_prv_data * pdata,bool enable,bool restart)363 static void xgbe_an37_set(struct xgbe_prv_data *pdata, bool enable,
364 bool restart)
365 {
366 unsigned int reg;
367
368 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_CTRL1);
369 reg &= ~MDIO_VEND2_CTRL1_AN_ENABLE;
370
371 if (enable)
372 reg |= MDIO_VEND2_CTRL1_AN_ENABLE;
373
374 if (restart)
375 reg |= MDIO_VEND2_CTRL1_AN_RESTART;
376
377 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_CTRL1, reg);
378
379 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL);
380 reg |= XGBE_VEND2_MAC_AUTO_SW;
381 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_PCS_DIG_CTRL, reg);
382 }
383
xgbe_an37_restart(struct xgbe_prv_data * pdata)384 static void xgbe_an37_restart(struct xgbe_prv_data *pdata)
385 {
386 xgbe_an37_enable_interrupts(pdata);
387 xgbe_an37_set(pdata, true, true);
388
389 netif_dbg(pdata, link, pdata->netdev, "CL37 AN enabled/restarted\n");
390 }
391
xgbe_an37_disable(struct xgbe_prv_data * pdata)392 static void xgbe_an37_disable(struct xgbe_prv_data *pdata)
393 {
394 xgbe_an37_set(pdata, false, false);
395 xgbe_an37_disable_interrupts(pdata);
396
397 netif_dbg(pdata, link, pdata->netdev, "CL37 AN disabled\n");
398 }
399
xgbe_an73_set(struct xgbe_prv_data * pdata,bool enable,bool restart)400 static void xgbe_an73_set(struct xgbe_prv_data *pdata, bool enable,
401 bool restart)
402 {
403 unsigned int reg;
404
405 /* Disable KR training for now */
406 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
407 reg &= ~XGBE_KR_TRAINING_ENABLE;
408 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
409
410 /* Update AN settings */
411 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
412 reg &= ~MDIO_AN_CTRL1_ENABLE;
413
414 if (enable)
415 reg |= MDIO_AN_CTRL1_ENABLE;
416
417 if (restart)
418 reg |= MDIO_AN_CTRL1_RESTART;
419
420 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
421 }
422
xgbe_an73_restart(struct xgbe_prv_data * pdata)423 static void xgbe_an73_restart(struct xgbe_prv_data *pdata)
424 {
425 xgbe_an73_enable_interrupts(pdata);
426 xgbe_an73_set(pdata, true, true);
427
428 netif_dbg(pdata, link, pdata->netdev, "CL73 AN enabled/restarted\n");
429 }
430
xgbe_an73_disable(struct xgbe_prv_data * pdata)431 static void xgbe_an73_disable(struct xgbe_prv_data *pdata)
432 {
433 xgbe_an73_set(pdata, false, false);
434 xgbe_an73_disable_interrupts(pdata);
435
436 pdata->an_start = 0;
437
438 netif_dbg(pdata, link, pdata->netdev, "CL73 AN disabled\n");
439 }
440
xgbe_an_restart(struct xgbe_prv_data * pdata)441 static void xgbe_an_restart(struct xgbe_prv_data *pdata)
442 {
443 if (pdata->phy_if.phy_impl.an_pre)
444 pdata->phy_if.phy_impl.an_pre(pdata);
445
446 switch (pdata->an_mode) {
447 case XGBE_AN_MODE_CL73:
448 case XGBE_AN_MODE_CL73_REDRV:
449 xgbe_an73_restart(pdata);
450 break;
451 case XGBE_AN_MODE_CL37:
452 case XGBE_AN_MODE_CL37_SGMII:
453 xgbe_an37_restart(pdata);
454 break;
455 default:
456 break;
457 }
458 }
459
xgbe_an_disable(struct xgbe_prv_data * pdata)460 static void xgbe_an_disable(struct xgbe_prv_data *pdata)
461 {
462 if (pdata->phy_if.phy_impl.an_post)
463 pdata->phy_if.phy_impl.an_post(pdata);
464
465 switch (pdata->an_mode) {
466 case XGBE_AN_MODE_CL73:
467 case XGBE_AN_MODE_CL73_REDRV:
468 xgbe_an73_disable(pdata);
469 break;
470 case XGBE_AN_MODE_CL37:
471 case XGBE_AN_MODE_CL37_SGMII:
472 xgbe_an37_disable(pdata);
473 break;
474 default:
475 break;
476 }
477 }
478
xgbe_an_disable_all(struct xgbe_prv_data * pdata)479 static void xgbe_an_disable_all(struct xgbe_prv_data *pdata)
480 {
481 xgbe_an73_disable(pdata);
482 xgbe_an37_disable(pdata);
483 }
484
xgbe_an73_tx_training(struct xgbe_prv_data * pdata,enum xgbe_rx * state)485 static enum xgbe_an xgbe_an73_tx_training(struct xgbe_prv_data *pdata,
486 enum xgbe_rx *state)
487 {
488 unsigned int ad_reg, lp_reg, reg;
489
490 *state = XGBE_RX_COMPLETE;
491
492 /* If we're not in KR mode then we're done */
493 if (!xgbe_in_kr_mode(pdata))
494 return XGBE_AN_PAGE_RECEIVED;
495
496 /* Enable/Disable FEC */
497 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
498 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2);
499
500 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL);
501 reg &= ~(MDIO_PMA_10GBR_FECABLE_ABLE | MDIO_PMA_10GBR_FECABLE_ERRABLE);
502 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
503 reg |= pdata->fec_ability;
504
505 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FECCTRL, reg);
506
507 /* Start KR training */
508 if (pdata->phy_if.phy_impl.kr_training_pre)
509 pdata->phy_if.phy_impl.kr_training_pre(pdata);
510
511 reg = XMDIO_READ(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
512 reg |= XGBE_KR_TRAINING_ENABLE;
513 reg |= XGBE_KR_TRAINING_START;
514 XMDIO_WRITE(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, reg);
515 pdata->kr_start_time = jiffies;
516
517 netif_dbg(pdata, link, pdata->netdev,
518 "KR training initiated\n");
519
520 if (pdata->phy_if.phy_impl.kr_training_post)
521 pdata->phy_if.phy_impl.kr_training_post(pdata);
522
523 return XGBE_AN_PAGE_RECEIVED;
524 }
525
xgbe_an73_tx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)526 static enum xgbe_an xgbe_an73_tx_xnp(struct xgbe_prv_data *pdata,
527 enum xgbe_rx *state)
528 {
529 u16 msg;
530
531 *state = XGBE_RX_XNP;
532
533 msg = XGBE_XNP_MCF_NULL_MESSAGE;
534 msg |= XGBE_XNP_MP_FORMATTED;
535
536 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
537 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
538 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_XNP, msg);
539
540 return XGBE_AN_PAGE_RECEIVED;
541 }
542
xgbe_an73_rx_bpa(struct xgbe_prv_data * pdata,enum xgbe_rx * state)543 static enum xgbe_an xgbe_an73_rx_bpa(struct xgbe_prv_data *pdata,
544 enum xgbe_rx *state)
545 {
546 unsigned int link_support;
547 unsigned int reg, ad_reg, lp_reg;
548
549 /* Read Base Ability register 2 first */
550 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1);
551
552 /* Check for a supported mode, otherwise restart in a different one */
553 link_support = xgbe_in_kr_mode(pdata) ? 0x80 : 0x20;
554 if (!(reg & link_support))
555 return XGBE_AN_INCOMPAT_LINK;
556
557 /* Check Extended Next Page support */
558 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
559 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA);
560
561 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
562 (lp_reg & XGBE_XNP_NP_EXCHANGE))
563 ? xgbe_an73_tx_xnp(pdata, state)
564 : xgbe_an73_tx_training(pdata, state);
565 }
566
xgbe_an73_rx_xnp(struct xgbe_prv_data * pdata,enum xgbe_rx * state)567 static enum xgbe_an xgbe_an73_rx_xnp(struct xgbe_prv_data *pdata,
568 enum xgbe_rx *state)
569 {
570 unsigned int ad_reg, lp_reg;
571
572 /* Check Extended Next Page support */
573 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_XNP);
574 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPX);
575
576 return ((ad_reg & XGBE_XNP_NP_EXCHANGE) ||
577 (lp_reg & XGBE_XNP_NP_EXCHANGE))
578 ? xgbe_an73_tx_xnp(pdata, state)
579 : xgbe_an73_tx_training(pdata, state);
580 }
581
xgbe_an73_page_received(struct xgbe_prv_data * pdata)582 static enum xgbe_an xgbe_an73_page_received(struct xgbe_prv_data *pdata)
583 {
584 enum xgbe_rx *state;
585 unsigned long an_timeout;
586 enum xgbe_an ret;
587
588 if (!pdata->an_start) {
589 pdata->an_start = jiffies;
590 } else {
591 an_timeout = pdata->an_start +
592 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
593 if (time_after(jiffies, an_timeout)) {
594 /* Auto-negotiation timed out, reset state */
595 pdata->kr_state = XGBE_RX_BPA;
596 pdata->kx_state = XGBE_RX_BPA;
597
598 pdata->an_start = jiffies;
599
600 netif_dbg(pdata, link, pdata->netdev,
601 "CL73 AN timed out, resetting state\n");
602 }
603 }
604
605 state = xgbe_in_kr_mode(pdata) ? &pdata->kr_state
606 : &pdata->kx_state;
607
608 switch (*state) {
609 case XGBE_RX_BPA:
610 ret = xgbe_an73_rx_bpa(pdata, state);
611 break;
612
613 case XGBE_RX_XNP:
614 ret = xgbe_an73_rx_xnp(pdata, state);
615 break;
616
617 default:
618 ret = XGBE_AN_ERROR;
619 }
620
621 return ret;
622 }
623
xgbe_an73_incompat_link(struct xgbe_prv_data * pdata)624 static enum xgbe_an xgbe_an73_incompat_link(struct xgbe_prv_data *pdata)
625 {
626 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
627
628 /* Be sure we aren't looping trying to negotiate */
629 if (xgbe_in_kr_mode(pdata)) {
630 pdata->kr_state = XGBE_RX_ERROR;
631
632 if (!XGBE_ADV(lks, 1000baseKX_Full) &&
633 !XGBE_ADV(lks, 2500baseX_Full))
634 return XGBE_AN_NO_LINK;
635
636 if (pdata->kx_state != XGBE_RX_BPA)
637 return XGBE_AN_NO_LINK;
638 } else {
639 pdata->kx_state = XGBE_RX_ERROR;
640
641 if (!XGBE_ADV(lks, 10000baseKR_Full))
642 return XGBE_AN_NO_LINK;
643
644 if (pdata->kr_state != XGBE_RX_BPA)
645 return XGBE_AN_NO_LINK;
646 }
647
648 xgbe_an_disable(pdata);
649
650 xgbe_switch_mode(pdata);
651
652 pdata->an_result = XGBE_AN_READY;
653
654 xgbe_an_restart(pdata);
655
656 return XGBE_AN_INCOMPAT_LINK;
657 }
658
xgbe_an37_isr(struct xgbe_prv_data * pdata)659 static void xgbe_an37_isr(struct xgbe_prv_data *pdata)
660 {
661 unsigned int reg;
662
663 /* Disable AN interrupts */
664 xgbe_an37_disable_interrupts(pdata);
665
666 /* Save the interrupt(s) that fired */
667 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT);
668 pdata->an_int = reg & XGBE_AN_CL37_INT_MASK;
669 pdata->an_status = reg & ~XGBE_AN_CL37_INT_MASK;
670
671 if (pdata->an_int) {
672 /* Clear the interrupt(s) that fired and process them */
673 reg &= ~XGBE_AN_CL37_INT_MASK;
674 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_STAT, reg);
675
676 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
677 } else {
678 /* Enable AN interrupts */
679 xgbe_an37_enable_interrupts(pdata);
680
681 /* Reissue interrupt if status is not clear */
682 if (pdata->vdata->irq_reissue_support)
683 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
684 }
685 }
686
xgbe_an73_isr(struct xgbe_prv_data * pdata)687 static void xgbe_an73_isr(struct xgbe_prv_data *pdata)
688 {
689 /* Disable AN interrupts */
690 xgbe_an73_disable_interrupts(pdata);
691
692 /* Save the interrupt(s) that fired */
693 pdata->an_int = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_INT);
694
695 if (pdata->an_int) {
696 /* Clear the interrupt(s) that fired and process them */
697 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_INT, ~pdata->an_int);
698
699 queue_work(pdata->an_workqueue, &pdata->an_irq_work);
700 } else {
701 /* Enable AN interrupts */
702 xgbe_an73_enable_interrupts(pdata);
703
704 /* Reissue interrupt if status is not clear */
705 if (pdata->vdata->irq_reissue_support)
706 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
707 }
708 }
709
xgbe_an_isr_task(struct tasklet_struct * t)710 static void xgbe_an_isr_task(struct tasklet_struct *t)
711 {
712 struct xgbe_prv_data *pdata = from_tasklet(pdata, t, tasklet_an);
713
714 netif_dbg(pdata, intr, pdata->netdev, "AN interrupt received\n");
715
716 switch (pdata->an_mode) {
717 case XGBE_AN_MODE_CL73:
718 case XGBE_AN_MODE_CL73_REDRV:
719 xgbe_an73_isr(pdata);
720 break;
721 case XGBE_AN_MODE_CL37:
722 case XGBE_AN_MODE_CL37_SGMII:
723 xgbe_an37_isr(pdata);
724 break;
725 default:
726 break;
727 }
728 }
729
xgbe_an_isr(int irq,void * data)730 static irqreturn_t xgbe_an_isr(int irq, void *data)
731 {
732 struct xgbe_prv_data *pdata = (struct xgbe_prv_data *)data;
733
734 if (pdata->isr_as_tasklet)
735 tasklet_schedule(&pdata->tasklet_an);
736 else
737 xgbe_an_isr_task(&pdata->tasklet_an);
738
739 return IRQ_HANDLED;
740 }
741
xgbe_an_combined_isr(struct xgbe_prv_data * pdata)742 static irqreturn_t xgbe_an_combined_isr(struct xgbe_prv_data *pdata)
743 {
744 xgbe_an_isr_task(&pdata->tasklet_an);
745
746 return IRQ_HANDLED;
747 }
748
xgbe_an_irq_work(struct work_struct * work)749 static void xgbe_an_irq_work(struct work_struct *work)
750 {
751 struct xgbe_prv_data *pdata = container_of(work,
752 struct xgbe_prv_data,
753 an_irq_work);
754
755 /* Avoid a race between enabling the IRQ and exiting the work by
756 * waiting for the work to finish and then queueing it
757 */
758 flush_work(&pdata->an_work);
759 queue_work(pdata->an_workqueue, &pdata->an_work);
760 }
761
xgbe_state_as_string(enum xgbe_an state)762 static const char *xgbe_state_as_string(enum xgbe_an state)
763 {
764 switch (state) {
765 case XGBE_AN_READY:
766 return "Ready";
767 case XGBE_AN_PAGE_RECEIVED:
768 return "Page-Received";
769 case XGBE_AN_INCOMPAT_LINK:
770 return "Incompatible-Link";
771 case XGBE_AN_COMPLETE:
772 return "Complete";
773 case XGBE_AN_NO_LINK:
774 return "No-Link";
775 case XGBE_AN_ERROR:
776 return "Error";
777 default:
778 return "Undefined";
779 }
780 }
781
xgbe_an37_state_machine(struct xgbe_prv_data * pdata)782 static void xgbe_an37_state_machine(struct xgbe_prv_data *pdata)
783 {
784 enum xgbe_an cur_state = pdata->an_state;
785
786 if (!pdata->an_int)
787 return;
788
789 if (pdata->an_int & XGBE_AN_CL37_INT_CMPLT) {
790 pdata->an_state = XGBE_AN_COMPLETE;
791 pdata->an_int &= ~XGBE_AN_CL37_INT_CMPLT;
792
793 /* If SGMII is enabled, check the link status */
794 if ((pdata->an_mode == XGBE_AN_MODE_CL37_SGMII) &&
795 !(pdata->an_status & XGBE_SGMII_AN_LINK_STATUS))
796 pdata->an_state = XGBE_AN_NO_LINK;
797 }
798
799 netif_dbg(pdata, link, pdata->netdev, "CL37 AN %s\n",
800 xgbe_state_as_string(pdata->an_state));
801
802 cur_state = pdata->an_state;
803
804 switch (pdata->an_state) {
805 case XGBE_AN_READY:
806 break;
807
808 case XGBE_AN_COMPLETE:
809 netif_dbg(pdata, link, pdata->netdev,
810 "Auto negotiation successful\n");
811 break;
812
813 case XGBE_AN_NO_LINK:
814 break;
815
816 default:
817 pdata->an_state = XGBE_AN_ERROR;
818 }
819
820 if (pdata->an_state == XGBE_AN_ERROR) {
821 netdev_err(pdata->netdev,
822 "error during auto-negotiation, state=%u\n",
823 cur_state);
824
825 pdata->an_int = 0;
826 xgbe_an37_clear_interrupts(pdata);
827 }
828
829 if (pdata->an_state >= XGBE_AN_COMPLETE) {
830 pdata->an_result = pdata->an_state;
831 pdata->an_state = XGBE_AN_READY;
832
833 if (pdata->phy_if.phy_impl.an_post)
834 pdata->phy_if.phy_impl.an_post(pdata);
835
836 netif_dbg(pdata, link, pdata->netdev, "CL37 AN result: %s\n",
837 xgbe_state_as_string(pdata->an_result));
838 }
839
840 xgbe_an37_enable_interrupts(pdata);
841 }
842
xgbe_an73_state_machine(struct xgbe_prv_data * pdata)843 static void xgbe_an73_state_machine(struct xgbe_prv_data *pdata)
844 {
845 enum xgbe_an cur_state = pdata->an_state;
846
847 if (!pdata->an_int)
848 return;
849
850 next_int:
851 if (pdata->an_int & XGBE_AN_CL73_PG_RCV) {
852 pdata->an_state = XGBE_AN_PAGE_RECEIVED;
853 pdata->an_int &= ~XGBE_AN_CL73_PG_RCV;
854 } else if (pdata->an_int & XGBE_AN_CL73_INC_LINK) {
855 pdata->an_state = XGBE_AN_INCOMPAT_LINK;
856 pdata->an_int &= ~XGBE_AN_CL73_INC_LINK;
857 } else if (pdata->an_int & XGBE_AN_CL73_INT_CMPLT) {
858 pdata->an_state = XGBE_AN_COMPLETE;
859 pdata->an_int &= ~XGBE_AN_CL73_INT_CMPLT;
860 } else {
861 pdata->an_state = XGBE_AN_ERROR;
862 }
863
864 again:
865 netif_dbg(pdata, link, pdata->netdev, "CL73 AN %s\n",
866 xgbe_state_as_string(pdata->an_state));
867
868 cur_state = pdata->an_state;
869
870 switch (pdata->an_state) {
871 case XGBE_AN_READY:
872 pdata->an_supported = 0;
873 break;
874
875 case XGBE_AN_PAGE_RECEIVED:
876 pdata->an_state = xgbe_an73_page_received(pdata);
877 pdata->an_supported++;
878 break;
879
880 case XGBE_AN_INCOMPAT_LINK:
881 pdata->an_supported = 0;
882 pdata->parallel_detect = 0;
883 pdata->an_state = xgbe_an73_incompat_link(pdata);
884 break;
885
886 case XGBE_AN_COMPLETE:
887 pdata->parallel_detect = pdata->an_supported ? 0 : 1;
888 netif_dbg(pdata, link, pdata->netdev, "%s successful\n",
889 pdata->an_supported ? "Auto negotiation"
890 : "Parallel detection");
891 break;
892
893 case XGBE_AN_NO_LINK:
894 break;
895
896 default:
897 pdata->an_state = XGBE_AN_ERROR;
898 }
899
900 if (pdata->an_state == XGBE_AN_NO_LINK) {
901 pdata->an_int = 0;
902 xgbe_an73_clear_interrupts(pdata);
903 } else if (pdata->an_state == XGBE_AN_ERROR) {
904 netdev_err(pdata->netdev,
905 "error during auto-negotiation, state=%u\n",
906 cur_state);
907
908 pdata->an_int = 0;
909 xgbe_an73_clear_interrupts(pdata);
910 }
911
912 if (pdata->an_state >= XGBE_AN_COMPLETE) {
913 pdata->an_result = pdata->an_state;
914 pdata->an_state = XGBE_AN_READY;
915 pdata->kr_state = XGBE_RX_BPA;
916 pdata->kx_state = XGBE_RX_BPA;
917 pdata->an_start = 0;
918
919 if (pdata->phy_if.phy_impl.an_post)
920 pdata->phy_if.phy_impl.an_post(pdata);
921
922 netif_dbg(pdata, link, pdata->netdev, "CL73 AN result: %s\n",
923 xgbe_state_as_string(pdata->an_result));
924 }
925
926 if (cur_state != pdata->an_state)
927 goto again;
928
929 if (pdata->an_int)
930 goto next_int;
931
932 xgbe_an73_enable_interrupts(pdata);
933 }
934
xgbe_an_state_machine(struct work_struct * work)935 static void xgbe_an_state_machine(struct work_struct *work)
936 {
937 struct xgbe_prv_data *pdata = container_of(work,
938 struct xgbe_prv_data,
939 an_work);
940
941 mutex_lock(&pdata->an_mutex);
942
943 switch (pdata->an_mode) {
944 case XGBE_AN_MODE_CL73:
945 case XGBE_AN_MODE_CL73_REDRV:
946 xgbe_an73_state_machine(pdata);
947 break;
948 case XGBE_AN_MODE_CL37:
949 case XGBE_AN_MODE_CL37_SGMII:
950 xgbe_an37_state_machine(pdata);
951 break;
952 default:
953 break;
954 }
955
956 /* Reissue interrupt if status is not clear */
957 if (pdata->vdata->irq_reissue_support)
958 XP_IOWRITE(pdata, XP_INT_REISSUE_EN, 1 << 3);
959
960 mutex_unlock(&pdata->an_mutex);
961 }
962
xgbe_an37_init(struct xgbe_prv_data * pdata)963 static void xgbe_an37_init(struct xgbe_prv_data *pdata)
964 {
965 struct ethtool_link_ksettings lks;
966 unsigned int reg;
967
968 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
969
970 /* Set up Advertisement register */
971 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE);
972 if (XGBE_ADV(&lks, Pause))
973 reg |= 0x100;
974 else
975 reg &= ~0x100;
976
977 if (XGBE_ADV(&lks, Asym_Pause))
978 reg |= 0x80;
979 else
980 reg &= ~0x80;
981
982 /* Full duplex, but not half */
983 reg |= XGBE_AN_CL37_FD_MASK;
984 reg &= ~XGBE_AN_CL37_HD_MASK;
985
986 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_ADVERTISE, reg);
987
988 /* Set up the Control register */
989 reg = XMDIO_READ(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL);
990 reg &= ~XGBE_AN_CL37_TX_CONFIG_MASK;
991 reg &= ~XGBE_AN_CL37_PCS_MODE_MASK;
992
993 switch (pdata->an_mode) {
994 case XGBE_AN_MODE_CL37:
995 reg |= XGBE_AN_CL37_PCS_MODE_BASEX;
996 break;
997 case XGBE_AN_MODE_CL37_SGMII:
998 reg |= XGBE_AN_CL37_PCS_MODE_SGMII;
999 break;
1000 default:
1001 break;
1002 }
1003
1004 reg |= XGBE_AN_CL37_MII_CTRL_8BIT;
1005
1006 XMDIO_WRITE(pdata, MDIO_MMD_VEND2, MDIO_VEND2_AN_CTRL, reg);
1007
1008 netif_dbg(pdata, link, pdata->netdev, "CL37 AN (%s) initialized\n",
1009 (pdata->an_mode == XGBE_AN_MODE_CL37) ? "BaseX" : "SGMII");
1010
1011 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1);
1012 reg &= ~MDIO_AN_CTRL1_ENABLE;
1013 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_CTRL1, reg);
1014
1015 }
1016
xgbe_an73_init(struct xgbe_prv_data * pdata)1017 static void xgbe_an73_init(struct xgbe_prv_data *pdata)
1018 {
1019 struct ethtool_link_ksettings lks;
1020 unsigned int reg;
1021
1022 pdata->phy_if.phy_impl.an_advertising(pdata, &lks);
1023
1024 /* Set up Advertisement register 3 first */
1025 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
1026 if (XGBE_ADV(&lks, 10000baseR_FEC))
1027 reg |= 0xc000;
1028 else
1029 reg &= ~0xc000;
1030
1031 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, reg);
1032
1033 /* Set up Advertisement register 2 next */
1034 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
1035 if (XGBE_ADV(&lks, 10000baseKR_Full))
1036 reg |= 0x80;
1037 else
1038 reg &= ~0x80;
1039
1040 if (XGBE_ADV(&lks, 1000baseKX_Full) ||
1041 XGBE_ADV(&lks, 2500baseX_Full))
1042 reg |= 0x20;
1043 else
1044 reg &= ~0x20;
1045
1046 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, reg);
1047
1048 /* Set up Advertisement register 1 last */
1049 reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1050 if (XGBE_ADV(&lks, Pause))
1051 reg |= 0x400;
1052 else
1053 reg &= ~0x400;
1054
1055 if (XGBE_ADV(&lks, Asym_Pause))
1056 reg |= 0x800;
1057 else
1058 reg &= ~0x800;
1059
1060 /* We don't intend to perform XNP */
1061 reg &= ~XGBE_XNP_NP_EXCHANGE;
1062
1063 XMDIO_WRITE(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE, reg);
1064
1065 netif_dbg(pdata, link, pdata->netdev, "CL73 AN initialized\n");
1066 }
1067
xgbe_an_init(struct xgbe_prv_data * pdata)1068 static void xgbe_an_init(struct xgbe_prv_data *pdata)
1069 {
1070 /* Set up advertisement registers based on current settings */
1071 pdata->an_mode = pdata->phy_if.phy_impl.an_mode(pdata);
1072 switch (pdata->an_mode) {
1073 case XGBE_AN_MODE_CL73:
1074 case XGBE_AN_MODE_CL73_REDRV:
1075 xgbe_an73_init(pdata);
1076 break;
1077 case XGBE_AN_MODE_CL37:
1078 case XGBE_AN_MODE_CL37_SGMII:
1079 xgbe_an37_init(pdata);
1080 break;
1081 default:
1082 break;
1083 }
1084 }
1085
xgbe_phy_fc_string(struct xgbe_prv_data * pdata)1086 static const char *xgbe_phy_fc_string(struct xgbe_prv_data *pdata)
1087 {
1088 if (pdata->tx_pause && pdata->rx_pause)
1089 return "rx/tx";
1090 else if (pdata->rx_pause)
1091 return "rx";
1092 else if (pdata->tx_pause)
1093 return "tx";
1094 else
1095 return "off";
1096 }
1097
xgbe_phy_speed_string(int speed)1098 static const char *xgbe_phy_speed_string(int speed)
1099 {
1100 switch (speed) {
1101 case SPEED_10:
1102 return "10Mbps";
1103 case SPEED_100:
1104 return "100Mbps";
1105 case SPEED_1000:
1106 return "1Gbps";
1107 case SPEED_2500:
1108 return "2.5Gbps";
1109 case SPEED_10000:
1110 return "10Gbps";
1111 case SPEED_UNKNOWN:
1112 return "Unknown";
1113 default:
1114 return "Unsupported";
1115 }
1116 }
1117
xgbe_phy_print_status(struct xgbe_prv_data * pdata)1118 static void xgbe_phy_print_status(struct xgbe_prv_data *pdata)
1119 {
1120 if (pdata->phy.link)
1121 netdev_info(pdata->netdev,
1122 "Link is Up - %s/%s - flow control %s\n",
1123 xgbe_phy_speed_string(pdata->phy.speed),
1124 pdata->phy.duplex == DUPLEX_FULL ? "Full" : "Half",
1125 xgbe_phy_fc_string(pdata));
1126 else
1127 netdev_info(pdata->netdev, "Link is Down\n");
1128 }
1129
xgbe_phy_adjust_link(struct xgbe_prv_data * pdata)1130 static void xgbe_phy_adjust_link(struct xgbe_prv_data *pdata)
1131 {
1132 int new_state = 0;
1133
1134 if (pdata->phy.link) {
1135 /* Flow control support */
1136 pdata->pause_autoneg = pdata->phy.pause_autoneg;
1137
1138 if (pdata->tx_pause != pdata->phy.tx_pause) {
1139 new_state = 1;
1140 pdata->tx_pause = pdata->phy.tx_pause;
1141 pdata->hw_if.config_tx_flow_control(pdata);
1142 }
1143
1144 if (pdata->rx_pause != pdata->phy.rx_pause) {
1145 new_state = 1;
1146 pdata->rx_pause = pdata->phy.rx_pause;
1147 pdata->hw_if.config_rx_flow_control(pdata);
1148 }
1149
1150 /* Speed support */
1151 if (pdata->phy_speed != pdata->phy.speed) {
1152 new_state = 1;
1153 pdata->phy_speed = pdata->phy.speed;
1154 }
1155
1156 if (pdata->phy_link != pdata->phy.link) {
1157 new_state = 1;
1158 pdata->phy_link = pdata->phy.link;
1159 }
1160 } else if (pdata->phy_link) {
1161 new_state = 1;
1162 pdata->phy_link = 0;
1163 pdata->phy_speed = SPEED_UNKNOWN;
1164 }
1165
1166 if (new_state && netif_msg_link(pdata))
1167 xgbe_phy_print_status(pdata);
1168 }
1169
xgbe_phy_valid_speed(struct xgbe_prv_data * pdata,int speed)1170 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed)
1171 {
1172 return pdata->phy_if.phy_impl.valid_speed(pdata, speed);
1173 }
1174
xgbe_phy_config_fixed(struct xgbe_prv_data * pdata)1175 static int xgbe_phy_config_fixed(struct xgbe_prv_data *pdata)
1176 {
1177 enum xgbe_mode mode;
1178
1179 netif_dbg(pdata, link, pdata->netdev, "fixed PHY configuration\n");
1180
1181 /* Disable auto-negotiation */
1182 xgbe_an_disable(pdata);
1183
1184 /* Set specified mode for specified speed */
1185 mode = pdata->phy_if.phy_impl.get_mode(pdata, pdata->phy.speed);
1186 switch (mode) {
1187 case XGBE_MODE_KX_1000:
1188 case XGBE_MODE_KX_2500:
1189 case XGBE_MODE_KR:
1190 case XGBE_MODE_SGMII_10:
1191 case XGBE_MODE_SGMII_100:
1192 case XGBE_MODE_SGMII_1000:
1193 case XGBE_MODE_X:
1194 case XGBE_MODE_SFI:
1195 break;
1196 case XGBE_MODE_UNKNOWN:
1197 default:
1198 return -EINVAL;
1199 }
1200
1201 /* Validate duplex mode */
1202 if (pdata->phy.duplex != DUPLEX_FULL)
1203 return -EINVAL;
1204
1205 /* Force the mode change for SFI in Fixed PHY config.
1206 * Fixed PHY configs needs PLL to be enabled while doing mode set.
1207 * When the SFP module isn't connected during boot, driver assumes
1208 * AN is ON and attempts autonegotiation. However, if the connected
1209 * SFP comes up in Fixed PHY config, the link will not come up as
1210 * PLL isn't enabled while the initial mode set command is issued.
1211 * So, force the mode change for SFI in Fixed PHY configuration to
1212 * fix link issues.
1213 */
1214 if (mode == XGBE_MODE_SFI)
1215 xgbe_change_mode(pdata, mode);
1216 else
1217 xgbe_set_mode(pdata, mode);
1218
1219 return 0;
1220 }
1221
__xgbe_phy_config_aneg(struct xgbe_prv_data * pdata,bool set_mode)1222 static int __xgbe_phy_config_aneg(struct xgbe_prv_data *pdata, bool set_mode)
1223 {
1224 int ret;
1225
1226 mutex_lock(&pdata->an_mutex);
1227
1228 set_bit(XGBE_LINK_INIT, &pdata->dev_state);
1229 pdata->link_check = jiffies;
1230
1231 ret = pdata->phy_if.phy_impl.an_config(pdata);
1232 if (ret)
1233 goto out;
1234
1235 if (pdata->phy.autoneg != AUTONEG_ENABLE) {
1236 ret = xgbe_phy_config_fixed(pdata);
1237 if (ret || !pdata->kr_redrv)
1238 goto out;
1239
1240 netif_dbg(pdata, link, pdata->netdev, "AN redriver support\n");
1241 } else {
1242 netif_dbg(pdata, link, pdata->netdev, "AN PHY configuration\n");
1243 }
1244
1245 /* Disable auto-negotiation interrupt */
1246 disable_irq(pdata->an_irq);
1247
1248 if (set_mode) {
1249 /* Start auto-negotiation in a supported mode */
1250 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1251 xgbe_set_mode(pdata, XGBE_MODE_KR);
1252 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1253 xgbe_set_mode(pdata, XGBE_MODE_KX_2500);
1254 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1255 xgbe_set_mode(pdata, XGBE_MODE_KX_1000);
1256 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1257 xgbe_set_mode(pdata, XGBE_MODE_SFI);
1258 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1259 xgbe_set_mode(pdata, XGBE_MODE_X);
1260 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1261 xgbe_set_mode(pdata, XGBE_MODE_SGMII_1000);
1262 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1263 xgbe_set_mode(pdata, XGBE_MODE_SGMII_100);
1264 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1265 xgbe_set_mode(pdata, XGBE_MODE_SGMII_10);
1266 } else {
1267 enable_irq(pdata->an_irq);
1268 ret = -EINVAL;
1269 goto out;
1270 }
1271 }
1272
1273 /* Disable and stop any in progress auto-negotiation */
1274 xgbe_an_disable_all(pdata);
1275
1276 /* Clear any auto-negotitation interrupts */
1277 xgbe_an_clear_interrupts_all(pdata);
1278
1279 pdata->an_result = XGBE_AN_READY;
1280 pdata->an_state = XGBE_AN_READY;
1281 pdata->kr_state = XGBE_RX_BPA;
1282 pdata->kx_state = XGBE_RX_BPA;
1283
1284 /* Re-enable auto-negotiation interrupt */
1285 enable_irq(pdata->an_irq);
1286
1287 xgbe_an_init(pdata);
1288 xgbe_an_restart(pdata);
1289
1290 out:
1291 if (ret)
1292 set_bit(XGBE_LINK_ERR, &pdata->dev_state);
1293 else
1294 clear_bit(XGBE_LINK_ERR, &pdata->dev_state);
1295
1296 mutex_unlock(&pdata->an_mutex);
1297
1298 return ret;
1299 }
1300
xgbe_phy_config_aneg(struct xgbe_prv_data * pdata)1301 static int xgbe_phy_config_aneg(struct xgbe_prv_data *pdata)
1302 {
1303 return __xgbe_phy_config_aneg(pdata, true);
1304 }
1305
xgbe_phy_reconfig_aneg(struct xgbe_prv_data * pdata)1306 static int xgbe_phy_reconfig_aneg(struct xgbe_prv_data *pdata)
1307 {
1308 return __xgbe_phy_config_aneg(pdata, false);
1309 }
1310
xgbe_phy_aneg_done(struct xgbe_prv_data * pdata)1311 static bool xgbe_phy_aneg_done(struct xgbe_prv_data *pdata)
1312 {
1313 return (pdata->an_result == XGBE_AN_COMPLETE);
1314 }
1315
xgbe_check_link_timeout(struct xgbe_prv_data * pdata)1316 static void xgbe_check_link_timeout(struct xgbe_prv_data *pdata)
1317 {
1318 unsigned long link_timeout;
1319 unsigned long kr_time;
1320 int wait;
1321
1322 link_timeout = pdata->link_check + (XGBE_LINK_TIMEOUT * HZ);
1323 if (time_after(jiffies, link_timeout)) {
1324 if ((xgbe_cur_mode(pdata) == XGBE_MODE_KR) &&
1325 pdata->phy.autoneg == AUTONEG_ENABLE) {
1326 /* AN restart should not happen while KR training is in progress.
1327 * The while loop ensures no AN restart during KR training,
1328 * waits up to 500ms and AN restart is triggered only if KR
1329 * training is failed.
1330 */
1331 wait = XGBE_KR_TRAINING_WAIT_ITER;
1332 while (wait--) {
1333 kr_time = pdata->kr_start_time +
1334 msecs_to_jiffies(XGBE_AN_MS_TIMEOUT);
1335 if (time_after(jiffies, kr_time))
1336 break;
1337 /* AN restart is not required, if AN result is COMPLETE */
1338 if (pdata->an_result == XGBE_AN_COMPLETE)
1339 return;
1340 usleep_range(10000, 11000);
1341 }
1342 }
1343 netif_dbg(pdata, link, pdata->netdev, "AN link timeout\n");
1344 xgbe_phy_config_aneg(pdata);
1345 }
1346 }
1347
xgbe_phy_status_aneg(struct xgbe_prv_data * pdata)1348 static enum xgbe_mode xgbe_phy_status_aneg(struct xgbe_prv_data *pdata)
1349 {
1350 return pdata->phy_if.phy_impl.an_outcome(pdata);
1351 }
1352
xgbe_phy_status_result(struct xgbe_prv_data * pdata)1353 static bool xgbe_phy_status_result(struct xgbe_prv_data *pdata)
1354 {
1355 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1356 enum xgbe_mode mode;
1357
1358 XGBE_ZERO_LP_ADV(lks);
1359
1360 if ((pdata->phy.autoneg != AUTONEG_ENABLE) || pdata->parallel_detect)
1361 mode = xgbe_cur_mode(pdata);
1362 else
1363 mode = xgbe_phy_status_aneg(pdata);
1364
1365 switch (mode) {
1366 case XGBE_MODE_SGMII_10:
1367 pdata->phy.speed = SPEED_10;
1368 break;
1369 case XGBE_MODE_SGMII_100:
1370 pdata->phy.speed = SPEED_100;
1371 break;
1372 case XGBE_MODE_X:
1373 case XGBE_MODE_KX_1000:
1374 case XGBE_MODE_SGMII_1000:
1375 pdata->phy.speed = SPEED_1000;
1376 break;
1377 case XGBE_MODE_KX_2500:
1378 pdata->phy.speed = SPEED_2500;
1379 break;
1380 case XGBE_MODE_KR:
1381 case XGBE_MODE_SFI:
1382 pdata->phy.speed = SPEED_10000;
1383 break;
1384 case XGBE_MODE_UNKNOWN:
1385 default:
1386 pdata->phy.speed = SPEED_UNKNOWN;
1387 }
1388
1389 pdata->phy.duplex = DUPLEX_FULL;
1390
1391 if (!xgbe_set_mode(pdata, mode))
1392 return false;
1393
1394 if (pdata->an_again)
1395 xgbe_phy_reconfig_aneg(pdata);
1396
1397 return true;
1398 }
1399
xgbe_phy_status(struct xgbe_prv_data * pdata)1400 static void xgbe_phy_status(struct xgbe_prv_data *pdata)
1401 {
1402 unsigned int link_aneg;
1403 int an_restart;
1404
1405 if (test_bit(XGBE_LINK_ERR, &pdata->dev_state)) {
1406 netif_carrier_off(pdata->netdev);
1407
1408 pdata->phy.link = 0;
1409 goto adjust_link;
1410 }
1411
1412 link_aneg = (pdata->phy.autoneg == AUTONEG_ENABLE);
1413
1414 pdata->phy.link = pdata->phy_if.phy_impl.link_status(pdata,
1415 &an_restart);
1416 /* bail out if the link status register read fails */
1417 if (pdata->phy.link < 0)
1418 return;
1419
1420 if (an_restart) {
1421 xgbe_phy_config_aneg(pdata);
1422 goto adjust_link;
1423 }
1424
1425 if (pdata->phy.link) {
1426 if (link_aneg && !xgbe_phy_aneg_done(pdata)) {
1427 xgbe_check_link_timeout(pdata);
1428 return;
1429 }
1430
1431 if (xgbe_phy_status_result(pdata))
1432 return;
1433
1434 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state))
1435 clear_bit(XGBE_LINK_INIT, &pdata->dev_state);
1436
1437 netif_carrier_on(pdata->netdev);
1438 } else {
1439 if (test_bit(XGBE_LINK_INIT, &pdata->dev_state)) {
1440 xgbe_check_link_timeout(pdata);
1441
1442 if (link_aneg)
1443 return;
1444 }
1445
1446 xgbe_phy_status_result(pdata);
1447
1448 netif_carrier_off(pdata->netdev);
1449 }
1450
1451 adjust_link:
1452 xgbe_phy_adjust_link(pdata);
1453 }
1454
xgbe_phy_stop(struct xgbe_prv_data * pdata)1455 static void xgbe_phy_stop(struct xgbe_prv_data *pdata)
1456 {
1457 netif_dbg(pdata, link, pdata->netdev, "stopping PHY\n");
1458
1459 if (!pdata->phy_started)
1460 return;
1461
1462 /* Indicate the PHY is down */
1463 pdata->phy_started = 0;
1464
1465 /* Disable auto-negotiation */
1466 xgbe_an_disable_all(pdata);
1467
1468 if (pdata->dev_irq != pdata->an_irq) {
1469 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1470 tasklet_kill(&pdata->tasklet_an);
1471 }
1472
1473 pdata->phy_if.phy_impl.stop(pdata);
1474
1475 pdata->phy.link = 0;
1476
1477 xgbe_phy_adjust_link(pdata);
1478 }
1479
xgbe_phy_start(struct xgbe_prv_data * pdata)1480 static int xgbe_phy_start(struct xgbe_prv_data *pdata)
1481 {
1482 struct net_device *netdev = pdata->netdev;
1483 int ret;
1484
1485 netif_dbg(pdata, link, pdata->netdev, "starting PHY\n");
1486
1487 ret = pdata->phy_if.phy_impl.start(pdata);
1488 if (ret)
1489 return ret;
1490
1491 /* If we have a separate AN irq, enable it */
1492 if (pdata->dev_irq != pdata->an_irq) {
1493 tasklet_setup(&pdata->tasklet_an, xgbe_an_isr_task);
1494
1495 ret = devm_request_irq(pdata->dev, pdata->an_irq,
1496 xgbe_an_isr, 0, pdata->an_name,
1497 pdata);
1498 if (ret) {
1499 netdev_err(netdev, "phy irq request failed\n");
1500 goto err_stop;
1501 }
1502 }
1503
1504 /* Set initial mode - call the mode setting routines
1505 * directly to insure we are properly configured
1506 */
1507 if (xgbe_use_mode(pdata, XGBE_MODE_KR)) {
1508 xgbe_kr_mode(pdata);
1509 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_2500)) {
1510 xgbe_kx_2500_mode(pdata);
1511 } else if (xgbe_use_mode(pdata, XGBE_MODE_KX_1000)) {
1512 xgbe_kx_1000_mode(pdata);
1513 } else if (xgbe_use_mode(pdata, XGBE_MODE_SFI)) {
1514 xgbe_sfi_mode(pdata);
1515 } else if (xgbe_use_mode(pdata, XGBE_MODE_X)) {
1516 xgbe_x_mode(pdata);
1517 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_1000)) {
1518 xgbe_sgmii_1000_mode(pdata);
1519 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_100)) {
1520 xgbe_sgmii_100_mode(pdata);
1521 } else if (xgbe_use_mode(pdata, XGBE_MODE_SGMII_10)) {
1522 xgbe_sgmii_10_mode(pdata);
1523 } else {
1524 ret = -EINVAL;
1525 goto err_irq;
1526 }
1527
1528 /* Indicate the PHY is up and running */
1529 pdata->phy_started = 1;
1530
1531 xgbe_an_init(pdata);
1532 xgbe_an_enable_interrupts(pdata);
1533
1534 return xgbe_phy_config_aneg(pdata);
1535
1536 err_irq:
1537 if (pdata->dev_irq != pdata->an_irq)
1538 devm_free_irq(pdata->dev, pdata->an_irq, pdata);
1539
1540 err_stop:
1541 pdata->phy_if.phy_impl.stop(pdata);
1542
1543 return ret;
1544 }
1545
xgbe_phy_reset(struct xgbe_prv_data * pdata)1546 static int xgbe_phy_reset(struct xgbe_prv_data *pdata)
1547 {
1548 int ret;
1549
1550 ret = pdata->phy_if.phy_impl.reset(pdata);
1551 if (ret)
1552 return ret;
1553
1554 /* Disable auto-negotiation for now */
1555 xgbe_an_disable_all(pdata);
1556
1557 /* Clear auto-negotiation interrupts */
1558 xgbe_an_clear_interrupts_all(pdata);
1559
1560 return 0;
1561 }
1562
xgbe_dump_phy_registers(struct xgbe_prv_data * pdata)1563 static void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
1564 {
1565 struct device *dev = pdata->dev;
1566
1567 dev_dbg(dev, "\n************* PHY Reg dump **********************\n");
1568
1569 dev_dbg(dev, "PCS Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1570 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
1571 dev_dbg(dev, "PCS Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1572 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
1573 dev_dbg(dev, "Phy Id (PHYS ID 1 %#06x)= %#06x\n", MDIO_DEVID1,
1574 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
1575 dev_dbg(dev, "Phy Id (PHYS ID 2 %#06x)= %#06x\n", MDIO_DEVID2,
1576 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
1577 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS1,
1578 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
1579 dev_dbg(dev, "Devices in Package (%#06x)= %#06x\n", MDIO_DEVS2,
1580 XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
1581
1582 dev_dbg(dev, "Auto-Neg Control Reg (%#06x) = %#06x\n", MDIO_CTRL1,
1583 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
1584 dev_dbg(dev, "Auto-Neg Status Reg (%#06x) = %#06x\n", MDIO_STAT1,
1585 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
1586 dev_dbg(dev, "Auto-Neg Ad Reg 1 (%#06x) = %#06x\n",
1587 MDIO_AN_ADVERTISE,
1588 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
1589 dev_dbg(dev, "Auto-Neg Ad Reg 2 (%#06x) = %#06x\n",
1590 MDIO_AN_ADVERTISE + 1,
1591 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
1592 dev_dbg(dev, "Auto-Neg Ad Reg 3 (%#06x) = %#06x\n",
1593 MDIO_AN_ADVERTISE + 2,
1594 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
1595 dev_dbg(dev, "Auto-Neg Completion Reg (%#06x) = %#06x\n",
1596 MDIO_AN_COMP_STAT,
1597 XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
1598
1599 dev_dbg(dev, "\n*************************************************\n");
1600 }
1601
xgbe_phy_best_advertised_speed(struct xgbe_prv_data * pdata)1602 static int xgbe_phy_best_advertised_speed(struct xgbe_prv_data *pdata)
1603 {
1604 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1605
1606 if (XGBE_ADV(lks, 10000baseKR_Full))
1607 return SPEED_10000;
1608 else if (XGBE_ADV(lks, 10000baseT_Full))
1609 return SPEED_10000;
1610 else if (XGBE_ADV(lks, 2500baseX_Full))
1611 return SPEED_2500;
1612 else if (XGBE_ADV(lks, 2500baseT_Full))
1613 return SPEED_2500;
1614 else if (XGBE_ADV(lks, 1000baseKX_Full))
1615 return SPEED_1000;
1616 else if (XGBE_ADV(lks, 1000baseT_Full))
1617 return SPEED_1000;
1618 else if (XGBE_ADV(lks, 100baseT_Full))
1619 return SPEED_100;
1620 else if (XGBE_ADV(lks, 10baseT_Full))
1621 return SPEED_10;
1622
1623 return SPEED_UNKNOWN;
1624 }
1625
xgbe_phy_exit(struct xgbe_prv_data * pdata)1626 static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
1627 {
1628 pdata->phy_if.phy_impl.exit(pdata);
1629 }
1630
xgbe_phy_init(struct xgbe_prv_data * pdata)1631 static int xgbe_phy_init(struct xgbe_prv_data *pdata)
1632 {
1633 struct ethtool_link_ksettings *lks = &pdata->phy.lks;
1634 int ret;
1635
1636 mutex_init(&pdata->an_mutex);
1637 INIT_WORK(&pdata->an_irq_work, xgbe_an_irq_work);
1638 INIT_WORK(&pdata->an_work, xgbe_an_state_machine);
1639 pdata->mdio_mmd = MDIO_MMD_PCS;
1640
1641 /* Check for FEC support */
1642 pdata->fec_ability = XMDIO_READ(pdata, MDIO_MMD_PMAPMD,
1643 MDIO_PMA_10GBR_FECABLE);
1644 pdata->fec_ability &= (MDIO_PMA_10GBR_FECABLE_ABLE |
1645 MDIO_PMA_10GBR_FECABLE_ERRABLE);
1646
1647 /* Setup the phy (including supported features) */
1648 ret = pdata->phy_if.phy_impl.init(pdata);
1649 if (ret)
1650 return ret;
1651
1652 /* Copy supported link modes to advertising link modes */
1653 XGBE_LM_COPY(lks, advertising, lks, supported);
1654
1655 pdata->phy.address = 0;
1656
1657 if (XGBE_ADV(lks, Autoneg)) {
1658 pdata->phy.autoneg = AUTONEG_ENABLE;
1659 pdata->phy.speed = SPEED_UNKNOWN;
1660 pdata->phy.duplex = DUPLEX_UNKNOWN;
1661 } else {
1662 pdata->phy.autoneg = AUTONEG_DISABLE;
1663 pdata->phy.speed = xgbe_phy_best_advertised_speed(pdata);
1664 pdata->phy.duplex = DUPLEX_FULL;
1665 }
1666
1667 pdata->phy.link = 0;
1668
1669 pdata->phy.pause_autoneg = pdata->pause_autoneg;
1670 pdata->phy.tx_pause = pdata->tx_pause;
1671 pdata->phy.rx_pause = pdata->rx_pause;
1672
1673 /* Fix up Flow Control advertising */
1674 XGBE_CLR_ADV(lks, Pause);
1675 XGBE_CLR_ADV(lks, Asym_Pause);
1676
1677 if (pdata->rx_pause) {
1678 XGBE_SET_ADV(lks, Pause);
1679 XGBE_SET_ADV(lks, Asym_Pause);
1680 }
1681
1682 if (pdata->tx_pause) {
1683 /* Equivalent to XOR of Asym_Pause */
1684 if (XGBE_ADV(lks, Asym_Pause))
1685 XGBE_CLR_ADV(lks, Asym_Pause);
1686 else
1687 XGBE_SET_ADV(lks, Asym_Pause);
1688 }
1689
1690 if (netif_msg_drv(pdata))
1691 xgbe_dump_phy_registers(pdata);
1692
1693 return 0;
1694 }
1695
xgbe_init_function_ptrs_phy(struct xgbe_phy_if * phy_if)1696 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *phy_if)
1697 {
1698 phy_if->phy_init = xgbe_phy_init;
1699 phy_if->phy_exit = xgbe_phy_exit;
1700
1701 phy_if->phy_reset = xgbe_phy_reset;
1702 phy_if->phy_start = xgbe_phy_start;
1703 phy_if->phy_stop = xgbe_phy_stop;
1704
1705 phy_if->phy_status = xgbe_phy_status;
1706 phy_if->phy_config_aneg = xgbe_phy_config_aneg;
1707
1708 phy_if->phy_valid_speed = xgbe_phy_valid_speed;
1709
1710 phy_if->an_isr = xgbe_an_combined_isr;
1711
1712 phy_if->module_info = xgbe_phy_module_info;
1713 phy_if->module_eeprom = xgbe_phy_module_eeprom;
1714 }
1715