1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_PROCESSOR_H
3 #define _ASM_X86_PROCESSOR_H
4
5 #include <asm/processor-flags.h>
6
7 /* Forward declaration, a strange C thing */
8 struct task_struct;
9 struct mm_struct;
10 struct io_bitmap;
11 struct vm86;
12
13 #include <asm/math_emu.h>
14 #include <asm/segment.h>
15 #include <asm/types.h>
16 #include <uapi/asm/sigcontext.h>
17 #include <asm/current.h>
18 #include <asm/cpufeatures.h>
19 #include <asm/cpuid.h>
20 #include <asm/page.h>
21 #include <asm/pgtable_types.h>
22 #include <asm/percpu.h>
23 #include <asm/msr.h>
24 #include <asm/desc_defs.h>
25 #include <asm/nops.h>
26 #include <asm/special_insns.h>
27 #include <asm/fpu/types.h>
28 #include <asm/unwind_hints.h>
29 #include <asm/vmxfeatures.h>
30 #include <asm/vdso/processor.h>
31 #include <asm/shstk.h>
32
33 #include <linux/personality.h>
34 #include <linux/cache.h>
35 #include <linux/threads.h>
36 #include <linux/math64.h>
37 #include <linux/err.h>
38 #include <linux/irqflags.h>
39 #include <linux/mem_encrypt.h>
40
41 /*
42 * We handle most unaligned accesses in hardware. On the other hand
43 * unaligned DMA can be quite expensive on some Nehalem processors.
44 *
45 * Based on this we disable the IP header alignment in network drivers.
46 */
47 #define NET_IP_ALIGN 0
48
49 #define HBP_NUM 4
50
51 /*
52 * These alignment constraints are for performance in the vSMP case,
53 * but in the task_struct case we must also meet hardware imposed
54 * alignment requirements of the FPU state:
55 */
56 #ifdef CONFIG_X86_VSMP
57 # define ARCH_MIN_TASKALIGN (1 << INTERNODE_CACHE_SHIFT)
58 # define ARCH_MIN_MMSTRUCT_ALIGN (1 << INTERNODE_CACHE_SHIFT)
59 #else
60 # define ARCH_MIN_TASKALIGN __alignof__(union fpregs_state)
61 # define ARCH_MIN_MMSTRUCT_ALIGN 0
62 #endif
63
64 enum tlb_infos {
65 ENTRIES,
66 NR_INFO
67 };
68
69 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
70 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
71 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
72 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
73 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
74 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
75 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
76
77 /*
78 * CPU type and hardware bug flags. Kept separately for each CPU.
79 * Members of this structure are referenced in head_32.S, so think twice
80 * before touching them. [mj]
81 */
82
83 struct cpuinfo_x86 {
84 union {
85 /*
86 * The particular ordering (low-to-high) of (vendor,
87 * family, model) is done in case range of models, like
88 * it is usually done on AMD, need to be compared.
89 */
90 struct {
91 __u8 x86_model;
92 /* CPU family */
93 __u8 x86;
94 /* CPU vendor */
95 __u8 x86_vendor;
96 __u8 x86_reserved;
97 };
98 /* combined vendor, family, model */
99 __u32 x86_vfm;
100 };
101 __u8 x86_stepping;
102 #ifdef CONFIG_X86_64
103 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
104 int x86_tlbsize;
105 #endif
106 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
107 __u32 vmx_capability[NVMXINTS];
108 #endif
109 __u8 x86_virt_bits;
110 __u8 x86_phys_bits;
111 /* CPUID returned core id bits: */
112 __u8 x86_coreid_bits;
113 __u8 cu_id;
114 /* Max extended CPUID function supported: */
115 __u32 extended_cpuid_level;
116 /* Maximum supported CPUID level, -1=no CPUID: */
117 int cpuid_level;
118 /*
119 * Align to size of unsigned long because the x86_capability array
120 * is passed to bitops which require the alignment. Use unnamed
121 * union to enforce the array is aligned to size of unsigned long.
122 */
123 union {
124 __u32 x86_capability[NCAPINTS + NBUGINTS];
125 unsigned long x86_capability_alignment;
126 };
127 char x86_vendor_id[16];
128 char x86_model_id[64];
129 /* in KB - valid for CPUS which support this call: */
130 unsigned int x86_cache_size;
131 int x86_cache_alignment; /* In bytes */
132 /* Cache QoS architectural values, valid only on the BSP: */
133 int x86_cache_max_rmid; /* max index */
134 int x86_cache_occ_scale; /* scale to bytes */
135 int x86_cache_mbm_width_offset;
136 int x86_power;
137 unsigned long loops_per_jiffy;
138 /* protected processor identification number */
139 u64 ppin;
140 /* cpuid returned max cores value: */
141 u16 x86_max_cores;
142 u16 apicid;
143 u16 initial_apicid;
144 u16 x86_clflush_size;
145 /* number of cores as seen by the OS: */
146 u16 booted_cores;
147 /* Physical processor id: */
148 u16 phys_proc_id;
149 /* Logical processor id: */
150 u16 logical_proc_id;
151 /* Core id: */
152 u16 cpu_core_id;
153 u16 cpu_die_id;
154 u16 logical_die_id;
155 /* Index into per_cpu list: */
156 u16 cpu_index;
157 /* Is SMT active on this core? */
158 bool smt_active;
159 u32 microcode;
160 /* Address space bits used by the cache internally */
161 u8 x86_cache_bits;
162 unsigned initialized : 1;
163 } __randomize_layout;
164
165 #define X86_VENDOR_INTEL 0
166 #define X86_VENDOR_CYRIX 1
167 #define X86_VENDOR_AMD 2
168 #define X86_VENDOR_UMC 3
169 #define X86_VENDOR_CENTAUR 5
170 #define X86_VENDOR_TRANSMETA 7
171 #define X86_VENDOR_NSC 8
172 #define X86_VENDOR_HYGON 9
173 #define X86_VENDOR_ZHAOXIN 10
174 #define X86_VENDOR_VORTEX 11
175 #define X86_VENDOR_NUM 12
176
177 #define X86_VENDOR_UNKNOWN 0xff
178
179 /*
180 * capabilities of CPUs
181 */
182 extern struct cpuinfo_x86 boot_cpu_data;
183 extern struct cpuinfo_x86 new_cpu_data;
184
185 extern __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS];
186 extern __u32 cpu_caps_set[NCAPINTS + NBUGINTS];
187
188 #ifdef CONFIG_SMP
189 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
190 #define cpu_data(cpu) per_cpu(cpu_info, cpu)
191 #else
192 #define cpu_info boot_cpu_data
193 #define cpu_data(cpu) boot_cpu_data
194 #endif
195
196 extern const struct seq_operations cpuinfo_op;
197
198 #define cache_line_size() (boot_cpu_data.x86_cache_alignment)
199
200 extern void cpu_detect(struct cpuinfo_x86 *c);
201
l1tf_pfn_limit(void)202 static inline unsigned long long l1tf_pfn_limit(void)
203 {
204 return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
205 }
206
207 void init_cpu_devs(void);
208 void get_cpu_vendor(struct cpuinfo_x86 *c);
209 extern void early_cpu_init(void);
210 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
211 extern void print_cpu_info(struct cpuinfo_x86 *);
212 void print_cpu_msr(struct cpuinfo_x86 *);
213
214 /*
215 * Friendlier CR3 helpers.
216 */
read_cr3_pa(void)217 static inline unsigned long read_cr3_pa(void)
218 {
219 return __read_cr3() & CR3_ADDR_MASK;
220 }
221
native_read_cr3_pa(void)222 static inline unsigned long native_read_cr3_pa(void)
223 {
224 return __native_read_cr3() & CR3_ADDR_MASK;
225 }
226
load_cr3(pgd_t * pgdir)227 static inline void load_cr3(pgd_t *pgdir)
228 {
229 write_cr3(__sme_pa(pgdir));
230 }
231
232 /*
233 * Note that while the legacy 'TSS' name comes from 'Task State Segment',
234 * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
235 * unrelated to the task-switch mechanism:
236 */
237 #ifdef CONFIG_X86_32
238 /* This is the TSS defined by the hardware. */
239 struct x86_hw_tss {
240 unsigned short back_link, __blh;
241 unsigned long sp0;
242 unsigned short ss0, __ss0h;
243 unsigned long sp1;
244
245 /*
246 * We don't use ring 1, so ss1 is a convenient scratch space in
247 * the same cacheline as sp0. We use ss1 to cache the value in
248 * MSR_IA32_SYSENTER_CS. When we context switch
249 * MSR_IA32_SYSENTER_CS, we first check if the new value being
250 * written matches ss1, and, if it's not, then we wrmsr the new
251 * value and update ss1.
252 *
253 * The only reason we context switch MSR_IA32_SYSENTER_CS is
254 * that we set it to zero in vm86 tasks to avoid corrupting the
255 * stack if we were to go through the sysenter path from vm86
256 * mode.
257 */
258 unsigned short ss1; /* MSR_IA32_SYSENTER_CS */
259
260 unsigned short __ss1h;
261 unsigned long sp2;
262 unsigned short ss2, __ss2h;
263 unsigned long __cr3;
264 unsigned long ip;
265 unsigned long flags;
266 unsigned long ax;
267 unsigned long cx;
268 unsigned long dx;
269 unsigned long bx;
270 unsigned long sp;
271 unsigned long bp;
272 unsigned long si;
273 unsigned long di;
274 unsigned short es, __esh;
275 unsigned short cs, __csh;
276 unsigned short ss, __ssh;
277 unsigned short ds, __dsh;
278 unsigned short fs, __fsh;
279 unsigned short gs, __gsh;
280 unsigned short ldt, __ldth;
281 unsigned short trace;
282 unsigned short io_bitmap_base;
283
284 } __attribute__((packed));
285 #else
286 struct x86_hw_tss {
287 u32 reserved1;
288 u64 sp0;
289 u64 sp1;
290
291 /*
292 * Since Linux does not use ring 2, the 'sp2' slot is unused by
293 * hardware. entry_SYSCALL_64 uses it as scratch space to stash
294 * the user RSP value.
295 */
296 u64 sp2;
297
298 u64 reserved2;
299 u64 ist[7];
300 u32 reserved3;
301 u32 reserved4;
302 u16 reserved5;
303 u16 io_bitmap_base;
304
305 } __attribute__((packed));
306 #endif
307
308 /*
309 * IO-bitmap sizes:
310 */
311 #define IO_BITMAP_BITS 65536
312 #define IO_BITMAP_BYTES (IO_BITMAP_BITS / BITS_PER_BYTE)
313 #define IO_BITMAP_LONGS (IO_BITMAP_BYTES / sizeof(long))
314
315 #define IO_BITMAP_OFFSET_VALID_MAP \
316 (offsetof(struct tss_struct, io_bitmap.bitmap) - \
317 offsetof(struct tss_struct, x86_tss))
318
319 #define IO_BITMAP_OFFSET_VALID_ALL \
320 (offsetof(struct tss_struct, io_bitmap.mapall) - \
321 offsetof(struct tss_struct, x86_tss))
322
323 #ifdef CONFIG_X86_IOPL_IOPERM
324 /*
325 * sizeof(unsigned long) coming from an extra "long" at the end of the
326 * iobitmap. The limit is inclusive, i.e. the last valid byte.
327 */
328 # define __KERNEL_TSS_LIMIT \
329 (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
330 sizeof(unsigned long) - 1)
331 #else
332 # define __KERNEL_TSS_LIMIT \
333 (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
334 #endif
335
336 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
337 #define IO_BITMAP_OFFSET_INVALID (__KERNEL_TSS_LIMIT + 1)
338
339 struct entry_stack {
340 char stack[PAGE_SIZE];
341 };
342
343 struct entry_stack_page {
344 struct entry_stack stack;
345 } __aligned(PAGE_SIZE);
346
347 /*
348 * All IO bitmap related data stored in the TSS:
349 */
350 struct x86_io_bitmap {
351 /* The sequence number of the last active bitmap. */
352 u64 prev_sequence;
353
354 /*
355 * Store the dirty size of the last io bitmap offender. The next
356 * one will have to do the cleanup as the switch out to a non io
357 * bitmap user will just set x86_tss.io_bitmap_base to a value
358 * outside of the TSS limit. So for sane tasks there is no need to
359 * actually touch the io_bitmap at all.
360 */
361 unsigned int prev_max;
362
363 /*
364 * The extra 1 is there because the CPU will access an
365 * additional byte beyond the end of the IO permission
366 * bitmap. The extra byte must be all 1 bits, and must
367 * be within the limit.
368 */
369 unsigned long bitmap[IO_BITMAP_LONGS + 1];
370
371 /*
372 * Special I/O bitmap to emulate IOPL(3). All bytes zero,
373 * except the additional byte at the end.
374 */
375 unsigned long mapall[IO_BITMAP_LONGS + 1];
376 };
377
378 struct tss_struct {
379 /*
380 * The fixed hardware portion. This must not cross a page boundary
381 * at risk of violating the SDM's advice and potentially triggering
382 * errata.
383 */
384 struct x86_hw_tss x86_tss;
385
386 struct x86_io_bitmap io_bitmap;
387 } __aligned(PAGE_SIZE);
388
389 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
390
391 /* Per CPU interrupt stacks */
392 struct irq_stack {
393 char stack[IRQ_STACK_SIZE];
394 } __aligned(IRQ_STACK_SIZE);
395
396 #ifdef CONFIG_X86_64
397 struct fixed_percpu_data {
398 /*
399 * GCC hardcodes the stack canary as %gs:40. Since the
400 * irq_stack is the object at %gs:0, we reserve the bottom
401 * 48 bytes of the irq stack for the canary.
402 *
403 * Once we are willing to require -mstack-protector-guard-symbol=
404 * support for x86_64 stackprotector, we can get rid of this.
405 */
406 char gs_base[40];
407 unsigned long stack_canary;
408 };
409
410 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
411 DECLARE_INIT_PER_CPU(fixed_percpu_data);
412
cpu_kernelmode_gs_base(int cpu)413 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
414 {
415 return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
416 }
417
418 extern asmlinkage void entry_SYSCALL32_ignore(void);
419
420 /* Save actual FS/GS selectors and bases to current->thread */
421 void current_save_fsgs(void);
422 #else /* X86_64 */
423 #ifdef CONFIG_STACKPROTECTOR
424 DECLARE_PER_CPU(unsigned long, __stack_chk_guard);
425 #endif
426 #endif /* !X86_64 */
427
428 struct perf_event;
429
430 struct thread_struct {
431 /* Cached TLS descriptors: */
432 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
433 #ifdef CONFIG_X86_32
434 unsigned long sp0;
435 #endif
436 unsigned long sp;
437 #ifdef CONFIG_X86_32
438 unsigned long sysenter_cs;
439 #else
440 unsigned short es;
441 unsigned short ds;
442 unsigned short fsindex;
443 unsigned short gsindex;
444 #endif
445
446 #ifdef CONFIG_X86_64
447 unsigned long fsbase;
448 unsigned long gsbase;
449 #else
450 /*
451 * XXX: this could presumably be unsigned short. Alternatively,
452 * 32-bit kernels could be taught to use fsindex instead.
453 */
454 unsigned long fs;
455 unsigned long gs;
456 #endif
457
458 /* Save middle states of ptrace breakpoints */
459 struct perf_event *ptrace_bps[HBP_NUM];
460 /* Debug status used for traps, single steps, etc... */
461 unsigned long virtual_dr6;
462 /* Keep track of the exact dr7 value set by the user */
463 unsigned long ptrace_dr7;
464 /* Fault info: */
465 unsigned long cr2;
466 unsigned long trap_nr;
467 unsigned long error_code;
468 #ifdef CONFIG_VM86
469 /* Virtual 86 mode info */
470 struct vm86 *vm86;
471 #endif
472 /* IO permissions: */
473 struct io_bitmap *io_bitmap;
474
475 /*
476 * IOPL. Privilege level dependent I/O permission which is
477 * emulated via the I/O bitmap to prevent user space from disabling
478 * interrupts.
479 */
480 unsigned long iopl_emul;
481
482 unsigned int iopl_warn:1;
483
484 /*
485 * Protection Keys Register for Userspace. Loaded immediately on
486 * context switch. Store it in thread_struct to avoid a lookup in
487 * the tasks's FPU xstate buffer. This value is only valid when a
488 * task is scheduled out. For 'current' the authoritative source of
489 * PKRU is the hardware itself.
490 */
491 u32 pkru;
492
493 #ifdef CONFIG_X86_USER_SHADOW_STACK
494 unsigned long features;
495 unsigned long features_locked;
496
497 struct thread_shstk shstk;
498 #endif
499
500 /* Floating point and extended processor state */
501 struct fpu fpu;
502 /*
503 * WARNING: 'fpu' is dynamically-sized. It *MUST* be at
504 * the end.
505 */
506 };
507
508 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
509
arch_thread_struct_whitelist(unsigned long * offset,unsigned long * size)510 static inline void arch_thread_struct_whitelist(unsigned long *offset,
511 unsigned long *size)
512 {
513 fpu_thread_struct_whitelist(offset, size);
514 }
515
516 static inline void
native_load_sp0(unsigned long sp0)517 native_load_sp0(unsigned long sp0)
518 {
519 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
520 }
521
native_swapgs(void)522 static __always_inline void native_swapgs(void)
523 {
524 #ifdef CONFIG_X86_64
525 asm volatile("swapgs" ::: "memory");
526 #endif
527 }
528
current_top_of_stack(void)529 static __always_inline unsigned long current_top_of_stack(void)
530 {
531 /*
532 * We can't read directly from tss.sp0: sp0 on x86_32 is special in
533 * and around vm86 mode and sp0 on x86_64 is special because of the
534 * entry trampoline.
535 */
536 return this_cpu_read_stable(pcpu_hot.top_of_stack);
537 }
538
on_thread_stack(void)539 static __always_inline bool on_thread_stack(void)
540 {
541 return (unsigned long)(current_top_of_stack() -
542 current_stack_pointer) < THREAD_SIZE;
543 }
544
545 #ifdef CONFIG_PARAVIRT_XXL
546 #include <asm/paravirt.h>
547 #else
548
load_sp0(unsigned long sp0)549 static inline void load_sp0(unsigned long sp0)
550 {
551 native_load_sp0(sp0);
552 }
553
554 #endif /* CONFIG_PARAVIRT_XXL */
555
556 unsigned long __get_wchan(struct task_struct *p);
557
558 extern void select_idle_routine(const struct cpuinfo_x86 *c);
559 extern void amd_e400_c1e_apic_setup(void);
560
561 extern unsigned long boot_option_idle_override;
562
563 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
564 IDLE_POLL};
565
566 extern void enable_sep_cpu(void);
567
568
569 /* Defined in head.S */
570 extern struct desc_ptr early_gdt_descr;
571
572 extern void switch_gdt_and_percpu_base(int);
573 extern void load_direct_gdt(int);
574 extern void load_fixmap_gdt(int);
575 extern void cpu_init(void);
576 extern void cpu_init_exception_handling(void);
577 extern void cr4_init(void);
578
get_debugctlmsr(void)579 static inline unsigned long get_debugctlmsr(void)
580 {
581 unsigned long debugctlmsr = 0;
582
583 #ifndef CONFIG_X86_DEBUGCTLMSR
584 if (boot_cpu_data.x86 < 6)
585 return 0;
586 #endif
587 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
588
589 return debugctlmsr;
590 }
591
update_debugctlmsr(unsigned long debugctlmsr)592 static inline void update_debugctlmsr(unsigned long debugctlmsr)
593 {
594 #ifndef CONFIG_X86_DEBUGCTLMSR
595 if (boot_cpu_data.x86 < 6)
596 return;
597 #endif
598 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
599 }
600
601 extern void set_task_blockstep(struct task_struct *task, bool on);
602
603 /* Boot loader type from the setup header: */
604 extern int bootloader_type;
605 extern int bootloader_version;
606
607 extern char ignore_fpu_irq;
608
609 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
610 #define ARCH_HAS_PREFETCHW
611
612 #ifdef CONFIG_X86_32
613 # define BASE_PREFETCH ""
614 # define ARCH_HAS_PREFETCH
615 #else
616 # define BASE_PREFETCH "prefetcht0 %P1"
617 #endif
618
619 /*
620 * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
621 *
622 * It's not worth to care about 3dnow prefetches for the K6
623 * because they are microcoded there and very slow.
624 */
prefetch(const void * x)625 static inline void prefetch(const void *x)
626 {
627 alternative_input(BASE_PREFETCH, "prefetchnta %P1",
628 X86_FEATURE_XMM,
629 "m" (*(const char *)x));
630 }
631
632 /*
633 * 3dnow prefetch to get an exclusive cache line.
634 * Useful for spinlocks to avoid one state transition in the
635 * cache coherency protocol:
636 */
prefetchw(const void * x)637 static __always_inline void prefetchw(const void *x)
638 {
639 alternative_input(BASE_PREFETCH, "prefetchw %P1",
640 X86_FEATURE_3DNOWPREFETCH,
641 "m" (*(const char *)x));
642 }
643
644 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
645 TOP_OF_KERNEL_STACK_PADDING)
646
647 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
648
649 #define task_pt_regs(task) \
650 ({ \
651 unsigned long __ptr = (unsigned long)task_stack_page(task); \
652 __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING; \
653 ((struct pt_regs *)__ptr) - 1; \
654 })
655
656 #ifdef CONFIG_X86_32
657 #define INIT_THREAD { \
658 .sp0 = TOP_OF_INIT_STACK, \
659 .sysenter_cs = __KERNEL_CS, \
660 }
661
662 #define KSTK_ESP(task) (task_pt_regs(task)->sp)
663
664 #else
665 extern unsigned long __end_init_task[];
666
667 #define INIT_THREAD { \
668 .sp = (unsigned long)&__end_init_task - sizeof(struct pt_regs), \
669 }
670
671 extern unsigned long KSTK_ESP(struct task_struct *task);
672
673 #endif /* CONFIG_X86_64 */
674
675 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
676 unsigned long new_sp);
677
678 /*
679 * This decides where the kernel will search for a free chunk of vm
680 * space during mmap's.
681 */
682 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
683 #define TASK_UNMAPPED_BASE __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
684
685 #define KSTK_EIP(task) (task_pt_regs(task)->ip)
686
687 /* Get/set a process' ability to use the timestamp counter instruction */
688 #define GET_TSC_CTL(adr) get_tsc_mode((adr))
689 #define SET_TSC_CTL(val) set_tsc_mode((val))
690
691 extern int get_tsc_mode(unsigned long adr);
692 extern int set_tsc_mode(unsigned int val);
693
694 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
695
696 extern u16 get_llc_id(unsigned int cpu);
697
698 #ifdef CONFIG_CPU_SUP_AMD
699 extern u32 amd_get_nodes_per_socket(void);
700 extern u32 amd_get_highest_perf(void);
701 extern void amd_clear_divider(void);
702 extern void amd_check_microcode(void);
703 #else
amd_get_nodes_per_socket(void)704 static inline u32 amd_get_nodes_per_socket(void) { return 0; }
amd_get_highest_perf(void)705 static inline u32 amd_get_highest_perf(void) { return 0; }
amd_clear_divider(void)706 static inline void amd_clear_divider(void) { }
amd_check_microcode(void)707 static inline void amd_check_microcode(void) { }
708 #endif
709
710 extern unsigned long arch_align_stack(unsigned long sp);
711 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
712 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
713
714 void default_idle(void);
715 #ifdef CONFIG_XEN
716 bool xen_set_default_idle(void);
717 #else
718 #define xen_set_default_idle 0
719 #endif
720
721 void __noreturn stop_this_cpu(void *dummy);
722 void microcode_check(struct cpuinfo_x86 *prev_info);
723 void store_cpu_caps(struct cpuinfo_x86 *info);
724
725 enum l1tf_mitigations {
726 L1TF_MITIGATION_OFF,
727 L1TF_MITIGATION_FLUSH_NOWARN,
728 L1TF_MITIGATION_FLUSH,
729 L1TF_MITIGATION_FLUSH_NOSMT,
730 L1TF_MITIGATION_FULL,
731 L1TF_MITIGATION_FULL_FORCE
732 };
733
734 extern enum l1tf_mitigations l1tf_mitigation;
735
736 enum mds_mitigations {
737 MDS_MITIGATION_OFF,
738 MDS_MITIGATION_FULL,
739 MDS_MITIGATION_VMWERV,
740 };
741
742 #ifdef CONFIG_X86_SGX
743 int arch_memory_failure(unsigned long pfn, int flags);
744 #define arch_memory_failure arch_memory_failure
745
746 bool arch_is_platform_page(u64 paddr);
747 #define arch_is_platform_page arch_is_platform_page
748 #endif
749
750 extern bool gds_ucode_mitigated(void);
751
752 /*
753 * Make previous memory operations globally visible before
754 * a WRMSR.
755 *
756 * MFENCE makes writes visible, but only affects load/store
757 * instructions. WRMSR is unfortunately not a load/store
758 * instruction and is unaffected by MFENCE. The LFENCE ensures
759 * that the WRMSR is not reordered.
760 *
761 * Most WRMSRs are full serializing instructions themselves and
762 * do not require this barrier. This is only required for the
763 * IA32_TSC_DEADLINE and X2APIC MSRs.
764 */
weak_wrmsr_fence(void)765 static inline void weak_wrmsr_fence(void)
766 {
767 alternative("mfence; lfence", "", ALT_NOT(X86_FEATURE_APIC_MSRS_FENCE));
768 }
769
770 #endif /* _ASM_X86_PROCESSOR_H */
771