1 /*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu/datadir.h"
33 #include "qemu/units.h"
34 #include "qemu/option.h"
35 #include "monitor/qdev.h"
36 #include "hw/sysbus.h"
37 #include "hw/arm/boot.h"
38 #include "hw/arm/primecell.h"
39 #include "hw/arm/virt.h"
40 #include "hw/block/flash.h"
41 #include "hw/vfio/vfio-calxeda-xgmac.h"
42 #include "hw/vfio/vfio-amd-xgbe.h"
43 #include "hw/display/ramfb.h"
44 #include "net/net.h"
45 #include "sysemu/device_tree.h"
46 #include "sysemu/numa.h"
47 #include "sysemu/runstate.h"
48 #include "sysemu/tpm.h"
49 #include "sysemu/tcg.h"
50 #include "sysemu/kvm.h"
51 #include "sysemu/hvf.h"
52 #include "sysemu/qtest.h"
53 #include "hw/loader.h"
54 #include "qapi/error.h"
55 #include "qemu/bitops.h"
56 #include "qemu/error-report.h"
57 #include "qemu/module.h"
58 #include "hw/pci-host/gpex.h"
59 #include "hw/virtio/virtio-pci.h"
60 #include "hw/core/sysbus-fdt.h"
61 #include "hw/platform-bus.h"
62 #include "hw/qdev-properties.h"
63 #include "hw/arm/fdt.h"
64 #include "hw/intc/arm_gic.h"
65 #include "hw/intc/arm_gicv3_common.h"
66 #include "hw/intc/arm_gicv3_its_common.h"
67 #include "hw/irq.h"
68 #include "kvm_arm.h"
69 #include "hvf_arm.h"
70 #include "hw/firmware/smbios.h"
71 #include "qapi/visitor.h"
72 #include "qapi/qapi-visit-common.h"
73 #include "qapi/qmp/qlist.h"
74 #include "standard-headers/linux/input.h"
75 #include "hw/arm/smmuv3.h"
76 #include "hw/acpi/acpi.h"
77 #include "target/arm/cpu-qom.h"
78 #include "target/arm/internals.h"
79 #include "target/arm/multiprocessing.h"
80 #include "target/arm/gtimer.h"
81 #include "hw/mem/pc-dimm.h"
82 #include "hw/mem/nvdimm.h"
83 #include "hw/acpi/generic_event_device.h"
84 #include "hw/virtio/virtio-md-pci.h"
85 #include "hw/virtio/virtio-iommu.h"
86 #include "hw/char/pl011.h"
87 #include "qemu/guest-random.h"
88
89 static GlobalProperty arm_virt_compat[] = {
90 { TYPE_VIRTIO_IOMMU_PCI, "aw-bits", "48" },
91 };
92 static const size_t arm_virt_compat_len = G_N_ELEMENTS(arm_virt_compat);
93
94 /*
95 * This cannot be called from the virt_machine_class_init() because
96 * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new()
97 * only is called on virt non abstract class init.
98 */
arm_virt_compat_set(MachineClass * mc)99 static void arm_virt_compat_set(MachineClass *mc)
100 {
101 compat_props_add(mc->compat_props, arm_virt_compat,
102 arm_virt_compat_len);
103 }
104
105 #define DEFINE_VIRT_MACHINE_IMPL(latest, ...) \
106 static void MACHINE_VER_SYM(class_init, virt, __VA_ARGS__)( \
107 ObjectClass *oc, \
108 void *data) \
109 { \
110 MachineClass *mc = MACHINE_CLASS(oc); \
111 arm_virt_compat_set(mc); \
112 MACHINE_VER_SYM(options, virt, __VA_ARGS__)(mc); \
113 mc->desc = "QEMU " MACHINE_VER_STR(__VA_ARGS__) " ARM Virtual Machine"; \
114 MACHINE_VER_DEPRECATION(__VA_ARGS__); \
115 if (latest) { \
116 mc->alias = "virt"; \
117 } \
118 } \
119 static const TypeInfo MACHINE_VER_SYM(info, virt, __VA_ARGS__) = \
120 { \
121 .name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
122 .parent = TYPE_VIRT_MACHINE, \
123 .class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
124 }; \
125 static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
126 { \
127 MACHINE_VER_DELETION(__VA_ARGS__); \
128 type_register_static(&MACHINE_VER_SYM(info, virt, __VA_ARGS__)); \
129 } \
130 type_init(MACHINE_VER_SYM(register, virt, __VA_ARGS__));
131
132 #define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
133 DEFINE_VIRT_MACHINE_IMPL(true, major, minor)
134 #define DEFINE_VIRT_MACHINE(major, minor) \
135 DEFINE_VIRT_MACHINE_IMPL(false, major, minor)
136
137
138 /* Number of external interrupt lines to configure the GIC with */
139 #define NUM_IRQS 256
140
141 #define PLATFORM_BUS_NUM_IRQS 64
142
143 /* Legacy RAM limit in GB (< version 4.0) */
144 #define LEGACY_RAMLIMIT_GB 255
145 #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
146
147 /* Addresses and sizes of our components.
148 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
149 * 128MB..256MB is used for miscellaneous device I/O.
150 * 256MB..1GB is reserved for possible future PCI support (ie where the
151 * PCI memory window will go if we add a PCI host controller).
152 * 1GB and up is RAM (which may happily spill over into the
153 * high memory region beyond 4GB).
154 * This represents a compromise between how much RAM can be given to
155 * a 32 bit VM and leaving space for expansion and in particular for PCI.
156 * Note that devices should generally be placed at multiples of 0x10000,
157 * to accommodate guests using 64K pages.
158 */
159 static const MemMapEntry base_memmap[] = {
160 /* Space up to 0x8000000 is reserved for a boot ROM */
161 [VIRT_FLASH] = { 0, 0x08000000 },
162 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
163 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
164 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
165 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
166 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
167 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
168 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
169 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
170 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
171 /* This redistributor space allows up to 2*64kB*123 CPUs */
172 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
173 [VIRT_UART0] = { 0x09000000, 0x00001000 },
174 [VIRT_RTC] = { 0x09010000, 0x00001000 },
175 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
176 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
177 [VIRT_UART1] = { 0x09040000, 0x00001000 },
178 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
179 [VIRT_PCDIMM_ACPI] = { 0x09070000, MEMORY_HOTPLUG_IO_LEN },
180 [VIRT_ACPI_GED] = { 0x09080000, ACPI_GED_EVT_SEL_LEN },
181 [VIRT_NVDIMM_ACPI] = { 0x09090000, NVDIMM_ACPI_IO_LEN},
182 [VIRT_PVTIME] = { 0x090a0000, 0x00010000 },
183 [VIRT_SECURE_GPIO] = { 0x090b0000, 0x00001000 },
184 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
185 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
186 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
187 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
188 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
189 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
190 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
191 /* Actual RAM size depends on initial RAM and device memory settings */
192 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
193 };
194
195 /*
196 * Highmem IO Regions: This memory map is floating, located after the RAM.
197 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
198 * top of the RAM, so that its base get the same alignment as the size,
199 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
200 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
201 * Note the extended_memmap is sized so that it eventually also includes the
202 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
203 * index of base_memmap).
204 *
205 * The memory map for these Highmem IO Regions can be in legacy or compact
206 * layout, depending on 'compact-highmem' property. With legacy layout, the
207 * PA space for one specific region is always reserved, even if the region
208 * has been disabled or doesn't fit into the PA space. However, the PA space
209 * for the region won't be reserved in these circumstances with compact layout.
210 */
211 static MemMapEntry extended_memmap[] = {
212 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
213 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
214 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
215 /* Second PCIe window */
216 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
217 };
218
219 static const int a15irqmap[] = {
220 [VIRT_UART0] = 1,
221 [VIRT_RTC] = 2,
222 [VIRT_PCIE] = 3, /* ... to 6 */
223 [VIRT_GPIO] = 7,
224 [VIRT_UART1] = 8,
225 [VIRT_ACPI_GED] = 9,
226 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
227 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
228 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
229 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
230 };
231
create_randomness(MachineState * ms,const char * node)232 static void create_randomness(MachineState *ms, const char *node)
233 {
234 struct {
235 uint64_t kaslr;
236 uint8_t rng[32];
237 } seed;
238
239 if (qemu_guest_getrandom(&seed, sizeof(seed), NULL)) {
240 return;
241 }
242 qemu_fdt_setprop_u64(ms->fdt, node, "kaslr-seed", seed.kaslr);
243 qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng));
244 }
245
246 /*
247 * The CPU object always exposes the NS EL2 virt timer IRQ line,
248 * but we don't want to advertise it to the guest in the dtb or ACPI
249 * table unless it's really going to do something.
250 */
ns_el2_virt_timer_present(void)251 static bool ns_el2_virt_timer_present(void)
252 {
253 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
254 CPUARMState *env = &cpu->env;
255
256 return arm_feature(env, ARM_FEATURE_AARCH64) &&
257 arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu);
258 }
259
create_fdt(VirtMachineState * vms)260 static void create_fdt(VirtMachineState *vms)
261 {
262 MachineState *ms = MACHINE(vms);
263 int nb_numa_nodes = ms->numa_state->num_nodes;
264 void *fdt = create_device_tree(&vms->fdt_size);
265
266 if (!fdt) {
267 error_report("create_device_tree() failed");
268 exit(1);
269 }
270
271 ms->fdt = fdt;
272
273 /* Header */
274 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
275 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
276 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
277 qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
278
279 /*
280 * For QEMU, all DMA is coherent. Advertising this in the root node
281 * has two benefits:
282 *
283 * - It avoids potential bugs where we forget to mark a DMA
284 * capable device as being dma-coherent
285 * - It avoids spurious warnings from the Linux kernel about
286 * devices which can't do DMA at all
287 */
288 qemu_fdt_setprop(fdt, "/", "dma-coherent", NULL, 0);
289
290 /* /chosen must exist for load_dtb to fill in necessary properties later */
291 qemu_fdt_add_subnode(fdt, "/chosen");
292 if (vms->dtb_randomness) {
293 create_randomness(ms, "/chosen");
294 }
295
296 if (vms->secure) {
297 qemu_fdt_add_subnode(fdt, "/secure-chosen");
298 if (vms->dtb_randomness) {
299 create_randomness(ms, "/secure-chosen");
300 }
301 }
302
303 qemu_fdt_add_subnode(fdt, "/aliases");
304
305 /* Clock node, for the benefit of the UART. The kernel device tree
306 * binding documentation claims the PL011 node clock properties are
307 * optional but in practice if you omit them the kernel refuses to
308 * probe for the device.
309 */
310 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
311 qemu_fdt_add_subnode(fdt, "/apb-pclk");
312 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
313 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
314 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
315 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
316 "clk24mhz");
317 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
318
319 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
320 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
321 uint32_t *matrix = g_malloc0(size);
322 int idx, i, j;
323
324 for (i = 0; i < nb_numa_nodes; i++) {
325 for (j = 0; j < nb_numa_nodes; j++) {
326 idx = (i * nb_numa_nodes + j) * 3;
327 matrix[idx + 0] = cpu_to_be32(i);
328 matrix[idx + 1] = cpu_to_be32(j);
329 matrix[idx + 2] =
330 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
331 }
332 }
333
334 qemu_fdt_add_subnode(fdt, "/distance-map");
335 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
336 "numa-distance-map-v1");
337 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
338 matrix, size);
339 g_free(matrix);
340 }
341 }
342
fdt_add_timer_nodes(const VirtMachineState * vms)343 static void fdt_add_timer_nodes(const VirtMachineState *vms)
344 {
345 /* On real hardware these interrupts are level-triggered.
346 * On KVM they were edge-triggered before host kernel version 4.4,
347 * and level-triggered afterwards.
348 * On emulated QEMU they are level-triggered.
349 *
350 * Getting the DTB info about them wrong is awkward for some
351 * guest kernels:
352 * pre-4.8 ignore the DT and leave the interrupt configured
353 * with whatever the GIC reset value (or the bootloader) left it at
354 * 4.8 before rc6 honour the incorrect data by programming it back
355 * into the GIC, causing problems
356 * 4.8rc6 and later ignore the DT and always write "level triggered"
357 * into the GIC
358 *
359 * For backwards-compatibility, virt-2.8 and earlier will continue
360 * to say these are edge-triggered, but later machines will report
361 * the correct information.
362 */
363 ARMCPU *armcpu;
364 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
365 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
366 MachineState *ms = MACHINE(vms);
367
368 if (vmc->claim_edge_triggered_timers) {
369 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
370 }
371
372 if (vms->gic_version == VIRT_GIC_VERSION_2) {
373 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
374 GIC_FDT_IRQ_PPI_CPU_WIDTH,
375 (1 << MACHINE(vms)->smp.cpus) - 1);
376 }
377
378 qemu_fdt_add_subnode(ms->fdt, "/timer");
379
380 armcpu = ARM_CPU(qemu_get_cpu(0));
381 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
382 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
383 qemu_fdt_setprop(ms->fdt, "/timer", "compatible",
384 compat, sizeof(compat));
385 } else {
386 qemu_fdt_setprop_string(ms->fdt, "/timer", "compatible",
387 "arm,armv7-timer");
388 }
389 qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0);
390 if (vms->ns_el2_virt_timer_irq) {
391 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
392 GIC_FDT_IRQ_TYPE_PPI,
393 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
394 GIC_FDT_IRQ_TYPE_PPI,
395 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
396 GIC_FDT_IRQ_TYPE_PPI,
397 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
398 GIC_FDT_IRQ_TYPE_PPI,
399 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags,
400 GIC_FDT_IRQ_TYPE_PPI,
401 INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags);
402 } else {
403 qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts",
404 GIC_FDT_IRQ_TYPE_PPI,
405 INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags,
406 GIC_FDT_IRQ_TYPE_PPI,
407 INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags,
408 GIC_FDT_IRQ_TYPE_PPI,
409 INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags,
410 GIC_FDT_IRQ_TYPE_PPI,
411 INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags);
412 }
413 }
414
fdt_add_cpu_nodes(const VirtMachineState * vms)415 static void fdt_add_cpu_nodes(const VirtMachineState *vms)
416 {
417 int cpu;
418 int addr_cells = 1;
419 const MachineState *ms = MACHINE(vms);
420 const VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
421 int smp_cpus = ms->smp.cpus;
422
423 /*
424 * See Linux Documentation/devicetree/bindings/arm/cpus.yaml
425 * On ARM v8 64-bit systems value should be set to 2,
426 * that corresponds to the MPIDR_EL1 register size.
427 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
428 * in the system, #address-cells can be set to 1, since
429 * MPIDR_EL1[63:32] bits are not used for CPUs
430 * identification.
431 *
432 * Here we actually don't know whether our system is 32- or 64-bit one.
433 * The simplest way to go is to examine affinity IDs of all our CPUs. If
434 * at least one of them has Aff3 populated, we set #address-cells to 2.
435 */
436 for (cpu = 0; cpu < smp_cpus; cpu++) {
437 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
438
439 if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
440 addr_cells = 2;
441 break;
442 }
443 }
444
445 qemu_fdt_add_subnode(ms->fdt, "/cpus");
446 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", addr_cells);
447 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
448
449 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
450 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
451 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
452 CPUState *cs = CPU(armcpu);
453
454 qemu_fdt_add_subnode(ms->fdt, nodename);
455 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
456 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
457 armcpu->dtb_compatible);
458
459 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED && smp_cpus > 1) {
460 qemu_fdt_setprop_string(ms->fdt, nodename,
461 "enable-method", "psci");
462 }
463
464 if (addr_cells == 2) {
465 qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
466 arm_cpu_mp_affinity(armcpu));
467 } else {
468 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
469 arm_cpu_mp_affinity(armcpu));
470 }
471
472 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
473 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id",
474 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
475 }
476
477 if (!vmc->no_cpu_topology) {
478 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
479 qemu_fdt_alloc_phandle(ms->fdt));
480 }
481
482 g_free(nodename);
483 }
484
485 if (!vmc->no_cpu_topology) {
486 /*
487 * Add vCPU topology description through fdt node cpu-map.
488 *
489 * See Linux Documentation/devicetree/bindings/cpu/cpu-topology.txt
490 * In a SMP system, the hierarchy of CPUs can be defined through
491 * four entities that are used to describe the layout of CPUs in
492 * the system: socket/cluster/core/thread.
493 *
494 * A socket node represents the boundary of system physical package
495 * and its child nodes must be one or more cluster nodes. A system
496 * can contain several layers of clustering within a single physical
497 * package and cluster nodes can be contained in parent cluster nodes.
498 *
499 * Note: currently we only support one layer of clustering within
500 * each physical package.
501 */
502 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map");
503
504 for (cpu = smp_cpus - 1; cpu >= 0; cpu--) {
505 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", cpu);
506 char *map_path;
507
508 if (ms->smp.threads > 1) {
509 map_path = g_strdup_printf(
510 "/cpus/cpu-map/socket%d/cluster%d/core%d/thread%d",
511 cpu / (ms->smp.clusters * ms->smp.cores * ms->smp.threads),
512 (cpu / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters,
513 (cpu / ms->smp.threads) % ms->smp.cores,
514 cpu % ms->smp.threads);
515 } else {
516 map_path = g_strdup_printf(
517 "/cpus/cpu-map/socket%d/cluster%d/core%d",
518 cpu / (ms->smp.clusters * ms->smp.cores),
519 (cpu / ms->smp.cores) % ms->smp.clusters,
520 cpu % ms->smp.cores);
521 }
522 qemu_fdt_add_path(ms->fdt, map_path);
523 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path);
524
525 g_free(map_path);
526 g_free(cpu_path);
527 }
528 }
529 }
530
fdt_add_its_gic_node(VirtMachineState * vms)531 static void fdt_add_its_gic_node(VirtMachineState *vms)
532 {
533 char *nodename;
534 MachineState *ms = MACHINE(vms);
535
536 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
537 nodename = g_strdup_printf("/intc/its@%" PRIx64,
538 vms->memmap[VIRT_GIC_ITS].base);
539 qemu_fdt_add_subnode(ms->fdt, nodename);
540 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
541 "arm,gic-v3-its");
542 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
543 qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
544 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
545 2, vms->memmap[VIRT_GIC_ITS].base,
546 2, vms->memmap[VIRT_GIC_ITS].size);
547 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
548 g_free(nodename);
549 }
550
fdt_add_v2m_gic_node(VirtMachineState * vms)551 static void fdt_add_v2m_gic_node(VirtMachineState *vms)
552 {
553 MachineState *ms = MACHINE(vms);
554 char *nodename;
555
556 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
557 vms->memmap[VIRT_GIC_V2M].base);
558 vms->msi_phandle = qemu_fdt_alloc_phandle(ms->fdt);
559 qemu_fdt_add_subnode(ms->fdt, nodename);
560 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
561 "arm,gic-v2m-frame");
562 qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
563 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
564 2, vms->memmap[VIRT_GIC_V2M].base,
565 2, vms->memmap[VIRT_GIC_V2M].size);
566 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->msi_phandle);
567 g_free(nodename);
568 }
569
fdt_add_gic_node(VirtMachineState * vms)570 static void fdt_add_gic_node(VirtMachineState *vms)
571 {
572 MachineState *ms = MACHINE(vms);
573 char *nodename;
574
575 vms->gic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
576 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", vms->gic_phandle);
577
578 nodename = g_strdup_printf("/intc@%" PRIx64,
579 vms->memmap[VIRT_GIC_DIST].base);
580 qemu_fdt_add_subnode(ms->fdt, nodename);
581 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3);
582 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
583 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2);
584 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2);
585 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0);
586 if (vms->gic_version != VIRT_GIC_VERSION_2) {
587 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
588
589 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
590 "arm,gic-v3");
591
592 qemu_fdt_setprop_cell(ms->fdt, nodename,
593 "#redistributor-regions", nb_redist_regions);
594
595 if (nb_redist_regions == 1) {
596 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
597 2, vms->memmap[VIRT_GIC_DIST].base,
598 2, vms->memmap[VIRT_GIC_DIST].size,
599 2, vms->memmap[VIRT_GIC_REDIST].base,
600 2, vms->memmap[VIRT_GIC_REDIST].size);
601 } else {
602 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
603 2, vms->memmap[VIRT_GIC_DIST].base,
604 2, vms->memmap[VIRT_GIC_DIST].size,
605 2, vms->memmap[VIRT_GIC_REDIST].base,
606 2, vms->memmap[VIRT_GIC_REDIST].size,
607 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
608 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
609 }
610
611 if (vms->virt) {
612 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
613 GIC_FDT_IRQ_TYPE_PPI,
614 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
615 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
616 }
617 } else {
618 /* 'cortex-a15-gic' means 'GIC v2' */
619 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
620 "arm,cortex-a15-gic");
621 if (!vms->virt) {
622 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
623 2, vms->memmap[VIRT_GIC_DIST].base,
624 2, vms->memmap[VIRT_GIC_DIST].size,
625 2, vms->memmap[VIRT_GIC_CPU].base,
626 2, vms->memmap[VIRT_GIC_CPU].size);
627 } else {
628 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
629 2, vms->memmap[VIRT_GIC_DIST].base,
630 2, vms->memmap[VIRT_GIC_DIST].size,
631 2, vms->memmap[VIRT_GIC_CPU].base,
632 2, vms->memmap[VIRT_GIC_CPU].size,
633 2, vms->memmap[VIRT_GIC_HYP].base,
634 2, vms->memmap[VIRT_GIC_HYP].size,
635 2, vms->memmap[VIRT_GIC_VCPU].base,
636 2, vms->memmap[VIRT_GIC_VCPU].size);
637 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
638 GIC_FDT_IRQ_TYPE_PPI,
639 INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
640 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
641 }
642 }
643
644 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", vms->gic_phandle);
645 g_free(nodename);
646 }
647
fdt_add_pmu_nodes(const VirtMachineState * vms)648 static void fdt_add_pmu_nodes(const VirtMachineState *vms)
649 {
650 ARMCPU *armcpu = ARM_CPU(first_cpu);
651 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
652 MachineState *ms = MACHINE(vms);
653
654 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
655 assert(!object_property_get_bool(OBJECT(armcpu), "pmu", NULL));
656 return;
657 }
658
659 if (vms->gic_version == VIRT_GIC_VERSION_2) {
660 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
661 GIC_FDT_IRQ_PPI_CPU_WIDTH,
662 (1 << MACHINE(vms)->smp.cpus) - 1);
663 }
664
665 qemu_fdt_add_subnode(ms->fdt, "/pmu");
666 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
667 const char compat[] = "arm,armv8-pmuv3";
668 qemu_fdt_setprop(ms->fdt, "/pmu", "compatible",
669 compat, sizeof(compat));
670 qemu_fdt_setprop_cells(ms->fdt, "/pmu", "interrupts",
671 GIC_FDT_IRQ_TYPE_PPI,
672 INTID_TO_PPI(VIRTUAL_PMU_IRQ), irqflags);
673 }
674 }
675
create_acpi_ged(VirtMachineState * vms)676 static inline DeviceState *create_acpi_ged(VirtMachineState *vms)
677 {
678 DeviceState *dev;
679 MachineState *ms = MACHINE(vms);
680 int irq = vms->irqmap[VIRT_ACPI_GED];
681 uint32_t event = ACPI_GED_PWR_DOWN_EVT;
682
683 if (ms->ram_slots) {
684 event |= ACPI_GED_MEM_HOTPLUG_EVT;
685 }
686
687 if (ms->nvdimms_state->is_enabled) {
688 event |= ACPI_GED_NVDIMM_HOTPLUG_EVT;
689 }
690
691 dev = qdev_new(TYPE_ACPI_GED);
692 qdev_prop_set_uint32(dev, "ged-event", event);
693 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
694
695 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].base);
696 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].base);
697 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, irq));
698
699 return dev;
700 }
701
create_its(VirtMachineState * vms)702 static void create_its(VirtMachineState *vms)
703 {
704 const char *itsclass = its_class_name();
705 DeviceState *dev;
706
707 if (!strcmp(itsclass, "arm-gicv3-its")) {
708 if (!vms->tcg_its) {
709 itsclass = NULL;
710 }
711 }
712
713 if (!itsclass) {
714 /* Do nothing if not supported */
715 return;
716 }
717
718 dev = qdev_new(itsclass);
719
720 object_property_set_link(OBJECT(dev), "parent-gicv3", OBJECT(vms->gic),
721 &error_abort);
722 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
723 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
724
725 fdt_add_its_gic_node(vms);
726 vms->msi_controller = VIRT_MSI_CTRL_ITS;
727 }
728
create_v2m(VirtMachineState * vms)729 static void create_v2m(VirtMachineState *vms)
730 {
731 int i;
732 int irq = vms->irqmap[VIRT_GIC_V2M];
733 DeviceState *dev;
734
735 dev = qdev_new("arm-gicv2m");
736 qdev_prop_set_uint32(dev, "base-spi", irq);
737 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
738 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
739 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
740
741 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
742 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
743 qdev_get_gpio_in(vms->gic, irq + i));
744 }
745
746 fdt_add_v2m_gic_node(vms);
747 vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
748 }
749
750 /*
751 * If the CPU has FEAT_NMI, then turn on the NMI support in the GICv3 too.
752 * It's permitted to have a configuration with NMI in the CPU (and thus the
753 * GICv3 CPU interface) but not in the distributor/redistributors, but it's
754 * not very useful.
755 */
gicv3_nmi_present(VirtMachineState * vms)756 static bool gicv3_nmi_present(VirtMachineState *vms)
757 {
758 ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0));
759
760 return tcg_enabled() && cpu_isar_feature(aa64_nmi, cpu) &&
761 (vms->gic_version != VIRT_GIC_VERSION_2);
762 }
763
create_gic(VirtMachineState * vms,MemoryRegion * mem)764 static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
765 {
766 MachineState *ms = MACHINE(vms);
767 /* We create a standalone GIC */
768 SysBusDevice *gicbusdev;
769 const char *gictype;
770 int i;
771 unsigned int smp_cpus = ms->smp.cpus;
772 uint32_t nb_redist_regions = 0;
773 int revision;
774
775 if (vms->gic_version == VIRT_GIC_VERSION_2) {
776 gictype = gic_class_name();
777 } else {
778 gictype = gicv3_class_name();
779 }
780
781 switch (vms->gic_version) {
782 case VIRT_GIC_VERSION_2:
783 revision = 2;
784 break;
785 case VIRT_GIC_VERSION_3:
786 revision = 3;
787 break;
788 case VIRT_GIC_VERSION_4:
789 revision = 4;
790 break;
791 default:
792 g_assert_not_reached();
793 }
794 vms->gic = qdev_new(gictype);
795 qdev_prop_set_uint32(vms->gic, "revision", revision);
796 qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus);
797 /* Note that the num-irq property counts both internal and external
798 * interrupts; there are always 32 of the former (mandated by GIC spec).
799 */
800 qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32);
801 if (!kvm_irqchip_in_kernel()) {
802 qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure);
803 }
804
805 if (vms->gic_version != VIRT_GIC_VERSION_2) {
806 QList *redist_region_count;
807 uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
808 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
809
810 nb_redist_regions = virt_gicv3_redist_region_count(vms);
811
812 redist_region_count = qlist_new();
813 qlist_append_int(redist_region_count, redist0_count);
814 if (nb_redist_regions == 2) {
815 uint32_t redist1_capacity =
816 virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
817
818 qlist_append_int(redist_region_count,
819 MIN(smp_cpus - redist0_count, redist1_capacity));
820 }
821 qdev_prop_set_array(vms->gic, "redist-region-count",
822 redist_region_count);
823
824 if (!kvm_irqchip_in_kernel()) {
825 if (vms->tcg_its) {
826 object_property_set_link(OBJECT(vms->gic), "sysmem",
827 OBJECT(mem), &error_fatal);
828 qdev_prop_set_bit(vms->gic, "has-lpi", true);
829 }
830 }
831 } else {
832 if (!kvm_irqchip_in_kernel()) {
833 qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
834 vms->virt);
835 }
836 }
837
838 if (gicv3_nmi_present(vms)) {
839 qdev_prop_set_bit(vms->gic, "has-nmi", true);
840 }
841
842 gicbusdev = SYS_BUS_DEVICE(vms->gic);
843 sysbus_realize_and_unref(gicbusdev, &error_fatal);
844 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
845 if (vms->gic_version != VIRT_GIC_VERSION_2) {
846 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
847 if (nb_redist_regions == 2) {
848 sysbus_mmio_map(gicbusdev, 2,
849 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
850 }
851 } else {
852 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
853 if (vms->virt) {
854 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
855 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
856 }
857 }
858
859 /* Wire the outputs from each CPU's generic timer and the GICv3
860 * maintenance interrupt signal to the appropriate GIC PPI inputs,
861 * and the GIC's IRQ/FIQ/VIRQ/VFIQ/NMI/VINMI interrupt outputs to the
862 * CPU's inputs.
863 */
864 for (i = 0; i < smp_cpus; i++) {
865 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
866 int intidbase = NUM_IRQS + i * GIC_INTERNAL;
867 /* Mapping from the output timer irq lines from the CPU to the
868 * GIC PPI inputs we use for the virt board.
869 */
870 const int timer_irq[] = {
871 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
872 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
873 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
874 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
875 [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
876 [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
877 [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
878 };
879
880 for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
881 qdev_connect_gpio_out(cpudev, irq,
882 qdev_get_gpio_in(vms->gic,
883 intidbase + timer_irq[irq]));
884 }
885
886 if (vms->gic_version != VIRT_GIC_VERSION_2) {
887 qemu_irq irq = qdev_get_gpio_in(vms->gic,
888 intidbase + ARCH_GIC_MAINT_IRQ);
889 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
890 0, irq);
891 } else if (vms->virt) {
892 qemu_irq irq = qdev_get_gpio_in(vms->gic,
893 intidbase + ARCH_GIC_MAINT_IRQ);
894 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
895 }
896
897 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
898 qdev_get_gpio_in(vms->gic, intidbase
899 + VIRTUAL_PMU_IRQ));
900
901 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
902 sysbus_connect_irq(gicbusdev, i + smp_cpus,
903 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
904 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
905 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
906 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
907 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
908
909 if (vms->gic_version != VIRT_GIC_VERSION_2) {
910 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus,
911 qdev_get_gpio_in(cpudev, ARM_CPU_NMI));
912 sysbus_connect_irq(gicbusdev, i + 5 * smp_cpus,
913 qdev_get_gpio_in(cpudev, ARM_CPU_VINMI));
914 }
915 }
916
917 fdt_add_gic_node(vms);
918
919 if (vms->gic_version != VIRT_GIC_VERSION_2 && vms->its) {
920 create_its(vms);
921 } else if (vms->gic_version == VIRT_GIC_VERSION_2) {
922 create_v2m(vms);
923 }
924 }
925
create_uart(const VirtMachineState * vms,int uart,MemoryRegion * mem,Chardev * chr,bool secure)926 static void create_uart(const VirtMachineState *vms, int uart,
927 MemoryRegion *mem, Chardev *chr, bool secure)
928 {
929 char *nodename;
930 hwaddr base = vms->memmap[uart].base;
931 hwaddr size = vms->memmap[uart].size;
932 int irq = vms->irqmap[uart];
933 const char compat[] = "arm,pl011\0arm,primecell";
934 const char clocknames[] = "uartclk\0apb_pclk";
935 DeviceState *dev = qdev_new(TYPE_PL011);
936 SysBusDevice *s = SYS_BUS_DEVICE(dev);
937 MachineState *ms = MACHINE(vms);
938
939 qdev_prop_set_chr(dev, "chardev", chr);
940 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
941 memory_region_add_subregion(mem, base,
942 sysbus_mmio_get_region(s, 0));
943 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
944
945 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
946 qemu_fdt_add_subnode(ms->fdt, nodename);
947 /* Note that we can't use setprop_string because of the embedded NUL */
948 qemu_fdt_setprop(ms->fdt, nodename, "compatible",
949 compat, sizeof(compat));
950 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
951 2, base, 2, size);
952 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
953 GIC_FDT_IRQ_TYPE_SPI, irq,
954 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
955 qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks",
956 vms->clock_phandle, vms->clock_phandle);
957 qemu_fdt_setprop(ms->fdt, nodename, "clock-names",
958 clocknames, sizeof(clocknames));
959
960 if (uart == VIRT_UART0) {
961 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
962 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
963 } else {
964 qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial1", nodename);
965 }
966 if (secure) {
967 /* Mark as not usable by the normal world */
968 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
969 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
970
971 qemu_fdt_setprop_string(ms->fdt, "/secure-chosen", "stdout-path",
972 nodename);
973 }
974
975 g_free(nodename);
976 }
977
create_rtc(const VirtMachineState * vms)978 static void create_rtc(const VirtMachineState *vms)
979 {
980 char *nodename;
981 hwaddr base = vms->memmap[VIRT_RTC].base;
982 hwaddr size = vms->memmap[VIRT_RTC].size;
983 int irq = vms->irqmap[VIRT_RTC];
984 const char compat[] = "arm,pl031\0arm,primecell";
985 MachineState *ms = MACHINE(vms);
986
987 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq));
988
989 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
990 qemu_fdt_add_subnode(ms->fdt, nodename);
991 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
992 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
993 2, base, 2, size);
994 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
995 GIC_FDT_IRQ_TYPE_SPI, irq,
996 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
997 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
998 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
999 g_free(nodename);
1000 }
1001
1002 static DeviceState *gpio_key_dev;
virt_powerdown_req(Notifier * n,void * opaque)1003 static void virt_powerdown_req(Notifier *n, void *opaque)
1004 {
1005 VirtMachineState *s = container_of(n, VirtMachineState, powerdown_notifier);
1006
1007 if (s->acpi_dev) {
1008 acpi_send_event(s->acpi_dev, ACPI_POWER_DOWN_STATUS);
1009 } else {
1010 /* use gpio Pin for power button event */
1011 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
1012 }
1013 }
1014
create_gpio_keys(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1015 static void create_gpio_keys(char *fdt, DeviceState *pl061_dev,
1016 uint32_t phandle)
1017 {
1018 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
1019 qdev_get_gpio_in(pl061_dev,
1020 GPIO_PIN_POWER_BUTTON));
1021
1022 qemu_fdt_add_subnode(fdt, "/gpio-keys");
1023 qemu_fdt_setprop_string(fdt, "/gpio-keys", "compatible", "gpio-keys");
1024
1025 qemu_fdt_add_subnode(fdt, "/gpio-keys/poweroff");
1026 qemu_fdt_setprop_string(fdt, "/gpio-keys/poweroff",
1027 "label", "GPIO Key Poweroff");
1028 qemu_fdt_setprop_cell(fdt, "/gpio-keys/poweroff", "linux,code",
1029 KEY_POWER);
1030 qemu_fdt_setprop_cells(fdt, "/gpio-keys/poweroff",
1031 "gpios", phandle, GPIO_PIN_POWER_BUTTON, 0);
1032 }
1033
1034 #define SECURE_GPIO_POWEROFF 0
1035 #define SECURE_GPIO_RESET 1
1036
create_secure_gpio_pwr(char * fdt,DeviceState * pl061_dev,uint32_t phandle)1037 static void create_secure_gpio_pwr(char *fdt, DeviceState *pl061_dev,
1038 uint32_t phandle)
1039 {
1040 DeviceState *gpio_pwr_dev;
1041
1042 /* gpio-pwr */
1043 gpio_pwr_dev = sysbus_create_simple("gpio-pwr", -1, NULL);
1044
1045 /* connect secure pl061 to gpio-pwr */
1046 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_RESET,
1047 qdev_get_gpio_in_named(gpio_pwr_dev, "reset", 0));
1048 qdev_connect_gpio_out(pl061_dev, SECURE_GPIO_POWEROFF,
1049 qdev_get_gpio_in_named(gpio_pwr_dev, "shutdown", 0));
1050
1051 qemu_fdt_add_subnode(fdt, "/gpio-poweroff");
1052 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "compatible",
1053 "gpio-poweroff");
1054 qemu_fdt_setprop_cells(fdt, "/gpio-poweroff",
1055 "gpios", phandle, SECURE_GPIO_POWEROFF, 0);
1056 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "status", "disabled");
1057 qemu_fdt_setprop_string(fdt, "/gpio-poweroff", "secure-status",
1058 "okay");
1059
1060 qemu_fdt_add_subnode(fdt, "/gpio-restart");
1061 qemu_fdt_setprop_string(fdt, "/gpio-restart", "compatible",
1062 "gpio-restart");
1063 qemu_fdt_setprop_cells(fdt, "/gpio-restart",
1064 "gpios", phandle, SECURE_GPIO_RESET, 0);
1065 qemu_fdt_setprop_string(fdt, "/gpio-restart", "status", "disabled");
1066 qemu_fdt_setprop_string(fdt, "/gpio-restart", "secure-status",
1067 "okay");
1068 }
1069
create_gpio_devices(const VirtMachineState * vms,int gpio,MemoryRegion * mem)1070 static void create_gpio_devices(const VirtMachineState *vms, int gpio,
1071 MemoryRegion *mem)
1072 {
1073 char *nodename;
1074 DeviceState *pl061_dev;
1075 hwaddr base = vms->memmap[gpio].base;
1076 hwaddr size = vms->memmap[gpio].size;
1077 int irq = vms->irqmap[gpio];
1078 const char compat[] = "arm,pl061\0arm,primecell";
1079 SysBusDevice *s;
1080 MachineState *ms = MACHINE(vms);
1081
1082 pl061_dev = qdev_new("pl061");
1083 /* Pull lines down to 0 if not driven by the PL061 */
1084 qdev_prop_set_uint32(pl061_dev, "pullups", 0);
1085 qdev_prop_set_uint32(pl061_dev, "pulldowns", 0xff);
1086 s = SYS_BUS_DEVICE(pl061_dev);
1087 sysbus_realize_and_unref(s, &error_fatal);
1088 memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0));
1089 sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq));
1090
1091 uint32_t phandle = qemu_fdt_alloc_phandle(ms->fdt);
1092 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
1093 qemu_fdt_add_subnode(ms->fdt, nodename);
1094 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1095 2, base, 2, size);
1096 qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
1097 qemu_fdt_setprop_cell(ms->fdt, nodename, "#gpio-cells", 2);
1098 qemu_fdt_setprop(ms->fdt, nodename, "gpio-controller", NULL, 0);
1099 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1100 GIC_FDT_IRQ_TYPE_SPI, irq,
1101 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
1102 qemu_fdt_setprop_cell(ms->fdt, nodename, "clocks", vms->clock_phandle);
1103 qemu_fdt_setprop_string(ms->fdt, nodename, "clock-names", "apb_pclk");
1104 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", phandle);
1105
1106 if (gpio != VIRT_GPIO) {
1107 /* Mark as not usable by the normal world */
1108 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1109 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1110 }
1111 g_free(nodename);
1112
1113 /* Child gpio devices */
1114 if (gpio == VIRT_GPIO) {
1115 create_gpio_keys(ms->fdt, pl061_dev, phandle);
1116 } else {
1117 create_secure_gpio_pwr(ms->fdt, pl061_dev, phandle);
1118 }
1119 }
1120
create_virtio_devices(const VirtMachineState * vms)1121 static void create_virtio_devices(const VirtMachineState *vms)
1122 {
1123 int i;
1124 hwaddr size = vms->memmap[VIRT_MMIO].size;
1125 MachineState *ms = MACHINE(vms);
1126
1127 /* We create the transports in forwards order. Since qbus_realize()
1128 * prepends (not appends) new child buses, the incrementing loop below will
1129 * create a list of virtio-mmio buses with decreasing base addresses.
1130 *
1131 * When a -device option is processed from the command line,
1132 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
1133 * order. The upshot is that -device options in increasing command line
1134 * order are mapped to virtio-mmio buses with decreasing base addresses.
1135 *
1136 * When this code was originally written, that arrangement ensured that the
1137 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
1138 * the first -device on the command line. (The end-to-end order is a
1139 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
1140 * guest kernel's name-to-address assignment strategy.)
1141 *
1142 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
1143 * the message, if not necessarily the code, of commit 70161ff336.
1144 * Therefore the loop now establishes the inverse of the original intent.
1145 *
1146 * Unfortunately, we can't counteract the kernel change by reversing the
1147 * loop; it would break existing command lines.
1148 *
1149 * In any case, the kernel makes no guarantee about the stability of
1150 * enumeration order of virtio devices (as demonstrated by it changing
1151 * between kernel versions). For reliable and stable identification
1152 * of disks users must use UUIDs or similar mechanisms.
1153 */
1154 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
1155 int irq = vms->irqmap[VIRT_MMIO] + i;
1156 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1157
1158 sysbus_create_simple("virtio-mmio", base,
1159 qdev_get_gpio_in(vms->gic, irq));
1160 }
1161
1162 /* We add dtb nodes in reverse order so that they appear in the finished
1163 * device tree lowest address first.
1164 *
1165 * Note that this mapping is independent of the loop above. The previous
1166 * loop influences virtio device to virtio transport assignment, whereas
1167 * this loop controls how virtio transports are laid out in the dtb.
1168 */
1169 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
1170 char *nodename;
1171 int irq = vms->irqmap[VIRT_MMIO] + i;
1172 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
1173
1174 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
1175 qemu_fdt_add_subnode(ms->fdt, nodename);
1176 qemu_fdt_setprop_string(ms->fdt, nodename,
1177 "compatible", "virtio,mmio");
1178 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1179 2, base, 2, size);
1180 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
1181 GIC_FDT_IRQ_TYPE_SPI, irq,
1182 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1183 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1184 g_free(nodename);
1185 }
1186 }
1187
1188 #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
1189
virt_flash_create1(VirtMachineState * vms,const char * name,const char * alias_prop_name)1190 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
1191 const char *name,
1192 const char *alias_prop_name)
1193 {
1194 /*
1195 * Create a single flash device. We use the same parameters as
1196 * the flash devices on the Versatile Express board.
1197 */
1198 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
1199
1200 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
1201 qdev_prop_set_uint8(dev, "width", 4);
1202 qdev_prop_set_uint8(dev, "device-width", 2);
1203 qdev_prop_set_bit(dev, "big-endian", false);
1204 qdev_prop_set_uint16(dev, "id0", 0x89);
1205 qdev_prop_set_uint16(dev, "id1", 0x18);
1206 qdev_prop_set_uint16(dev, "id2", 0x00);
1207 qdev_prop_set_uint16(dev, "id3", 0x00);
1208 qdev_prop_set_string(dev, "name", name);
1209 object_property_add_child(OBJECT(vms), name, OBJECT(dev));
1210 object_property_add_alias(OBJECT(vms), alias_prop_name,
1211 OBJECT(dev), "drive");
1212 return PFLASH_CFI01(dev);
1213 }
1214
virt_flash_create(VirtMachineState * vms)1215 static void virt_flash_create(VirtMachineState *vms)
1216 {
1217 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
1218 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
1219 }
1220
virt_flash_map1(PFlashCFI01 * flash,hwaddr base,hwaddr size,MemoryRegion * sysmem)1221 static void virt_flash_map1(PFlashCFI01 *flash,
1222 hwaddr base, hwaddr size,
1223 MemoryRegion *sysmem)
1224 {
1225 DeviceState *dev = DEVICE(flash);
1226
1227 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
1228 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
1229 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
1230 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1231
1232 memory_region_add_subregion(sysmem, base,
1233 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
1234 0));
1235 }
1236
virt_flash_map(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1237 static void virt_flash_map(VirtMachineState *vms,
1238 MemoryRegion *sysmem,
1239 MemoryRegion *secure_sysmem)
1240 {
1241 /*
1242 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
1243 * sysmem is the system memory space. secure_sysmem is the secure view
1244 * of the system, and the first flash device should be made visible only
1245 * there. The second flash device is visible to both secure and nonsecure.
1246 * If sysmem == secure_sysmem this means there is no separate Secure
1247 * address space and both flash devices are generally visible.
1248 */
1249 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1250 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1251
1252 virt_flash_map1(vms->flash[0], flashbase, flashsize,
1253 secure_sysmem);
1254 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
1255 sysmem);
1256 }
1257
virt_flash_fdt(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1258 static void virt_flash_fdt(VirtMachineState *vms,
1259 MemoryRegion *sysmem,
1260 MemoryRegion *secure_sysmem)
1261 {
1262 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
1263 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
1264 MachineState *ms = MACHINE(vms);
1265 char *nodename;
1266
1267 if (sysmem == secure_sysmem) {
1268 /* Report both flash devices as a single node in the DT */
1269 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
1270 qemu_fdt_add_subnode(ms->fdt, nodename);
1271 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1272 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1273 2, flashbase, 2, flashsize,
1274 2, flashbase + flashsize, 2, flashsize);
1275 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1276 g_free(nodename);
1277 } else {
1278 /*
1279 * Report the devices as separate nodes so we can mark one as
1280 * only visible to the secure world.
1281 */
1282 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
1283 qemu_fdt_add_subnode(ms->fdt, nodename);
1284 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1285 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1286 2, flashbase, 2, flashsize);
1287 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1288 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1289 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1290 g_free(nodename);
1291
1292 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase + flashsize);
1293 qemu_fdt_add_subnode(ms->fdt, nodename);
1294 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash");
1295 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1296 2, flashbase + flashsize, 2, flashsize);
1297 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4);
1298 g_free(nodename);
1299 }
1300 }
1301
virt_firmware_init(VirtMachineState * vms,MemoryRegion * sysmem,MemoryRegion * secure_sysmem)1302 static bool virt_firmware_init(VirtMachineState *vms,
1303 MemoryRegion *sysmem,
1304 MemoryRegion *secure_sysmem)
1305 {
1306 int i;
1307 const char *bios_name;
1308 BlockBackend *pflash_blk0;
1309
1310 /* Map legacy -drive if=pflash to machine properties */
1311 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1312 pflash_cfi01_legacy_drive(vms->flash[i],
1313 drive_get(IF_PFLASH, 0, i));
1314 }
1315
1316 virt_flash_map(vms, sysmem, secure_sysmem);
1317
1318 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1319
1320 bios_name = MACHINE(vms)->firmware;
1321 if (bios_name) {
1322 char *fname;
1323 MemoryRegion *mr;
1324 int image_size;
1325
1326 if (pflash_blk0) {
1327 error_report("The contents of the first flash device may be "
1328 "specified with -bios or with -drive if=pflash... "
1329 "but you cannot use both options at once");
1330 exit(1);
1331 }
1332
1333 /* Fall back to -bios */
1334
1335 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1336 if (!fname) {
1337 error_report("Could not find ROM image '%s'", bios_name);
1338 exit(1);
1339 }
1340 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1341 image_size = load_image_mr(fname, mr);
1342 g_free(fname);
1343 if (image_size < 0) {
1344 error_report("Could not load ROM image '%s'", bios_name);
1345 exit(1);
1346 }
1347 }
1348
1349 return pflash_blk0 || bios_name;
1350 }
1351
create_fw_cfg(const VirtMachineState * vms,AddressSpace * as)1352 static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1353 {
1354 MachineState *ms = MACHINE(vms);
1355 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1356 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1357 FWCfgState *fw_cfg;
1358 char *nodename;
1359
1360 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1361 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1362
1363 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1364 qemu_fdt_add_subnode(ms->fdt, nodename);
1365 qemu_fdt_setprop_string(ms->fdt, nodename,
1366 "compatible", "qemu,fw-cfg-mmio");
1367 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1368 2, base, 2, size);
1369 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1370 g_free(nodename);
1371 return fw_cfg;
1372 }
1373
create_pcie_irq_map(const MachineState * ms,uint32_t gic_phandle,int first_irq,const char * nodename)1374 static void create_pcie_irq_map(const MachineState *ms,
1375 uint32_t gic_phandle,
1376 int first_irq, const char *nodename)
1377 {
1378 int devfn, pin;
1379 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1380 uint32_t *irq_map = full_irq_map;
1381
1382 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1383 for (pin = 0; pin < 4; pin++) {
1384 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1385 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1386 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1387 int i;
1388
1389 uint32_t map[] = {
1390 devfn << 8, 0, 0, /* devfn */
1391 pin + 1, /* PCI pin */
1392 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1393
1394 /* Convert map to big endian */
1395 for (i = 0; i < 10; i++) {
1396 irq_map[i] = cpu_to_be32(map[i]);
1397 }
1398 irq_map += 10;
1399 }
1400 }
1401
1402 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map",
1403 full_irq_map, sizeof(full_irq_map));
1404
1405 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask",
1406 cpu_to_be16(PCI_DEVFN(3, 0)), /* Slot 3 */
1407 0, 0,
1408 0x7 /* PCI irq */);
1409 }
1410
create_smmu(const VirtMachineState * vms,PCIBus * bus)1411 static void create_smmu(const VirtMachineState *vms,
1412 PCIBus *bus)
1413 {
1414 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1415 char *node;
1416 const char compat[] = "arm,smmu-v3";
1417 int irq = vms->irqmap[VIRT_SMMU];
1418 int i;
1419 hwaddr base = vms->memmap[VIRT_SMMU].base;
1420 hwaddr size = vms->memmap[VIRT_SMMU].size;
1421 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1422 DeviceState *dev;
1423 MachineState *ms = MACHINE(vms);
1424
1425 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1426 return;
1427 }
1428
1429 dev = qdev_new(TYPE_ARM_SMMUV3);
1430
1431 if (!vmc->no_nested_smmu) {
1432 object_property_set_str(OBJECT(dev), "stage", "nested", &error_fatal);
1433 }
1434 object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(bus),
1435 &error_abort);
1436 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1437 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1438 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1439 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1440 qdev_get_gpio_in(vms->gic, irq + i));
1441 }
1442
1443 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1444 qemu_fdt_add_subnode(ms->fdt, node);
1445 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1446 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg", 2, base, 2, size);
1447
1448 qemu_fdt_setprop_cells(ms->fdt, node, "interrupts",
1449 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1450 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1451 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1452 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1453
1454 qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
1455 sizeof(irq_names));
1456
1457 qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
1458
1459 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1460
1461 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1462 g_free(node);
1463 }
1464
create_virtio_iommu_dt_bindings(VirtMachineState * vms)1465 static void create_virtio_iommu_dt_bindings(VirtMachineState *vms)
1466 {
1467 const char compat[] = "virtio,pci-iommu\0pci1af4,1057";
1468 uint16_t bdf = vms->virtio_iommu_bdf;
1469 MachineState *ms = MACHINE(vms);
1470 char *node;
1471
1472 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1473
1474 node = g_strdup_printf("%s/virtio_iommu@%x,%x", vms->pciehb_nodename,
1475 PCI_SLOT(bdf), PCI_FUNC(bdf));
1476 qemu_fdt_add_subnode(ms->fdt, node);
1477 qemu_fdt_setprop(ms->fdt, node, "compatible", compat, sizeof(compat));
1478 qemu_fdt_setprop_sized_cells(ms->fdt, node, "reg",
1479 1, bdf << 8, 1, 0, 1, 0,
1480 1, 0, 1, 0);
1481
1482 qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
1483 qemu_fdt_setprop_cell(ms->fdt, node, "phandle", vms->iommu_phandle);
1484 g_free(node);
1485
1486 qemu_fdt_setprop_cells(ms->fdt, vms->pciehb_nodename, "iommu-map",
1487 0x0, vms->iommu_phandle, 0x0, bdf,
1488 bdf + 1, vms->iommu_phandle, bdf + 1, 0xffff - bdf);
1489 }
1490
create_pcie(VirtMachineState * vms)1491 static void create_pcie(VirtMachineState *vms)
1492 {
1493 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1494 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1495 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1496 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1497 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1498 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1499 hwaddr base_ecam, size_ecam;
1500 hwaddr base = base_mmio;
1501 int nr_pcie_buses;
1502 int irq = vms->irqmap[VIRT_PCIE];
1503 MemoryRegion *mmio_alias;
1504 MemoryRegion *mmio_reg;
1505 MemoryRegion *ecam_alias;
1506 MemoryRegion *ecam_reg;
1507 DeviceState *dev;
1508 char *nodename;
1509 int i, ecam_id;
1510 PCIHostState *pci;
1511 MachineState *ms = MACHINE(vms);
1512 MachineClass *mc = MACHINE_GET_CLASS(ms);
1513
1514 dev = qdev_new(TYPE_GPEX_HOST);
1515 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1516
1517 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1518 base_ecam = vms->memmap[ecam_id].base;
1519 size_ecam = vms->memmap[ecam_id].size;
1520 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1521 /* Map only the first size_ecam bytes of ECAM space */
1522 ecam_alias = g_new0(MemoryRegion, 1);
1523 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1524 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1525 ecam_reg, 0, size_ecam);
1526 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1527
1528 /* Map the MMIO window into system address space so as to expose
1529 * the section of PCI MMIO space which starts at the same base address
1530 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1531 * the window).
1532 */
1533 mmio_alias = g_new0(MemoryRegion, 1);
1534 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1535 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1536 mmio_reg, base_mmio, size_mmio);
1537 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1538
1539 if (vms->highmem_mmio) {
1540 /* Map high MMIO space */
1541 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1542
1543 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1544 mmio_reg, base_mmio_high, size_mmio_high);
1545 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1546 high_mmio_alias);
1547 }
1548
1549 /* Map IO port space */
1550 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1551
1552 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1553 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
1554 qdev_get_gpio_in(vms->gic, irq + i));
1555 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1556 }
1557
1558 pci = PCI_HOST_BRIDGE(dev);
1559 pci->bypass_iommu = vms->default_bus_bypass_iommu;
1560 vms->bus = pci->bus;
1561 if (vms->bus) {
1562 pci_init_nic_devices(pci->bus, mc->default_nic);
1563 }
1564
1565 nodename = vms->pciehb_nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1566 qemu_fdt_add_subnode(ms->fdt, nodename);
1567 qemu_fdt_setprop_string(ms->fdt, nodename,
1568 "compatible", "pci-host-ecam-generic");
1569 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci");
1570 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3);
1571 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
1572 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
1573 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
1574 nr_pcie_buses - 1);
1575 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
1576
1577 if (vms->msi_phandle) {
1578 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
1579 0, vms->msi_phandle, 0, 0x10000);
1580 }
1581
1582 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
1583 2, base_ecam, 2, size_ecam);
1584
1585 if (vms->highmem_mmio) {
1586 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1587 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1588 2, base_pio, 2, size_pio,
1589 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1590 2, base_mmio, 2, size_mmio,
1591 1, FDT_PCI_RANGE_MMIO_64BIT,
1592 2, base_mmio_high,
1593 2, base_mmio_high, 2, size_mmio_high);
1594 } else {
1595 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
1596 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1597 2, base_pio, 2, size_pio,
1598 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1599 2, base_mmio, 2, size_mmio);
1600 }
1601
1602 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1);
1603 create_pcie_irq_map(ms, vms->gic_phandle, irq, nodename);
1604
1605 if (vms->iommu) {
1606 vms->iommu_phandle = qemu_fdt_alloc_phandle(ms->fdt);
1607
1608 switch (vms->iommu) {
1609 case VIRT_IOMMU_SMMUV3:
1610 create_smmu(vms, vms->bus);
1611 qemu_fdt_setprop_cells(ms->fdt, nodename, "iommu-map",
1612 0x0, vms->iommu_phandle, 0x0, 0x10000);
1613 break;
1614 default:
1615 g_assert_not_reached();
1616 }
1617 }
1618 }
1619
create_platform_bus(VirtMachineState * vms)1620 static void create_platform_bus(VirtMachineState *vms)
1621 {
1622 DeviceState *dev;
1623 SysBusDevice *s;
1624 int i;
1625 MemoryRegion *sysmem = get_system_memory();
1626
1627 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE);
1628 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE);
1629 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1630 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1631 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1632 vms->platform_bus_dev = dev;
1633
1634 s = SYS_BUS_DEVICE(dev);
1635 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1636 int irq = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1637 sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq));
1638 }
1639
1640 memory_region_add_subregion(sysmem,
1641 vms->memmap[VIRT_PLATFORM_BUS].base,
1642 sysbus_mmio_get_region(s, 0));
1643 }
1644
create_tag_ram(MemoryRegion * tag_sysmem,hwaddr base,hwaddr size,const char * name)1645 static void create_tag_ram(MemoryRegion *tag_sysmem,
1646 hwaddr base, hwaddr size,
1647 const char *name)
1648 {
1649 MemoryRegion *tagram = g_new(MemoryRegion, 1);
1650
1651 memory_region_init_ram(tagram, NULL, name, size / 32, &error_fatal);
1652 memory_region_add_subregion(tag_sysmem, base / 32, tagram);
1653 }
1654
create_secure_ram(VirtMachineState * vms,MemoryRegion * secure_sysmem,MemoryRegion * secure_tag_sysmem)1655 static void create_secure_ram(VirtMachineState *vms,
1656 MemoryRegion *secure_sysmem,
1657 MemoryRegion *secure_tag_sysmem)
1658 {
1659 MemoryRegion *secram = g_new(MemoryRegion, 1);
1660 char *nodename;
1661 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1662 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1663 MachineState *ms = MACHINE(vms);
1664
1665 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1666 &error_fatal);
1667 memory_region_add_subregion(secure_sysmem, base, secram);
1668
1669 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1670 qemu_fdt_add_subnode(ms->fdt, nodename);
1671 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory");
1672 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size);
1673 qemu_fdt_setprop_string(ms->fdt, nodename, "status", "disabled");
1674 qemu_fdt_setprop_string(ms->fdt, nodename, "secure-status", "okay");
1675
1676 if (secure_tag_sysmem) {
1677 create_tag_ram(secure_tag_sysmem, base, size, "mach-virt.secure-tag");
1678 }
1679
1680 g_free(nodename);
1681 }
1682
machvirt_dtb(const struct arm_boot_info * binfo,int * fdt_size)1683 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1684 {
1685 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1686 bootinfo);
1687 MachineState *ms = MACHINE(board);
1688
1689
1690 *fdt_size = board->fdt_size;
1691 return ms->fdt;
1692 }
1693
virt_build_smbios(VirtMachineState * vms)1694 static void virt_build_smbios(VirtMachineState *vms)
1695 {
1696 MachineClass *mc = MACHINE_GET_CLASS(vms);
1697 MachineState *ms = MACHINE(vms);
1698 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1699 uint8_t *smbios_tables, *smbios_anchor;
1700 size_t smbios_tables_len, smbios_anchor_len;
1701 struct smbios_phys_mem_area mem_array;
1702 const char *product = "QEMU Virtual Machine";
1703
1704 if (kvm_enabled()) {
1705 product = "KVM Virtual Machine";
1706 }
1707
1708 smbios_set_defaults("QEMU", product,
1709 vmc->smbios_old_sys_ver ? "1.0" : mc->name);
1710
1711 /* build the array of physical mem area from base_memmap */
1712 mem_array.address = vms->memmap[VIRT_MEM].base;
1713 mem_array.length = ms->ram_size;
1714
1715 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, &mem_array, 1,
1716 &smbios_tables, &smbios_tables_len,
1717 &smbios_anchor, &smbios_anchor_len,
1718 &error_fatal);
1719
1720 if (smbios_anchor) {
1721 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1722 smbios_tables, smbios_tables_len);
1723 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1724 smbios_anchor, smbios_anchor_len);
1725 }
1726 }
1727
1728 static
virt_machine_done(Notifier * notifier,void * data)1729 void virt_machine_done(Notifier *notifier, void *data)
1730 {
1731 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1732 machine_done);
1733 MachineState *ms = MACHINE(vms);
1734 ARMCPU *cpu = ARM_CPU(first_cpu);
1735 struct arm_boot_info *info = &vms->bootinfo;
1736 AddressSpace *as = arm_boot_address_space(cpu, info);
1737
1738 /*
1739 * If the user provided a dtb, we assume the dynamic sysbus nodes
1740 * already are integrated there. This corresponds to a use case where
1741 * the dynamic sysbus nodes are complex and their generation is not yet
1742 * supported. In that case the user can take charge of the guest dt
1743 * while qemu takes charge of the qom stuff.
1744 */
1745 if (info->dtb_filename == NULL) {
1746 platform_bus_add_all_fdt_nodes(ms->fdt, "/intc",
1747 vms->memmap[VIRT_PLATFORM_BUS].base,
1748 vms->memmap[VIRT_PLATFORM_BUS].size,
1749 vms->irqmap[VIRT_PLATFORM_BUS]);
1750 }
1751 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1752 exit(1);
1753 }
1754
1755 fw_cfg_add_extra_pci_roots(vms->bus, vms->fw_cfg);
1756
1757 virt_acpi_setup(vms);
1758 virt_build_smbios(vms);
1759 }
1760
virt_cpu_mp_affinity(VirtMachineState * vms,int idx)1761 static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1762 {
1763 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1764 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1765
1766 if (!vmc->disallow_affinity_adjustment) {
1767 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1768 * GIC's target-list limitations. 32-bit KVM hosts currently
1769 * always create clusters of 4 CPUs, but that is expected to
1770 * change when they gain support for gicv3. When KVM is enabled
1771 * it will override the changes we make here, therefore our
1772 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1773 * and to improve SGI efficiency.
1774 */
1775 if (vms->gic_version == VIRT_GIC_VERSION_2) {
1776 clustersz = GIC_TARGETLIST_BITS;
1777 } else {
1778 clustersz = GICV3_TARGETLIST_BITS;
1779 }
1780 }
1781 return arm_build_mp_affinity(idx, clustersz);
1782 }
1783
virt_get_high_memmap_enabled(VirtMachineState * vms,int index)1784 static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
1785 int index)
1786 {
1787 bool *enabled_array[] = {
1788 &vms->highmem_redists,
1789 &vms->highmem_ecam,
1790 &vms->highmem_mmio,
1791 };
1792
1793 assert(ARRAY_SIZE(extended_memmap) - VIRT_LOWMEMMAP_LAST ==
1794 ARRAY_SIZE(enabled_array));
1795 assert(index - VIRT_LOWMEMMAP_LAST < ARRAY_SIZE(enabled_array));
1796
1797 return enabled_array[index - VIRT_LOWMEMMAP_LAST];
1798 }
1799
virt_set_high_memmap(VirtMachineState * vms,hwaddr base,int pa_bits)1800 static void virt_set_high_memmap(VirtMachineState *vms,
1801 hwaddr base, int pa_bits)
1802 {
1803 hwaddr region_base, region_size;
1804 bool *region_enabled, fits;
1805 int i;
1806
1807 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1808 region_enabled = virt_get_high_memmap_enabled(vms, i);
1809 region_base = ROUND_UP(base, extended_memmap[i].size);
1810 region_size = extended_memmap[i].size;
1811
1812 vms->memmap[i].base = region_base;
1813 vms->memmap[i].size = region_size;
1814
1815 /*
1816 * Check each device to see if it fits in the PA space,
1817 * moving highest_gpa as we go. For compatibility, move
1818 * highest_gpa for disabled fitting devices as well, if
1819 * the compact layout has been disabled.
1820 *
1821 * For each device that doesn't fit, disable it.
1822 */
1823 fits = (region_base + region_size) <= BIT_ULL(pa_bits);
1824 *region_enabled &= fits;
1825 if (vms->highmem_compact && !*region_enabled) {
1826 continue;
1827 }
1828
1829 base = region_base + region_size;
1830 if (fits) {
1831 vms->highest_gpa = base - 1;
1832 }
1833 }
1834 }
1835
virt_set_memmap(VirtMachineState * vms,int pa_bits)1836 static void virt_set_memmap(VirtMachineState *vms, int pa_bits)
1837 {
1838 MachineState *ms = MACHINE(vms);
1839 hwaddr base, device_memory_base, device_memory_size, memtop;
1840 int i;
1841
1842 vms->memmap = extended_memmap;
1843
1844 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1845 vms->memmap[i] = base_memmap[i];
1846 }
1847
1848 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1849 error_report("unsupported number of memory slots: %"PRIu64,
1850 ms->ram_slots);
1851 exit(EXIT_FAILURE);
1852 }
1853
1854 /*
1855 * !highmem is exactly the same as limiting the PA space to 32bit,
1856 * irrespective of the underlying capabilities of the HW.
1857 */
1858 if (!vms->highmem) {
1859 pa_bits = 32;
1860 }
1861
1862 /*
1863 * We compute the base of the high IO region depending on the
1864 * amount of initial and device memory. The device memory start/size
1865 * is aligned on 1GiB. We never put the high IO region below 256GiB
1866 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1867 * The device region size assumes 1GiB page max alignment per slot.
1868 */
1869 device_memory_base =
1870 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1871 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1872
1873 /* Base address of the high IO region */
1874 memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1875 if (memtop > BIT_ULL(pa_bits)) {
1876 error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
1877 pa_bits, memtop - BIT_ULL(pa_bits));
1878 exit(EXIT_FAILURE);
1879 }
1880 if (base < device_memory_base) {
1881 error_report("maxmem/slots too huge");
1882 exit(EXIT_FAILURE);
1883 }
1884 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1885 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1886 }
1887
1888 /* We know for sure that at least the memory fits in the PA space */
1889 vms->highest_gpa = memtop - 1;
1890
1891 virt_set_high_memmap(vms, base, pa_bits);
1892
1893 if (device_memory_size > 0) {
1894 machine_memory_devices_init(ms, device_memory_base, device_memory_size);
1895 }
1896 }
1897
finalize_gic_version_do(const char * accel_name,VirtGICType gic_version,int gics_supported,unsigned int max_cpus)1898 static VirtGICType finalize_gic_version_do(const char *accel_name,
1899 VirtGICType gic_version,
1900 int gics_supported,
1901 unsigned int max_cpus)
1902 {
1903 /* Convert host/max/nosel to GIC version number */
1904 switch (gic_version) {
1905 case VIRT_GIC_VERSION_HOST:
1906 if (!kvm_enabled()) {
1907 error_report("gic-version=host requires KVM");
1908 exit(1);
1909 }
1910
1911 /* For KVM, gic-version=host means gic-version=max */
1912 return finalize_gic_version_do(accel_name, VIRT_GIC_VERSION_MAX,
1913 gics_supported, max_cpus);
1914 case VIRT_GIC_VERSION_MAX:
1915 if (gics_supported & VIRT_GIC_VERSION_4_MASK) {
1916 gic_version = VIRT_GIC_VERSION_4;
1917 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1918 gic_version = VIRT_GIC_VERSION_3;
1919 } else {
1920 gic_version = VIRT_GIC_VERSION_2;
1921 }
1922 break;
1923 case VIRT_GIC_VERSION_NOSEL:
1924 if ((gics_supported & VIRT_GIC_VERSION_2_MASK) &&
1925 max_cpus <= GIC_NCPU) {
1926 gic_version = VIRT_GIC_VERSION_2;
1927 } else if (gics_supported & VIRT_GIC_VERSION_3_MASK) {
1928 /*
1929 * in case the host does not support v2 emulation or
1930 * the end-user requested more than 8 VCPUs we now default
1931 * to v3. In any case defaulting to v2 would be broken.
1932 */
1933 gic_version = VIRT_GIC_VERSION_3;
1934 } else if (max_cpus > GIC_NCPU) {
1935 error_report("%s only supports GICv2 emulation but more than 8 "
1936 "vcpus are requested", accel_name);
1937 exit(1);
1938 }
1939 break;
1940 case VIRT_GIC_VERSION_2:
1941 case VIRT_GIC_VERSION_3:
1942 case VIRT_GIC_VERSION_4:
1943 break;
1944 }
1945
1946 /* Check chosen version is effectively supported */
1947 switch (gic_version) {
1948 case VIRT_GIC_VERSION_2:
1949 if (!(gics_supported & VIRT_GIC_VERSION_2_MASK)) {
1950 error_report("%s does not support GICv2 emulation", accel_name);
1951 exit(1);
1952 }
1953 break;
1954 case VIRT_GIC_VERSION_3:
1955 if (!(gics_supported & VIRT_GIC_VERSION_3_MASK)) {
1956 error_report("%s does not support GICv3 emulation", accel_name);
1957 exit(1);
1958 }
1959 break;
1960 case VIRT_GIC_VERSION_4:
1961 if (!(gics_supported & VIRT_GIC_VERSION_4_MASK)) {
1962 error_report("%s does not support GICv4 emulation, is virtualization=on?",
1963 accel_name);
1964 exit(1);
1965 }
1966 break;
1967 default:
1968 error_report("logic error in finalize_gic_version");
1969 exit(1);
1970 break;
1971 }
1972
1973 return gic_version;
1974 }
1975
1976 /*
1977 * finalize_gic_version - Determines the final gic_version
1978 * according to the gic-version property
1979 *
1980 * Default GIC type is v2
1981 */
finalize_gic_version(VirtMachineState * vms)1982 static void finalize_gic_version(VirtMachineState *vms)
1983 {
1984 const char *accel_name = current_accel_name();
1985 unsigned int max_cpus = MACHINE(vms)->smp.max_cpus;
1986 int gics_supported = 0;
1987
1988 /* Determine which GIC versions the current environment supports */
1989 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1990 int probe_bitmap = kvm_arm_vgic_probe();
1991
1992 if (!probe_bitmap) {
1993 error_report("Unable to determine GIC version supported by host");
1994 exit(1);
1995 }
1996
1997 if (probe_bitmap & KVM_ARM_VGIC_V2) {
1998 gics_supported |= VIRT_GIC_VERSION_2_MASK;
1999 }
2000 if (probe_bitmap & KVM_ARM_VGIC_V3) {
2001 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2002 }
2003 } else if (kvm_enabled() && !kvm_irqchip_in_kernel()) {
2004 /* KVM w/o kernel irqchip can only deal with GICv2 */
2005 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2006 accel_name = "KVM with kernel-irqchip=off";
2007 } else if (tcg_enabled() || hvf_enabled() || qtest_enabled()) {
2008 gics_supported |= VIRT_GIC_VERSION_2_MASK;
2009 if (module_object_class_by_name("arm-gicv3")) {
2010 gics_supported |= VIRT_GIC_VERSION_3_MASK;
2011 if (vms->virt) {
2012 /* GICv4 only makes sense if CPU has EL2 */
2013 gics_supported |= VIRT_GIC_VERSION_4_MASK;
2014 }
2015 }
2016 } else {
2017 error_report("Unsupported accelerator, can not determine GIC support");
2018 exit(1);
2019 }
2020
2021 /*
2022 * Then convert helpers like host/max to concrete GIC versions and ensure
2023 * the desired version is supported
2024 */
2025 vms->gic_version = finalize_gic_version_do(accel_name, vms->gic_version,
2026 gics_supported, max_cpus);
2027 }
2028
2029 /*
2030 * virt_cpu_post_init() must be called after the CPUs have
2031 * been realized and the GIC has been created.
2032 */
virt_cpu_post_init(VirtMachineState * vms,MemoryRegion * sysmem)2033 static void virt_cpu_post_init(VirtMachineState *vms, MemoryRegion *sysmem)
2034 {
2035 int max_cpus = MACHINE(vms)->smp.max_cpus;
2036 bool aarch64, pmu, steal_time;
2037 CPUState *cpu;
2038
2039 aarch64 = object_property_get_bool(OBJECT(first_cpu), "aarch64", NULL);
2040 pmu = object_property_get_bool(OBJECT(first_cpu), "pmu", NULL);
2041 steal_time = object_property_get_bool(OBJECT(first_cpu),
2042 "kvm-steal-time", NULL);
2043
2044 if (kvm_enabled()) {
2045 hwaddr pvtime_reg_base = vms->memmap[VIRT_PVTIME].base;
2046 hwaddr pvtime_reg_size = vms->memmap[VIRT_PVTIME].size;
2047
2048 if (steal_time) {
2049 MemoryRegion *pvtime = g_new(MemoryRegion, 1);
2050 hwaddr pvtime_size = max_cpus * PVTIME_SIZE_PER_CPU;
2051
2052 /* The memory region size must be a multiple of host page size. */
2053 pvtime_size = REAL_HOST_PAGE_ALIGN(pvtime_size);
2054
2055 if (pvtime_size > pvtime_reg_size) {
2056 error_report("pvtime requires a %" HWADDR_PRId
2057 " byte memory region for %d CPUs,"
2058 " but only %" HWADDR_PRId " has been reserved",
2059 pvtime_size, max_cpus, pvtime_reg_size);
2060 exit(1);
2061 }
2062
2063 memory_region_init_ram(pvtime, NULL, "pvtime", pvtime_size, NULL);
2064 memory_region_add_subregion(sysmem, pvtime_reg_base, pvtime);
2065 }
2066
2067 CPU_FOREACH(cpu) {
2068 if (pmu) {
2069 assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
2070 if (kvm_irqchip_in_kernel()) {
2071 kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
2072 }
2073 kvm_arm_pmu_init(ARM_CPU(cpu));
2074 }
2075 if (steal_time) {
2076 kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
2077 + cpu->cpu_index
2078 * PVTIME_SIZE_PER_CPU);
2079 }
2080 }
2081 } else {
2082 if (aarch64 && vms->highmem) {
2083 int requested_pa_size = 64 - clz64(vms->highest_gpa);
2084 int pamax = arm_pamax(ARM_CPU(first_cpu));
2085
2086 if (pamax < requested_pa_size) {
2087 error_report("VCPU supports less PA bits (%d) than "
2088 "requested by the memory map (%d)",
2089 pamax, requested_pa_size);
2090 exit(1);
2091 }
2092 }
2093 }
2094 }
2095
machvirt_init(MachineState * machine)2096 static void machvirt_init(MachineState *machine)
2097 {
2098 VirtMachineState *vms = VIRT_MACHINE(machine);
2099 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
2100 MachineClass *mc = MACHINE_GET_CLASS(machine);
2101 const CPUArchIdList *possible_cpus;
2102 MemoryRegion *sysmem = get_system_memory();
2103 MemoryRegion *secure_sysmem = NULL;
2104 MemoryRegion *tag_sysmem = NULL;
2105 MemoryRegion *secure_tag_sysmem = NULL;
2106 int n, virt_max_cpus;
2107 bool firmware_loaded;
2108 bool aarch64 = true;
2109 bool has_ged = !vmc->no_ged;
2110 unsigned int smp_cpus = machine->smp.cpus;
2111 unsigned int max_cpus = machine->smp.max_cpus;
2112
2113 possible_cpus = mc->possible_cpu_arch_ids(machine);
2114
2115 /*
2116 * In accelerated mode, the memory map is computed earlier in kvm_type()
2117 * for Linux, or hvf_get_physical_address_range() for macOS to create a
2118 * VM with the right number of IPA bits.
2119 */
2120 if (!vms->memmap) {
2121 Object *cpuobj;
2122 ARMCPU *armcpu;
2123 int pa_bits;
2124
2125 /*
2126 * Instantiate a temporary CPU object to find out about what
2127 * we are about to deal with. Once this is done, get rid of
2128 * the object.
2129 */
2130 cpuobj = object_new(possible_cpus->cpus[0].type);
2131 armcpu = ARM_CPU(cpuobj);
2132
2133 pa_bits = arm_pamax(armcpu);
2134
2135 object_unref(cpuobj);
2136
2137 virt_set_memmap(vms, pa_bits);
2138 }
2139
2140 /* We can probe only here because during property set
2141 * KVM is not available yet
2142 */
2143 finalize_gic_version(vms);
2144
2145 if (vms->secure) {
2146 /*
2147 * The Secure view of the world is the same as the NonSecure,
2148 * but with a few extra devices. Create it as a container region
2149 * containing the system memory at low priority; any secure-only
2150 * devices go in at higher priority and take precedence.
2151 */
2152 secure_sysmem = g_new(MemoryRegion, 1);
2153 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
2154 UINT64_MAX);
2155 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
2156 }
2157
2158 firmware_loaded = virt_firmware_init(vms, sysmem,
2159 secure_sysmem ?: sysmem);
2160
2161 /* If we have an EL3 boot ROM then the assumption is that it will
2162 * implement PSCI itself, so disable QEMU's internal implementation
2163 * so it doesn't get in the way. Instead of starting secondary
2164 * CPUs in PSCI powerdown state we will start them all running and
2165 * let the boot ROM sort them out.
2166 * The usual case is that we do use QEMU's PSCI implementation;
2167 * if the guest has EL2 then we will use SMC as the conduit,
2168 * and otherwise we will use HVC (for backwards compatibility and
2169 * because if we're using KVM then we must use HVC).
2170 */
2171 if (vms->secure && firmware_loaded) {
2172 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
2173 } else if (vms->virt) {
2174 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
2175 } else {
2176 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
2177 }
2178
2179 /*
2180 * The maximum number of CPUs depends on the GIC version, or on how
2181 * many redistributors we can fit into the memory map (which in turn
2182 * depends on whether this is a GICv3 or v4).
2183 */
2184 if (vms->gic_version == VIRT_GIC_VERSION_2) {
2185 virt_max_cpus = GIC_NCPU;
2186 } else {
2187 virt_max_cpus = virt_redist_capacity(vms, VIRT_GIC_REDIST);
2188 if (vms->highmem_redists) {
2189 virt_max_cpus += virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
2190 }
2191 }
2192
2193 if (max_cpus > virt_max_cpus) {
2194 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
2195 "supported by machine 'mach-virt' (%d)",
2196 max_cpus, virt_max_cpus);
2197 if (vms->gic_version != VIRT_GIC_VERSION_2 && !vms->highmem_redists) {
2198 error_printf("Try 'highmem-redists=on' for more CPUs\n");
2199 }
2200
2201 exit(1);
2202 }
2203
2204 if (vms->secure && (kvm_enabled() || hvf_enabled())) {
2205 error_report("mach-virt: %s does not support providing "
2206 "Security extensions (TrustZone) to the guest CPU",
2207 current_accel_name());
2208 exit(1);
2209 }
2210
2211 if (vms->virt && (kvm_enabled() || hvf_enabled())) {
2212 error_report("mach-virt: %s does not support providing "
2213 "Virtualization extensions to the guest CPU",
2214 current_accel_name());
2215 exit(1);
2216 }
2217
2218 if (vms->mte && hvf_enabled()) {
2219 error_report("mach-virt: %s does not support providing "
2220 "MTE to the guest CPU",
2221 current_accel_name());
2222 exit(1);
2223 }
2224
2225 create_fdt(vms);
2226
2227 assert(possible_cpus->len == max_cpus);
2228 for (n = 0; n < possible_cpus->len; n++) {
2229 Object *cpuobj;
2230 CPUState *cs;
2231
2232 if (n >= smp_cpus) {
2233 break;
2234 }
2235
2236 cpuobj = object_new(possible_cpus->cpus[n].type);
2237 object_property_set_int(cpuobj, "mp-affinity",
2238 possible_cpus->cpus[n].arch_id, NULL);
2239
2240 cs = CPU(cpuobj);
2241 cs->cpu_index = n;
2242
2243 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
2244 &error_fatal);
2245
2246 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
2247
2248 if (!vms->secure) {
2249 object_property_set_bool(cpuobj, "has_el3", false, NULL);
2250 }
2251
2252 if (!vms->virt && object_property_find(cpuobj, "has_el2")) {
2253 object_property_set_bool(cpuobj, "has_el2", false, NULL);
2254 }
2255
2256 if (vmc->kvm_no_adjvtime &&
2257 object_property_find(cpuobj, "kvm-no-adjvtime")) {
2258 object_property_set_bool(cpuobj, "kvm-no-adjvtime", true, NULL);
2259 }
2260
2261 if (vmc->no_kvm_steal_time &&
2262 object_property_find(cpuobj, "kvm-steal-time")) {
2263 object_property_set_bool(cpuobj, "kvm-steal-time", false, NULL);
2264 }
2265
2266 if (vmc->no_pmu && object_property_find(cpuobj, "pmu")) {
2267 object_property_set_bool(cpuobj, "pmu", false, NULL);
2268 }
2269
2270 if (vmc->no_tcg_lpa2 && object_property_find(cpuobj, "lpa2")) {
2271 object_property_set_bool(cpuobj, "lpa2", false, NULL);
2272 }
2273
2274 if (object_property_find(cpuobj, "reset-cbar")) {
2275 object_property_set_int(cpuobj, "reset-cbar",
2276 vms->memmap[VIRT_CPUPERIPHS].base,
2277 &error_abort);
2278 }
2279
2280 object_property_set_link(cpuobj, "memory", OBJECT(sysmem),
2281 &error_abort);
2282 if (vms->secure) {
2283 object_property_set_link(cpuobj, "secure-memory",
2284 OBJECT(secure_sysmem), &error_abort);
2285 }
2286
2287 if (vms->mte) {
2288 if (tcg_enabled()) {
2289 /* Create the memory region only once, but link to all cpus. */
2290 if (!tag_sysmem) {
2291 /*
2292 * The property exists only if MemTag is supported.
2293 * If it is, we must allocate the ram to back that up.
2294 */
2295 if (!object_property_find(cpuobj, "tag-memory")) {
2296 error_report("MTE requested, but not supported "
2297 "by the guest CPU");
2298 exit(1);
2299 }
2300
2301 tag_sysmem = g_new(MemoryRegion, 1);
2302 memory_region_init(tag_sysmem, OBJECT(machine),
2303 "tag-memory", UINT64_MAX / 32);
2304
2305 if (vms->secure) {
2306 secure_tag_sysmem = g_new(MemoryRegion, 1);
2307 memory_region_init(secure_tag_sysmem, OBJECT(machine),
2308 "secure-tag-memory",
2309 UINT64_MAX / 32);
2310
2311 /* As with ram, secure-tag takes precedence over tag. */
2312 memory_region_add_subregion_overlap(secure_tag_sysmem,
2313 0, tag_sysmem, -1);
2314 }
2315 }
2316
2317 object_property_set_link(cpuobj, "tag-memory",
2318 OBJECT(tag_sysmem), &error_abort);
2319 if (vms->secure) {
2320 object_property_set_link(cpuobj, "secure-tag-memory",
2321 OBJECT(secure_tag_sysmem),
2322 &error_abort);
2323 }
2324 } else if (kvm_enabled()) {
2325 if (!kvm_arm_mte_supported()) {
2326 error_report("MTE requested, but not supported by KVM");
2327 exit(1);
2328 }
2329 kvm_arm_enable_mte(cpuobj, &error_abort);
2330 } else {
2331 error_report("MTE requested, but not supported ");
2332 exit(1);
2333 }
2334 }
2335
2336 qdev_realize(DEVICE(cpuobj), NULL, &error_fatal);
2337 object_unref(cpuobj);
2338 }
2339
2340 /* Now we've created the CPUs we can see if they have the hypvirt timer */
2341 vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() &&
2342 !vmc->no_ns_el2_virt_timer_irq;
2343
2344 fdt_add_timer_nodes(vms);
2345 fdt_add_cpu_nodes(vms);
2346
2347 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base,
2348 machine->ram);
2349
2350 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
2351
2352 create_gic(vms, sysmem);
2353
2354 virt_cpu_post_init(vms, sysmem);
2355
2356 fdt_add_pmu_nodes(vms);
2357
2358 /*
2359 * The first UART always exists. If the security extensions are
2360 * enabled, the second UART also always exists. Otherwise, it only exists
2361 * if a backend is configured explicitly via '-serial <backend>'.
2362 * This avoids potentially breaking existing user setups that expect
2363 * only one NonSecure UART to be present (for instance, older EDK2
2364 * binaries).
2365 *
2366 * The nodes end up in the DTB in reverse order of creation, so we must
2367 * create UART0 last to ensure it appears as the first node in the DTB,
2368 * for compatibility with guest software that just iterates through the
2369 * DTB to find the first UART, as older versions of EDK2 do.
2370 * DTB readers that follow the spec, as Linux does, should honour the
2371 * aliases node information and /chosen/stdout-path regardless of
2372 * the order that nodes appear in the DTB.
2373 *
2374 * For similar back-compatibility reasons, if UART1 is the secure UART
2375 * we create it second (and so it appears first in the DTB), because
2376 * that's what QEMU has always done.
2377 */
2378 if (!vms->secure) {
2379 Chardev *serial1 = serial_hd(1);
2380
2381 if (serial1) {
2382 vms->second_ns_uart_present = true;
2383 create_uart(vms, VIRT_UART1, sysmem, serial1, false);
2384 }
2385 }
2386 create_uart(vms, VIRT_UART0, sysmem, serial_hd(0), false);
2387 if (vms->secure) {
2388 create_uart(vms, VIRT_UART1, secure_sysmem, serial_hd(1), true);
2389 }
2390
2391 if (vms->secure) {
2392 create_secure_ram(vms, secure_sysmem, secure_tag_sysmem);
2393 }
2394
2395 if (tag_sysmem) {
2396 create_tag_ram(tag_sysmem, vms->memmap[VIRT_MEM].base,
2397 machine->ram_size, "mach-virt.tag");
2398 }
2399
2400 vms->highmem_ecam &= (!firmware_loaded || aarch64);
2401
2402 create_rtc(vms);
2403
2404 create_pcie(vms);
2405
2406 if (has_ged && aarch64 && firmware_loaded && virt_is_acpi_enabled(vms)) {
2407 vms->acpi_dev = create_acpi_ged(vms);
2408 } else {
2409 create_gpio_devices(vms, VIRT_GPIO, sysmem);
2410 }
2411
2412 if (vms->secure && !vmc->no_secure_gpio) {
2413 create_gpio_devices(vms, VIRT_SECURE_GPIO, secure_sysmem);
2414 }
2415
2416 /* connect powerdown request */
2417 vms->powerdown_notifier.notify = virt_powerdown_req;
2418 qemu_register_powerdown_notifier(&vms->powerdown_notifier);
2419
2420 /* Create mmio transports, so the user can create virtio backends
2421 * (which will be automatically plugged in to the transports). If
2422 * no backend is created the transport will just sit harmlessly idle.
2423 */
2424 create_virtio_devices(vms);
2425
2426 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
2427 rom_set_fw(vms->fw_cfg);
2428
2429 create_platform_bus(vms);
2430
2431 if (machine->nvdimms_state->is_enabled) {
2432 const struct AcpiGenericAddress arm_virt_nvdimm_acpi_dsmio = {
2433 .space_id = AML_AS_SYSTEM_MEMORY,
2434 .address = vms->memmap[VIRT_NVDIMM_ACPI].base,
2435 .bit_width = NVDIMM_ACPI_IO_LEN << 3
2436 };
2437
2438 nvdimm_init_acpi_state(machine->nvdimms_state, sysmem,
2439 arm_virt_nvdimm_acpi_dsmio,
2440 vms->fw_cfg, OBJECT(vms));
2441 }
2442
2443 vms->bootinfo.ram_size = machine->ram_size;
2444 vms->bootinfo.board_id = -1;
2445 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
2446 vms->bootinfo.get_dtb = machvirt_dtb;
2447 vms->bootinfo.skip_dtb_autoload = true;
2448 vms->bootinfo.firmware_loaded = firmware_loaded;
2449 vms->bootinfo.psci_conduit = vms->psci_conduit;
2450 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
2451
2452 vms->machine_done.notify = virt_machine_done;
2453 qemu_add_machine_init_done_notifier(&vms->machine_done);
2454 }
2455
virt_get_secure(Object * obj,Error ** errp)2456 static bool virt_get_secure(Object *obj, Error **errp)
2457 {
2458 VirtMachineState *vms = VIRT_MACHINE(obj);
2459
2460 return vms->secure;
2461 }
2462
virt_set_secure(Object * obj,bool value,Error ** errp)2463 static void virt_set_secure(Object *obj, bool value, Error **errp)
2464 {
2465 VirtMachineState *vms = VIRT_MACHINE(obj);
2466
2467 vms->secure = value;
2468 }
2469
virt_get_virt(Object * obj,Error ** errp)2470 static bool virt_get_virt(Object *obj, Error **errp)
2471 {
2472 VirtMachineState *vms = VIRT_MACHINE(obj);
2473
2474 return vms->virt;
2475 }
2476
virt_set_virt(Object * obj,bool value,Error ** errp)2477 static void virt_set_virt(Object *obj, bool value, Error **errp)
2478 {
2479 VirtMachineState *vms = VIRT_MACHINE(obj);
2480
2481 vms->virt = value;
2482 }
2483
virt_get_highmem(Object * obj,Error ** errp)2484 static bool virt_get_highmem(Object *obj, Error **errp)
2485 {
2486 VirtMachineState *vms = VIRT_MACHINE(obj);
2487
2488 return vms->highmem;
2489 }
2490
virt_set_highmem(Object * obj,bool value,Error ** errp)2491 static void virt_set_highmem(Object *obj, bool value, Error **errp)
2492 {
2493 VirtMachineState *vms = VIRT_MACHINE(obj);
2494
2495 vms->highmem = value;
2496 }
2497
virt_get_compact_highmem(Object * obj,Error ** errp)2498 static bool virt_get_compact_highmem(Object *obj, Error **errp)
2499 {
2500 VirtMachineState *vms = VIRT_MACHINE(obj);
2501
2502 return vms->highmem_compact;
2503 }
2504
virt_set_compact_highmem(Object * obj,bool value,Error ** errp)2505 static void virt_set_compact_highmem(Object *obj, bool value, Error **errp)
2506 {
2507 VirtMachineState *vms = VIRT_MACHINE(obj);
2508
2509 vms->highmem_compact = value;
2510 }
2511
virt_get_highmem_redists(Object * obj,Error ** errp)2512 static bool virt_get_highmem_redists(Object *obj, Error **errp)
2513 {
2514 VirtMachineState *vms = VIRT_MACHINE(obj);
2515
2516 return vms->highmem_redists;
2517 }
2518
virt_set_highmem_redists(Object * obj,bool value,Error ** errp)2519 static void virt_set_highmem_redists(Object *obj, bool value, Error **errp)
2520 {
2521 VirtMachineState *vms = VIRT_MACHINE(obj);
2522
2523 vms->highmem_redists = value;
2524 }
2525
virt_get_highmem_ecam(Object * obj,Error ** errp)2526 static bool virt_get_highmem_ecam(Object *obj, Error **errp)
2527 {
2528 VirtMachineState *vms = VIRT_MACHINE(obj);
2529
2530 return vms->highmem_ecam;
2531 }
2532
virt_set_highmem_ecam(Object * obj,bool value,Error ** errp)2533 static void virt_set_highmem_ecam(Object *obj, bool value, Error **errp)
2534 {
2535 VirtMachineState *vms = VIRT_MACHINE(obj);
2536
2537 vms->highmem_ecam = value;
2538 }
2539
virt_get_highmem_mmio(Object * obj,Error ** errp)2540 static bool virt_get_highmem_mmio(Object *obj, Error **errp)
2541 {
2542 VirtMachineState *vms = VIRT_MACHINE(obj);
2543
2544 return vms->highmem_mmio;
2545 }
2546
virt_set_highmem_mmio(Object * obj,bool value,Error ** errp)2547 static void virt_set_highmem_mmio(Object *obj, bool value, Error **errp)
2548 {
2549 VirtMachineState *vms = VIRT_MACHINE(obj);
2550
2551 vms->highmem_mmio = value;
2552 }
2553
2554
virt_get_its(Object * obj,Error ** errp)2555 static bool virt_get_its(Object *obj, Error **errp)
2556 {
2557 VirtMachineState *vms = VIRT_MACHINE(obj);
2558
2559 return vms->its;
2560 }
2561
virt_set_its(Object * obj,bool value,Error ** errp)2562 static void virt_set_its(Object *obj, bool value, Error **errp)
2563 {
2564 VirtMachineState *vms = VIRT_MACHINE(obj);
2565
2566 vms->its = value;
2567 }
2568
virt_get_dtb_randomness(Object * obj,Error ** errp)2569 static bool virt_get_dtb_randomness(Object *obj, Error **errp)
2570 {
2571 VirtMachineState *vms = VIRT_MACHINE(obj);
2572
2573 return vms->dtb_randomness;
2574 }
2575
virt_set_dtb_randomness(Object * obj,bool value,Error ** errp)2576 static void virt_set_dtb_randomness(Object *obj, bool value, Error **errp)
2577 {
2578 VirtMachineState *vms = VIRT_MACHINE(obj);
2579
2580 vms->dtb_randomness = value;
2581 }
2582
virt_get_oem_id(Object * obj,Error ** errp)2583 static char *virt_get_oem_id(Object *obj, Error **errp)
2584 {
2585 VirtMachineState *vms = VIRT_MACHINE(obj);
2586
2587 return g_strdup(vms->oem_id);
2588 }
2589
virt_set_oem_id(Object * obj,const char * value,Error ** errp)2590 static void virt_set_oem_id(Object *obj, const char *value, Error **errp)
2591 {
2592 VirtMachineState *vms = VIRT_MACHINE(obj);
2593 size_t len = strlen(value);
2594
2595 if (len > 6) {
2596 error_setg(errp,
2597 "User specified oem-id value is bigger than 6 bytes in size");
2598 return;
2599 }
2600
2601 strncpy(vms->oem_id, value, 6);
2602 }
2603
virt_get_oem_table_id(Object * obj,Error ** errp)2604 static char *virt_get_oem_table_id(Object *obj, Error **errp)
2605 {
2606 VirtMachineState *vms = VIRT_MACHINE(obj);
2607
2608 return g_strdup(vms->oem_table_id);
2609 }
2610
virt_set_oem_table_id(Object * obj,const char * value,Error ** errp)2611 static void virt_set_oem_table_id(Object *obj, const char *value,
2612 Error **errp)
2613 {
2614 VirtMachineState *vms = VIRT_MACHINE(obj);
2615 size_t len = strlen(value);
2616
2617 if (len > 8) {
2618 error_setg(errp,
2619 "User specified oem-table-id value is bigger than 8 bytes in size");
2620 return;
2621 }
2622 strncpy(vms->oem_table_id, value, 8);
2623 }
2624
2625
virt_is_acpi_enabled(VirtMachineState * vms)2626 bool virt_is_acpi_enabled(VirtMachineState *vms)
2627 {
2628 if (vms->acpi == ON_OFF_AUTO_OFF) {
2629 return false;
2630 }
2631 return true;
2632 }
2633
virt_get_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2634 static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
2635 void *opaque, Error **errp)
2636 {
2637 VirtMachineState *vms = VIRT_MACHINE(obj);
2638 OnOffAuto acpi = vms->acpi;
2639
2640 visit_type_OnOffAuto(v, name, &acpi, errp);
2641 }
2642
virt_set_acpi(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)2643 static void virt_set_acpi(Object *obj, Visitor *v, const char *name,
2644 void *opaque, Error **errp)
2645 {
2646 VirtMachineState *vms = VIRT_MACHINE(obj);
2647
2648 visit_type_OnOffAuto(v, name, &vms->acpi, errp);
2649 }
2650
virt_get_ras(Object * obj,Error ** errp)2651 static bool virt_get_ras(Object *obj, Error **errp)
2652 {
2653 VirtMachineState *vms = VIRT_MACHINE(obj);
2654
2655 return vms->ras;
2656 }
2657
virt_set_ras(Object * obj,bool value,Error ** errp)2658 static void virt_set_ras(Object *obj, bool value, Error **errp)
2659 {
2660 VirtMachineState *vms = VIRT_MACHINE(obj);
2661
2662 vms->ras = value;
2663 }
2664
virt_get_mte(Object * obj,Error ** errp)2665 static bool virt_get_mte(Object *obj, Error **errp)
2666 {
2667 VirtMachineState *vms = VIRT_MACHINE(obj);
2668
2669 return vms->mte;
2670 }
2671
virt_set_mte(Object * obj,bool value,Error ** errp)2672 static void virt_set_mte(Object *obj, bool value, Error **errp)
2673 {
2674 VirtMachineState *vms = VIRT_MACHINE(obj);
2675
2676 vms->mte = value;
2677 }
2678
virt_get_gic_version(Object * obj,Error ** errp)2679 static char *virt_get_gic_version(Object *obj, Error **errp)
2680 {
2681 VirtMachineState *vms = VIRT_MACHINE(obj);
2682 const char *val;
2683
2684 switch (vms->gic_version) {
2685 case VIRT_GIC_VERSION_4:
2686 val = "4";
2687 break;
2688 case VIRT_GIC_VERSION_3:
2689 val = "3";
2690 break;
2691 default:
2692 val = "2";
2693 break;
2694 }
2695 return g_strdup(val);
2696 }
2697
virt_set_gic_version(Object * obj,const char * value,Error ** errp)2698 static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
2699 {
2700 VirtMachineState *vms = VIRT_MACHINE(obj);
2701
2702 if (!strcmp(value, "4")) {
2703 vms->gic_version = VIRT_GIC_VERSION_4;
2704 } else if (!strcmp(value, "3")) {
2705 vms->gic_version = VIRT_GIC_VERSION_3;
2706 } else if (!strcmp(value, "2")) {
2707 vms->gic_version = VIRT_GIC_VERSION_2;
2708 } else if (!strcmp(value, "host")) {
2709 vms->gic_version = VIRT_GIC_VERSION_HOST; /* Will probe later */
2710 } else if (!strcmp(value, "max")) {
2711 vms->gic_version = VIRT_GIC_VERSION_MAX; /* Will probe later */
2712 } else {
2713 error_setg(errp, "Invalid gic-version value");
2714 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
2715 }
2716 }
2717
virt_get_iommu(Object * obj,Error ** errp)2718 static char *virt_get_iommu(Object *obj, Error **errp)
2719 {
2720 VirtMachineState *vms = VIRT_MACHINE(obj);
2721
2722 switch (vms->iommu) {
2723 case VIRT_IOMMU_NONE:
2724 return g_strdup("none");
2725 case VIRT_IOMMU_SMMUV3:
2726 return g_strdup("smmuv3");
2727 default:
2728 g_assert_not_reached();
2729 }
2730 }
2731
virt_set_iommu(Object * obj,const char * value,Error ** errp)2732 static void virt_set_iommu(Object *obj, const char *value, Error **errp)
2733 {
2734 VirtMachineState *vms = VIRT_MACHINE(obj);
2735
2736 if (!strcmp(value, "smmuv3")) {
2737 vms->iommu = VIRT_IOMMU_SMMUV3;
2738 } else if (!strcmp(value, "none")) {
2739 vms->iommu = VIRT_IOMMU_NONE;
2740 } else {
2741 error_setg(errp, "Invalid iommu value");
2742 error_append_hint(errp, "Valid values are none, smmuv3.\n");
2743 }
2744 }
2745
virt_get_default_bus_bypass_iommu(Object * obj,Error ** errp)2746 static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
2747 {
2748 VirtMachineState *vms = VIRT_MACHINE(obj);
2749
2750 return vms->default_bus_bypass_iommu;
2751 }
2752
virt_set_default_bus_bypass_iommu(Object * obj,bool value,Error ** errp)2753 static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
2754 Error **errp)
2755 {
2756 VirtMachineState *vms = VIRT_MACHINE(obj);
2757
2758 vms->default_bus_bypass_iommu = value;
2759 }
2760
2761 static CpuInstanceProperties
virt_cpu_index_to_props(MachineState * ms,unsigned cpu_index)2762 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
2763 {
2764 MachineClass *mc = MACHINE_GET_CLASS(ms);
2765 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
2766
2767 assert(cpu_index < possible_cpus->len);
2768 return possible_cpus->cpus[cpu_index].props;
2769 }
2770
virt_get_default_cpu_node_id(const MachineState * ms,int idx)2771 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
2772 {
2773 int64_t socket_id = ms->possible_cpus->cpus[idx].props.socket_id;
2774
2775 return socket_id % ms->numa_state->num_nodes;
2776 }
2777
virt_possible_cpu_arch_ids(MachineState * ms)2778 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
2779 {
2780 int n;
2781 unsigned int max_cpus = ms->smp.max_cpus;
2782 VirtMachineState *vms = VIRT_MACHINE(ms);
2783 MachineClass *mc = MACHINE_GET_CLASS(vms);
2784
2785 if (ms->possible_cpus) {
2786 assert(ms->possible_cpus->len == max_cpus);
2787 return ms->possible_cpus;
2788 }
2789
2790 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
2791 sizeof(CPUArchId) * max_cpus);
2792 ms->possible_cpus->len = max_cpus;
2793 for (n = 0; n < ms->possible_cpus->len; n++) {
2794 ms->possible_cpus->cpus[n].type = ms->cpu_type;
2795 ms->possible_cpus->cpus[n].arch_id =
2796 virt_cpu_mp_affinity(vms, n);
2797
2798 assert(!mc->smp_props.dies_supported);
2799 ms->possible_cpus->cpus[n].props.has_socket_id = true;
2800 ms->possible_cpus->cpus[n].props.socket_id =
2801 n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads);
2802 ms->possible_cpus->cpus[n].props.has_cluster_id = true;
2803 ms->possible_cpus->cpus[n].props.cluster_id =
2804 (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters;
2805 ms->possible_cpus->cpus[n].props.has_core_id = true;
2806 ms->possible_cpus->cpus[n].props.core_id =
2807 (n / ms->smp.threads) % ms->smp.cores;
2808 ms->possible_cpus->cpus[n].props.has_thread_id = true;
2809 ms->possible_cpus->cpus[n].props.thread_id =
2810 n % ms->smp.threads;
2811 }
2812 return ms->possible_cpus;
2813 }
2814
virt_memory_pre_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2815 static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
2816 Error **errp)
2817 {
2818 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2819 const MachineState *ms = MACHINE(hotplug_dev);
2820 const bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2821
2822 if (!vms->acpi_dev) {
2823 error_setg(errp,
2824 "memory hotplug is not enabled: missing acpi-ged device");
2825 return;
2826 }
2827
2828 if (vms->mte) {
2829 error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
2830 return;
2831 }
2832
2833 if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
2834 error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
2835 return;
2836 }
2837
2838 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), errp);
2839 }
2840
virt_memory_plug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2841 static void virt_memory_plug(HotplugHandler *hotplug_dev,
2842 DeviceState *dev, Error **errp)
2843 {
2844 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2845 MachineState *ms = MACHINE(hotplug_dev);
2846 bool is_nvdimm = object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM);
2847
2848 pc_dimm_plug(PC_DIMM(dev), MACHINE(vms));
2849
2850 if (is_nvdimm) {
2851 nvdimm_plug(ms->nvdimms_state);
2852 }
2853
2854 hotplug_handler_plug(HOTPLUG_HANDLER(vms->acpi_dev),
2855 dev, &error_abort);
2856 }
2857
virt_machine_device_pre_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2858 static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
2859 DeviceState *dev, Error **errp)
2860 {
2861 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2862
2863 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2864 virt_memory_pre_plug(hotplug_dev, dev, errp);
2865 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2866 virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2867 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2868 hwaddr db_start = 0, db_end = 0;
2869 QList *reserved_regions;
2870 char *resv_prop_str;
2871
2872 if (vms->iommu != VIRT_IOMMU_NONE) {
2873 error_setg(errp, "virt machine does not support multiple IOMMUs");
2874 return;
2875 }
2876
2877 switch (vms->msi_controller) {
2878 case VIRT_MSI_CTRL_NONE:
2879 return;
2880 case VIRT_MSI_CTRL_ITS:
2881 /* GITS_TRANSLATER page */
2882 db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
2883 db_end = base_memmap[VIRT_GIC_ITS].base +
2884 base_memmap[VIRT_GIC_ITS].size - 1;
2885 break;
2886 case VIRT_MSI_CTRL_GICV2M:
2887 /* MSI_SETSPI_NS page */
2888 db_start = base_memmap[VIRT_GIC_V2M].base;
2889 db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
2890 break;
2891 }
2892 resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
2893 db_start, db_end,
2894 VIRTIO_IOMMU_RESV_MEM_T_MSI);
2895
2896 reserved_regions = qlist_new();
2897 qlist_append_str(reserved_regions, resv_prop_str);
2898 qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
2899 g_free(resv_prop_str);
2900 }
2901 }
2902
virt_machine_device_plug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2903 static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
2904 DeviceState *dev, Error **errp)
2905 {
2906 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2907
2908 if (vms->platform_bus_dev) {
2909 MachineClass *mc = MACHINE_GET_CLASS(vms);
2910
2911 if (device_is_dynamic_sysbus(mc, dev)) {
2912 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
2913 SYS_BUS_DEVICE(dev));
2914 }
2915 }
2916
2917 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2918 virt_memory_plug(hotplug_dev, dev, errp);
2919 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2920 virtio_md_pci_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2921 }
2922
2923 if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
2924 PCIDevice *pdev = PCI_DEVICE(dev);
2925
2926 vms->iommu = VIRT_IOMMU_VIRTIO;
2927 vms->virtio_iommu_bdf = pci_get_bdf(pdev);
2928 create_virtio_iommu_dt_bindings(vms);
2929 }
2930 }
2931
virt_dimm_unplug_request(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2932 static void virt_dimm_unplug_request(HotplugHandler *hotplug_dev,
2933 DeviceState *dev, Error **errp)
2934 {
2935 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2936
2937 if (!vms->acpi_dev) {
2938 error_setg(errp,
2939 "memory hotplug is not enabled: missing acpi-ged device");
2940 return;
2941 }
2942
2943 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
2944 error_setg(errp, "nvdimm device hot unplug is not supported yet.");
2945 return;
2946 }
2947
2948 hotplug_handler_unplug_request(HOTPLUG_HANDLER(vms->acpi_dev), dev,
2949 errp);
2950 }
2951
virt_dimm_unplug(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2952 static void virt_dimm_unplug(HotplugHandler *hotplug_dev,
2953 DeviceState *dev, Error **errp)
2954 {
2955 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
2956 Error *local_err = NULL;
2957
2958 hotplug_handler_unplug(HOTPLUG_HANDLER(vms->acpi_dev), dev, &local_err);
2959 if (local_err) {
2960 goto out;
2961 }
2962
2963 pc_dimm_unplug(PC_DIMM(dev), MACHINE(vms));
2964 qdev_unrealize(dev);
2965
2966 out:
2967 error_propagate(errp, local_err);
2968 }
2969
virt_machine_device_unplug_request_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2970 static void virt_machine_device_unplug_request_cb(HotplugHandler *hotplug_dev,
2971 DeviceState *dev, Error **errp)
2972 {
2973 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2974 virt_dimm_unplug_request(hotplug_dev, dev, errp);
2975 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2976 virtio_md_pci_unplug_request(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev),
2977 errp);
2978 } else {
2979 error_setg(errp, "device unplug request for unsupported device"
2980 " type: %s", object_get_typename(OBJECT(dev)));
2981 }
2982 }
2983
virt_machine_device_unplug_cb(HotplugHandler * hotplug_dev,DeviceState * dev,Error ** errp)2984 static void virt_machine_device_unplug_cb(HotplugHandler *hotplug_dev,
2985 DeviceState *dev, Error **errp)
2986 {
2987 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
2988 virt_dimm_unplug(hotplug_dev, dev, errp);
2989 } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI)) {
2990 virtio_md_pci_unplug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
2991 } else {
2992 error_setg(errp, "virt: device unplug for unsupported device"
2993 " type: %s", object_get_typename(OBJECT(dev)));
2994 }
2995 }
2996
virt_machine_get_hotplug_handler(MachineState * machine,DeviceState * dev)2997 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
2998 DeviceState *dev)
2999 {
3000 MachineClass *mc = MACHINE_GET_CLASS(machine);
3001
3002 if (device_is_dynamic_sysbus(mc, dev) ||
3003 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) ||
3004 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_MD_PCI) ||
3005 object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
3006 return HOTPLUG_HANDLER(machine);
3007 }
3008 return NULL;
3009 }
3010
3011 /*
3012 * for arm64 kvm_type [7-0] encodes the requested number of bits
3013 * in the IPA address space
3014 */
virt_kvm_type(MachineState * ms,const char * type_str)3015 static int virt_kvm_type(MachineState *ms, const char *type_str)
3016 {
3017 VirtMachineState *vms = VIRT_MACHINE(ms);
3018 int max_vm_pa_size, requested_pa_size;
3019 bool fixed_ipa;
3020
3021 max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms, &fixed_ipa);
3022
3023 /* we freeze the memory map to compute the highest gpa */
3024 virt_set_memmap(vms, max_vm_pa_size);
3025
3026 requested_pa_size = 64 - clz64(vms->highest_gpa);
3027
3028 /*
3029 * KVM requires the IPA size to be at least 32 bits.
3030 */
3031 if (requested_pa_size < 32) {
3032 requested_pa_size = 32;
3033 }
3034
3035 if (requested_pa_size > max_vm_pa_size) {
3036 error_report("-m and ,maxmem option values "
3037 "require an IPA range (%d bits) larger than "
3038 "the one supported by the host (%d bits)",
3039 requested_pa_size, max_vm_pa_size);
3040 return -1;
3041 }
3042 /*
3043 * We return the requested PA log size, unless KVM only supports
3044 * the implicit legacy 40b IPA setting, in which case the kvm_type
3045 * must be 0.
3046 */
3047 return fixed_ipa ? 0 : requested_pa_size;
3048 }
3049
virt_hvf_get_physical_address_range(MachineState * ms)3050 static int virt_hvf_get_physical_address_range(MachineState *ms)
3051 {
3052 VirtMachineState *vms = VIRT_MACHINE(ms);
3053
3054 int default_ipa_size = hvf_arm_get_default_ipa_bit_size();
3055 int max_ipa_size = hvf_arm_get_max_ipa_bit_size();
3056
3057 /* We freeze the memory map to compute the highest gpa */
3058 virt_set_memmap(vms, max_ipa_size);
3059
3060 int requested_ipa_size = 64 - clz64(vms->highest_gpa);
3061
3062 /*
3063 * If we're <= the default IPA size just use the default.
3064 * If we're above the default but below the maximum, round up to
3065 * the maximum. hvf_arm_get_max_ipa_bit_size() conveniently only
3066 * returns values that are valid ARM PARange values.
3067 */
3068 if (requested_ipa_size <= default_ipa_size) {
3069 requested_ipa_size = default_ipa_size;
3070 } else if (requested_ipa_size <= max_ipa_size) {
3071 requested_ipa_size = max_ipa_size;
3072 } else {
3073 error_report("-m and ,maxmem option values "
3074 "require an IPA range (%d bits) larger than "
3075 "the one supported by the host (%d bits)",
3076 requested_ipa_size, max_ipa_size);
3077 return -1;
3078 }
3079
3080 return requested_ipa_size;
3081 }
3082
virt_machine_class_init(ObjectClass * oc,void * data)3083 static void virt_machine_class_init(ObjectClass *oc, void *data)
3084 {
3085 MachineClass *mc = MACHINE_CLASS(oc);
3086 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
3087 static const char * const valid_cpu_types[] = {
3088 #ifdef CONFIG_TCG
3089 ARM_CPU_TYPE_NAME("cortex-a7"),
3090 ARM_CPU_TYPE_NAME("cortex-a15"),
3091 #ifdef TARGET_AARCH64
3092 ARM_CPU_TYPE_NAME("cortex-a35"),
3093 ARM_CPU_TYPE_NAME("cortex-a55"),
3094 ARM_CPU_TYPE_NAME("cortex-a72"),
3095 ARM_CPU_TYPE_NAME("cortex-a76"),
3096 ARM_CPU_TYPE_NAME("cortex-a710"),
3097 ARM_CPU_TYPE_NAME("a64fx"),
3098 ARM_CPU_TYPE_NAME("neoverse-n1"),
3099 ARM_CPU_TYPE_NAME("neoverse-v1"),
3100 ARM_CPU_TYPE_NAME("neoverse-n2"),
3101 #endif /* TARGET_AARCH64 */
3102 #endif /* CONFIG_TCG */
3103 #ifdef TARGET_AARCH64
3104 ARM_CPU_TYPE_NAME("cortex-a53"),
3105 ARM_CPU_TYPE_NAME("cortex-a57"),
3106 #if defined(CONFIG_KVM) || defined(CONFIG_HVF)
3107 ARM_CPU_TYPE_NAME("host"),
3108 #endif /* CONFIG_KVM || CONFIG_HVF */
3109 #endif /* TARGET_AARCH64 */
3110 ARM_CPU_TYPE_NAME("max"),
3111 NULL
3112 };
3113
3114 mc->init = machvirt_init;
3115 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
3116 * The value may be reduced later when we have more information about the
3117 * configuration of the particular instance.
3118 */
3119 mc->max_cpus = 512;
3120 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
3121 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
3122 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
3123 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
3124 #ifdef CONFIG_TPM
3125 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS);
3126 #endif
3127 mc->block_default_type = IF_VIRTIO;
3128 mc->no_cdrom = 1;
3129 mc->pci_allow_0_address = true;
3130 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
3131 mc->minimum_page_bits = 12;
3132 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
3133 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
3134 #ifdef CONFIG_TCG
3135 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
3136 #else
3137 mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
3138 #endif
3139 mc->valid_cpu_types = valid_cpu_types;
3140 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
3141 mc->kvm_type = virt_kvm_type;
3142 mc->hvf_get_physical_address_range = virt_hvf_get_physical_address_range;
3143 assert(!mc->get_hotplug_handler);
3144 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
3145 hc->pre_plug = virt_machine_device_pre_plug_cb;
3146 hc->plug = virt_machine_device_plug_cb;
3147 hc->unplug_request = virt_machine_device_unplug_request_cb;
3148 hc->unplug = virt_machine_device_unplug_cb;
3149 mc->nvdimm_supported = true;
3150 mc->smp_props.clusters_supported = true;
3151 mc->auto_enable_numa_with_memhp = true;
3152 mc->auto_enable_numa_with_memdev = true;
3153 /* platform instead of architectural choice */
3154 mc->cpu_cluster_has_numa_boundary = true;
3155 mc->default_ram_id = "mach-virt.ram";
3156 mc->default_nic = "virtio-net-pci";
3157
3158 object_class_property_add(oc, "acpi", "OnOffAuto",
3159 virt_get_acpi, virt_set_acpi,
3160 NULL, NULL);
3161 object_class_property_set_description(oc, "acpi",
3162 "Enable ACPI");
3163 object_class_property_add_bool(oc, "secure", virt_get_secure,
3164 virt_set_secure);
3165 object_class_property_set_description(oc, "secure",
3166 "Set on/off to enable/disable the ARM "
3167 "Security Extensions (TrustZone)");
3168
3169 object_class_property_add_bool(oc, "virtualization", virt_get_virt,
3170 virt_set_virt);
3171 object_class_property_set_description(oc, "virtualization",
3172 "Set on/off to enable/disable emulating a "
3173 "guest CPU which implements the ARM "
3174 "Virtualization Extensions");
3175
3176 object_class_property_add_bool(oc, "highmem", virt_get_highmem,
3177 virt_set_highmem);
3178 object_class_property_set_description(oc, "highmem",
3179 "Set on/off to enable/disable using "
3180 "physical address space above 32 bits");
3181
3182 object_class_property_add_bool(oc, "compact-highmem",
3183 virt_get_compact_highmem,
3184 virt_set_compact_highmem);
3185 object_class_property_set_description(oc, "compact-highmem",
3186 "Set on/off to enable/disable compact "
3187 "layout for high memory regions");
3188
3189 object_class_property_add_bool(oc, "highmem-redists",
3190 virt_get_highmem_redists,
3191 virt_set_highmem_redists);
3192 object_class_property_set_description(oc, "highmem-redists",
3193 "Set on/off to enable/disable high "
3194 "memory region for GICv3 or GICv4 "
3195 "redistributor");
3196
3197 object_class_property_add_bool(oc, "highmem-ecam",
3198 virt_get_highmem_ecam,
3199 virt_set_highmem_ecam);
3200 object_class_property_set_description(oc, "highmem-ecam",
3201 "Set on/off to enable/disable high "
3202 "memory region for PCI ECAM");
3203
3204 object_class_property_add_bool(oc, "highmem-mmio",
3205 virt_get_highmem_mmio,
3206 virt_set_highmem_mmio);
3207 object_class_property_set_description(oc, "highmem-mmio",
3208 "Set on/off to enable/disable high "
3209 "memory region for PCI MMIO");
3210
3211 object_class_property_add_str(oc, "gic-version", virt_get_gic_version,
3212 virt_set_gic_version);
3213 object_class_property_set_description(oc, "gic-version",
3214 "Set GIC version. "
3215 "Valid values are 2, 3, 4, host and max");
3216
3217 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_iommu);
3218 object_class_property_set_description(oc, "iommu",
3219 "Set the IOMMU type. "
3220 "Valid values are none and smmuv3");
3221
3222 object_class_property_add_bool(oc, "default-bus-bypass-iommu",
3223 virt_get_default_bus_bypass_iommu,
3224 virt_set_default_bus_bypass_iommu);
3225 object_class_property_set_description(oc, "default-bus-bypass-iommu",
3226 "Set on/off to enable/disable "
3227 "bypass_iommu for default root bus");
3228
3229 object_class_property_add_bool(oc, "ras", virt_get_ras,
3230 virt_set_ras);
3231 object_class_property_set_description(oc, "ras",
3232 "Set on/off to enable/disable reporting host memory errors "
3233 "to a KVM guest using ACPI and guest external abort exceptions");
3234
3235 object_class_property_add_bool(oc, "mte", virt_get_mte, virt_set_mte);
3236 object_class_property_set_description(oc, "mte",
3237 "Set on/off to enable/disable emulating a "
3238 "guest CPU which implements the ARM "
3239 "Memory Tagging Extension");
3240
3241 object_class_property_add_bool(oc, "its", virt_get_its,
3242 virt_set_its);
3243 object_class_property_set_description(oc, "its",
3244 "Set on/off to enable/disable "
3245 "ITS instantiation");
3246
3247 object_class_property_add_bool(oc, "dtb-randomness",
3248 virt_get_dtb_randomness,
3249 virt_set_dtb_randomness);
3250 object_class_property_set_description(oc, "dtb-randomness",
3251 "Set off to disable passing random or "
3252 "non-deterministic dtb nodes to guest");
3253
3254 object_class_property_add_bool(oc, "dtb-kaslr-seed",
3255 virt_get_dtb_randomness,
3256 virt_set_dtb_randomness);
3257 object_class_property_set_description(oc, "dtb-kaslr-seed",
3258 "Deprecated synonym of dtb-randomness");
3259
3260 object_class_property_add_str(oc, "x-oem-id",
3261 virt_get_oem_id,
3262 virt_set_oem_id);
3263 object_class_property_set_description(oc, "x-oem-id",
3264 "Override the default value of field OEMID "
3265 "in ACPI table header."
3266 "The string may be up to 6 bytes in size");
3267
3268
3269 object_class_property_add_str(oc, "x-oem-table-id",
3270 virt_get_oem_table_id,
3271 virt_set_oem_table_id);
3272 object_class_property_set_description(oc, "x-oem-table-id",
3273 "Override the default value of field OEM Table ID "
3274 "in ACPI table header."
3275 "The string may be up to 8 bytes in size");
3276
3277 }
3278
virt_instance_init(Object * obj)3279 static void virt_instance_init(Object *obj)
3280 {
3281 VirtMachineState *vms = VIRT_MACHINE(obj);
3282 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
3283
3284 /* EL3 is disabled by default on virt: this makes us consistent
3285 * between KVM and TCG for this board, and it also allows us to
3286 * boot UEFI blobs which assume no TrustZone support.
3287 */
3288 vms->secure = false;
3289
3290 /* EL2 is also disabled by default, for similar reasons */
3291 vms->virt = false;
3292
3293 /* High memory is enabled by default */
3294 vms->highmem = true;
3295 vms->highmem_compact = !vmc->no_highmem_compact;
3296 vms->gic_version = VIRT_GIC_VERSION_NOSEL;
3297
3298 vms->highmem_ecam = !vmc->no_highmem_ecam;
3299 vms->highmem_mmio = true;
3300 vms->highmem_redists = true;
3301
3302 if (vmc->no_its) {
3303 vms->its = false;
3304 } else {
3305 /* Default allows ITS instantiation */
3306 vms->its = true;
3307
3308 if (vmc->no_tcg_its) {
3309 vms->tcg_its = false;
3310 } else {
3311 vms->tcg_its = true;
3312 }
3313 }
3314
3315 /* Default disallows iommu instantiation */
3316 vms->iommu = VIRT_IOMMU_NONE;
3317
3318 /* The default root bus is attached to iommu by default */
3319 vms->default_bus_bypass_iommu = false;
3320
3321 /* Default disallows RAS instantiation */
3322 vms->ras = false;
3323
3324 /* MTE is disabled by default. */
3325 vms->mte = false;
3326
3327 /* Supply kaslr-seed and rng-seed by default */
3328 vms->dtb_randomness = true;
3329
3330 vms->irqmap = a15irqmap;
3331
3332 virt_flash_create(vms);
3333
3334 vms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6);
3335 vms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8);
3336 }
3337
3338 static const TypeInfo virt_machine_info = {
3339 .name = TYPE_VIRT_MACHINE,
3340 .parent = TYPE_MACHINE,
3341 .abstract = true,
3342 .instance_size = sizeof(VirtMachineState),
3343 .class_size = sizeof(VirtMachineClass),
3344 .class_init = virt_machine_class_init,
3345 .instance_init = virt_instance_init,
3346 .interfaces = (InterfaceInfo[]) {
3347 { TYPE_HOTPLUG_HANDLER },
3348 { }
3349 },
3350 };
3351
machvirt_machine_init(void)3352 static void machvirt_machine_init(void)
3353 {
3354 type_register_static(&virt_machine_info);
3355 }
3356 type_init(machvirt_machine_init);
3357
virt_machine_9_2_options(MachineClass * mc)3358 static void virt_machine_9_2_options(MachineClass *mc)
3359 {
3360 }
3361 DEFINE_VIRT_MACHINE_AS_LATEST(9, 2)
3362
virt_machine_9_1_options(MachineClass * mc)3363 static void virt_machine_9_1_options(MachineClass *mc)
3364 {
3365 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3366
3367 virt_machine_9_2_options(mc);
3368 compat_props_add(mc->compat_props, hw_compat_9_1, hw_compat_9_1_len);
3369 /* 9.1 and earlier have only a stage-1 SMMU, not a nested s1+2 one */
3370 vmc->no_nested_smmu = true;
3371 }
3372 DEFINE_VIRT_MACHINE(9, 1)
3373
virt_machine_9_0_options(MachineClass * mc)3374 static void virt_machine_9_0_options(MachineClass *mc)
3375 {
3376 virt_machine_9_1_options(mc);
3377 mc->smbios_memory_device_size = 16 * GiB;
3378 compat_props_add(mc->compat_props, hw_compat_9_0, hw_compat_9_0_len);
3379 }
3380 DEFINE_VIRT_MACHINE(9, 0)
3381
virt_machine_8_2_options(MachineClass * mc)3382 static void virt_machine_8_2_options(MachineClass *mc)
3383 {
3384 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3385
3386 virt_machine_9_0_options(mc);
3387 compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
3388 /*
3389 * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and
3390 * earlier machines. (Exposing it tickles a bug in older EDK2
3391 * guest BIOS binaries.)
3392 */
3393 vmc->no_ns_el2_virt_timer_irq = true;
3394 }
3395 DEFINE_VIRT_MACHINE(8, 2)
3396
virt_machine_8_1_options(MachineClass * mc)3397 static void virt_machine_8_1_options(MachineClass *mc)
3398 {
3399 virt_machine_8_2_options(mc);
3400 compat_props_add(mc->compat_props, hw_compat_8_1, hw_compat_8_1_len);
3401 }
3402 DEFINE_VIRT_MACHINE(8, 1)
3403
virt_machine_8_0_options(MachineClass * mc)3404 static void virt_machine_8_0_options(MachineClass *mc)
3405 {
3406 virt_machine_8_1_options(mc);
3407 compat_props_add(mc->compat_props, hw_compat_8_0, hw_compat_8_0_len);
3408 }
3409 DEFINE_VIRT_MACHINE(8, 0)
3410
virt_machine_7_2_options(MachineClass * mc)3411 static void virt_machine_7_2_options(MachineClass *mc)
3412 {
3413 virt_machine_8_0_options(mc);
3414 compat_props_add(mc->compat_props, hw_compat_7_2, hw_compat_7_2_len);
3415 }
3416 DEFINE_VIRT_MACHINE(7, 2)
3417
virt_machine_7_1_options(MachineClass * mc)3418 static void virt_machine_7_1_options(MachineClass *mc)
3419 {
3420 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3421
3422 virt_machine_7_2_options(mc);
3423 compat_props_add(mc->compat_props, hw_compat_7_1, hw_compat_7_1_len);
3424 /* Compact layout for high memory regions was introduced with 7.2 */
3425 vmc->no_highmem_compact = true;
3426 }
3427 DEFINE_VIRT_MACHINE(7, 1)
3428
virt_machine_7_0_options(MachineClass * mc)3429 static void virt_machine_7_0_options(MachineClass *mc)
3430 {
3431 virt_machine_7_1_options(mc);
3432 compat_props_add(mc->compat_props, hw_compat_7_0, hw_compat_7_0_len);
3433 }
3434 DEFINE_VIRT_MACHINE(7, 0)
3435
virt_machine_6_2_options(MachineClass * mc)3436 static void virt_machine_6_2_options(MachineClass *mc)
3437 {
3438 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3439
3440 virt_machine_7_0_options(mc);
3441 compat_props_add(mc->compat_props, hw_compat_6_2, hw_compat_6_2_len);
3442 vmc->no_tcg_lpa2 = true;
3443 }
3444 DEFINE_VIRT_MACHINE(6, 2)
3445
virt_machine_6_1_options(MachineClass * mc)3446 static void virt_machine_6_1_options(MachineClass *mc)
3447 {
3448 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3449
3450 virt_machine_6_2_options(mc);
3451 compat_props_add(mc->compat_props, hw_compat_6_1, hw_compat_6_1_len);
3452 mc->smp_props.prefer_sockets = true;
3453 vmc->no_cpu_topology = true;
3454
3455 /* qemu ITS was introduced with 6.2 */
3456 vmc->no_tcg_its = true;
3457 }
3458 DEFINE_VIRT_MACHINE(6, 1)
3459
virt_machine_6_0_options(MachineClass * mc)3460 static void virt_machine_6_0_options(MachineClass *mc)
3461 {
3462 virt_machine_6_1_options(mc);
3463 compat_props_add(mc->compat_props, hw_compat_6_0, hw_compat_6_0_len);
3464 }
3465 DEFINE_VIRT_MACHINE(6, 0)
3466
virt_machine_5_2_options(MachineClass * mc)3467 static void virt_machine_5_2_options(MachineClass *mc)
3468 {
3469 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3470
3471 virt_machine_6_0_options(mc);
3472 compat_props_add(mc->compat_props, hw_compat_5_2, hw_compat_5_2_len);
3473 vmc->no_secure_gpio = true;
3474 }
3475 DEFINE_VIRT_MACHINE(5, 2)
3476
virt_machine_5_1_options(MachineClass * mc)3477 static void virt_machine_5_1_options(MachineClass *mc)
3478 {
3479 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3480
3481 virt_machine_5_2_options(mc);
3482 compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len);
3483 vmc->no_kvm_steal_time = true;
3484 }
3485 DEFINE_VIRT_MACHINE(5, 1)
3486
virt_machine_5_0_options(MachineClass * mc)3487 static void virt_machine_5_0_options(MachineClass *mc)
3488 {
3489 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3490
3491 virt_machine_5_1_options(mc);
3492 compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
3493 mc->numa_mem_supported = true;
3494 vmc->acpi_expose_flash = true;
3495 mc->auto_enable_numa_with_memdev = false;
3496 }
3497 DEFINE_VIRT_MACHINE(5, 0)
3498
virt_machine_4_2_options(MachineClass * mc)3499 static void virt_machine_4_2_options(MachineClass *mc)
3500 {
3501 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3502
3503 virt_machine_5_0_options(mc);
3504 compat_props_add(mc->compat_props, hw_compat_4_2, hw_compat_4_2_len);
3505 vmc->kvm_no_adjvtime = true;
3506 }
3507 DEFINE_VIRT_MACHINE(4, 2)
3508
virt_machine_4_1_options(MachineClass * mc)3509 static void virt_machine_4_1_options(MachineClass *mc)
3510 {
3511 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3512
3513 virt_machine_4_2_options(mc);
3514 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
3515 vmc->no_ged = true;
3516 mc->auto_enable_numa_with_memhp = false;
3517 }
3518 DEFINE_VIRT_MACHINE(4, 1)
3519
virt_machine_4_0_options(MachineClass * mc)3520 static void virt_machine_4_0_options(MachineClass *mc)
3521 {
3522 virt_machine_4_1_options(mc);
3523 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
3524 }
3525 DEFINE_VIRT_MACHINE(4, 0)
3526
virt_machine_3_1_options(MachineClass * mc)3527 static void virt_machine_3_1_options(MachineClass *mc)
3528 {
3529 virt_machine_4_0_options(mc);
3530 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
3531 }
3532 DEFINE_VIRT_MACHINE(3, 1)
3533
virt_machine_3_0_options(MachineClass * mc)3534 static void virt_machine_3_0_options(MachineClass *mc)
3535 {
3536 virt_machine_3_1_options(mc);
3537 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
3538 }
3539 DEFINE_VIRT_MACHINE(3, 0)
3540
virt_machine_2_12_options(MachineClass * mc)3541 static void virt_machine_2_12_options(MachineClass *mc)
3542 {
3543 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3544
3545 virt_machine_3_0_options(mc);
3546 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
3547 vmc->no_highmem_ecam = true;
3548 mc->max_cpus = 255;
3549 }
3550 DEFINE_VIRT_MACHINE(2, 12)
3551
virt_machine_2_11_options(MachineClass * mc)3552 static void virt_machine_2_11_options(MachineClass *mc)
3553 {
3554 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3555
3556 virt_machine_2_12_options(mc);
3557 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
3558 vmc->smbios_old_sys_ver = true;
3559 }
3560 DEFINE_VIRT_MACHINE(2, 11)
3561
virt_machine_2_10_options(MachineClass * mc)3562 static void virt_machine_2_10_options(MachineClass *mc)
3563 {
3564 virt_machine_2_11_options(mc);
3565 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
3566 /* before 2.11 we never faulted accesses to bad addresses */
3567 mc->ignore_memory_transaction_failures = true;
3568 }
3569 DEFINE_VIRT_MACHINE(2, 10)
3570
virt_machine_2_9_options(MachineClass * mc)3571 static void virt_machine_2_9_options(MachineClass *mc)
3572 {
3573 virt_machine_2_10_options(mc);
3574 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
3575 }
3576 DEFINE_VIRT_MACHINE(2, 9)
3577
virt_machine_2_8_options(MachineClass * mc)3578 static void virt_machine_2_8_options(MachineClass *mc)
3579 {
3580 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3581
3582 virt_machine_2_9_options(mc);
3583 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
3584 /* For 2.8 and earlier we falsely claimed in the DT that
3585 * our timers were edge-triggered, not level-triggered.
3586 */
3587 vmc->claim_edge_triggered_timers = true;
3588 }
3589 DEFINE_VIRT_MACHINE(2, 8)
3590
virt_machine_2_7_options(MachineClass * mc)3591 static void virt_machine_2_7_options(MachineClass *mc)
3592 {
3593 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3594
3595 virt_machine_2_8_options(mc);
3596 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
3597 /* ITS was introduced with 2.8 */
3598 vmc->no_its = true;
3599 /* Stick with 1K pages for migration compatibility */
3600 mc->minimum_page_bits = 0;
3601 }
3602 DEFINE_VIRT_MACHINE(2, 7)
3603
virt_machine_2_6_options(MachineClass * mc)3604 static void virt_machine_2_6_options(MachineClass *mc)
3605 {
3606 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
3607
3608 virt_machine_2_7_options(mc);
3609 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
3610 vmc->disallow_affinity_adjustment = true;
3611 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
3612 vmc->no_pmu = true;
3613 }
3614 DEFINE_VIRT_MACHINE(2, 6)
3615