1 /*
2 * vfio based device assignment support
3 *
4 * Copyright Red Hat, Inc. 2012
5 *
6 * Authors:
7 * Alex Williamson <alex.williamson@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
19 */
20
21 #include "qemu/osdep.h"
22 #include CONFIG_DEVICES /* CONFIG_IOMMUFD */
23 #include <linux/vfio.h>
24 #include <sys/ioctl.h>
25
26 #include "hw/hw.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "hw/pci/pci_bridge.h"
30 #include "hw/qdev-properties.h"
31 #include "hw/qdev-properties-system.h"
32 #include "migration/vmstate.h"
33 #include "qobject/qdict.h"
34 #include "qemu/error-report.h"
35 #include "qemu/main-loop.h"
36 #include "qemu/module.h"
37 #include "qemu/range.h"
38 #include "qemu/units.h"
39 #include "system/kvm.h"
40 #include "system/runstate.h"
41 #include "pci.h"
42 #include "trace.h"
43 #include "qapi/error.h"
44 #include "migration/blocker.h"
45 #include "migration/qemu-file.h"
46 #include "system/iommufd.h"
47
48 #define TYPE_VFIO_PCI_NOHOTPLUG "vfio-pci-nohotplug"
49
50 /* Protected by BQL */
51 static KVMRouteChange vfio_route_change;
52
53 static void vfio_disable_interrupts(VFIOPCIDevice *vdev);
54 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled);
55 static void vfio_msi_disable_common(VFIOPCIDevice *vdev);
56
57 /*
58 * Disabling BAR mmaping can be slow, but toggling it around INTx can
59 * also be a huge overhead. We try to get the best of both worlds by
60 * waiting until an interrupt to disable mmaps (subsequent transitions
61 * to the same state are effectively no overhead). If the interrupt has
62 * been serviced and the time gap is long enough, we re-enable mmaps for
63 * performance. This works well for things like graphics cards, which
64 * may not use their interrupt at all and are penalized to an unusable
65 * level by read/write BAR traps. Other devices, like NICs, have more
66 * regular interrupts and see much better latency by staying in non-mmap
67 * mode. We therefore set the default mmap_timeout such that a ping
68 * is just enough to keep the mmap disabled. Users can experiment with
69 * other options with the x-intx-mmap-timeout-ms parameter (a value of
70 * zero disables the timer).
71 */
vfio_intx_mmap_enable(void * opaque)72 static void vfio_intx_mmap_enable(void *opaque)
73 {
74 VFIOPCIDevice *vdev = opaque;
75
76 if (vdev->intx.pending) {
77 timer_mod(vdev->intx.mmap_timer,
78 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
79 return;
80 }
81
82 vfio_mmap_set_enabled(vdev, true);
83 }
84
vfio_intx_interrupt(void * opaque)85 static void vfio_intx_interrupt(void *opaque)
86 {
87 VFIOPCIDevice *vdev = opaque;
88
89 if (!event_notifier_test_and_clear(&vdev->intx.interrupt)) {
90 return;
91 }
92
93 trace_vfio_intx_interrupt(vdev->vbasedev.name, 'A' + vdev->intx.pin);
94
95 vdev->intx.pending = true;
96 pci_irq_assert(&vdev->pdev);
97 vfio_mmap_set_enabled(vdev, false);
98 if (vdev->intx.mmap_timeout) {
99 timer_mod(vdev->intx.mmap_timer,
100 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + vdev->intx.mmap_timeout);
101 }
102 }
103
vfio_intx_eoi(VFIODevice * vbasedev)104 static void vfio_intx_eoi(VFIODevice *vbasedev)
105 {
106 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
107
108 if (!vdev->intx.pending) {
109 return;
110 }
111
112 trace_vfio_intx_eoi(vbasedev->name);
113
114 vdev->intx.pending = false;
115 pci_irq_deassert(&vdev->pdev);
116 vfio_unmask_single_irqindex(vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
117 }
118
vfio_intx_enable_kvm(VFIOPCIDevice * vdev,Error ** errp)119 static bool vfio_intx_enable_kvm(VFIOPCIDevice *vdev, Error **errp)
120 {
121 #ifdef CONFIG_KVM
122 int irq_fd = event_notifier_get_fd(&vdev->intx.interrupt);
123
124 if (vdev->no_kvm_intx || !kvm_irqfds_enabled() ||
125 vdev->intx.route.mode != PCI_INTX_ENABLED ||
126 !kvm_resamplefds_enabled()) {
127 return true;
128 }
129
130 /* Get to a known interrupt state */
131 qemu_set_fd_handler(irq_fd, NULL, NULL, vdev);
132 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
133 vdev->intx.pending = false;
134 pci_irq_deassert(&vdev->pdev);
135
136 /* Get an eventfd for resample/unmask */
137 if (event_notifier_init(&vdev->intx.unmask, 0)) {
138 error_setg(errp, "event_notifier_init failed eoi");
139 goto fail;
140 }
141
142 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state,
143 &vdev->intx.interrupt,
144 &vdev->intx.unmask,
145 vdev->intx.route.irq)) {
146 error_setg_errno(errp, errno, "failed to setup resample irqfd");
147 goto fail_irqfd;
148 }
149
150 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX, 0,
151 VFIO_IRQ_SET_ACTION_UNMASK,
152 event_notifier_get_fd(&vdev->intx.unmask),
153 errp)) {
154 goto fail_vfio;
155 }
156
157 /* Let'em rip */
158 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
159
160 vdev->intx.kvm_accel = true;
161
162 trace_vfio_intx_enable_kvm(vdev->vbasedev.name);
163
164 return true;
165
166 fail_vfio:
167 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vdev->intx.interrupt,
168 vdev->intx.route.irq);
169 fail_irqfd:
170 event_notifier_cleanup(&vdev->intx.unmask);
171 fail:
172 qemu_set_fd_handler(irq_fd, vfio_intx_interrupt, NULL, vdev);
173 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
174 return false;
175 #else
176 return true;
177 #endif
178 }
179
vfio_intx_disable_kvm(VFIOPCIDevice * vdev)180 static void vfio_intx_disable_kvm(VFIOPCIDevice *vdev)
181 {
182 #ifdef CONFIG_KVM
183 if (!vdev->intx.kvm_accel) {
184 return;
185 }
186
187 /*
188 * Get to a known state, hardware masked, QEMU ready to accept new
189 * interrupts, QEMU IRQ de-asserted.
190 */
191 vfio_mask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
192 vdev->intx.pending = false;
193 pci_irq_deassert(&vdev->pdev);
194
195 /* Tell KVM to stop listening for an INTx irqfd */
196 if (kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vdev->intx.interrupt,
197 vdev->intx.route.irq)) {
198 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
199 }
200
201 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
202 event_notifier_cleanup(&vdev->intx.unmask);
203
204 /* QEMU starts listening for interrupt events. */
205 qemu_set_fd_handler(event_notifier_get_fd(&vdev->intx.interrupt),
206 vfio_intx_interrupt, NULL, vdev);
207
208 vdev->intx.kvm_accel = false;
209
210 /* If we've missed an event, let it re-fire through QEMU */
211 vfio_unmask_single_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
212
213 trace_vfio_intx_disable_kvm(vdev->vbasedev.name);
214 #endif
215 }
216
vfio_intx_update(VFIOPCIDevice * vdev,PCIINTxRoute * route)217 static void vfio_intx_update(VFIOPCIDevice *vdev, PCIINTxRoute *route)
218 {
219 Error *err = NULL;
220
221 trace_vfio_intx_update(vdev->vbasedev.name,
222 vdev->intx.route.irq, route->irq);
223
224 vfio_intx_disable_kvm(vdev);
225
226 vdev->intx.route = *route;
227
228 if (route->mode != PCI_INTX_ENABLED) {
229 return;
230 }
231
232 if (!vfio_intx_enable_kvm(vdev, &err)) {
233 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
234 }
235
236 /* Re-enable the interrupt in cased we missed an EOI */
237 vfio_intx_eoi(&vdev->vbasedev);
238 }
239
vfio_intx_routing_notifier(PCIDevice * pdev)240 static void vfio_intx_routing_notifier(PCIDevice *pdev)
241 {
242 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
243 PCIINTxRoute route;
244
245 if (vdev->interrupt != VFIO_INT_INTx) {
246 return;
247 }
248
249 route = pci_device_route_intx_to_irq(&vdev->pdev, vdev->intx.pin);
250
251 if (pci_intx_route_changed(&vdev->intx.route, &route)) {
252 vfio_intx_update(vdev, &route);
253 }
254 }
255
vfio_irqchip_change(Notifier * notify,void * data)256 static void vfio_irqchip_change(Notifier *notify, void *data)
257 {
258 VFIOPCIDevice *vdev = container_of(notify, VFIOPCIDevice,
259 irqchip_change_notifier);
260
261 vfio_intx_update(vdev, &vdev->intx.route);
262 }
263
vfio_intx_enable(VFIOPCIDevice * vdev,Error ** errp)264 static bool vfio_intx_enable(VFIOPCIDevice *vdev, Error **errp)
265 {
266 uint8_t pin = vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1);
267 Error *err = NULL;
268 int32_t fd;
269 int ret;
270
271
272 if (!pin) {
273 return true;
274 }
275
276 vfio_disable_interrupts(vdev);
277
278 vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */
279 pci_config_set_interrupt_pin(vdev->pdev.config, pin);
280
281 #ifdef CONFIG_KVM
282 /*
283 * Only conditional to avoid generating error messages on platforms
284 * where we won't actually use the result anyway.
285 */
286 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) {
287 vdev->intx.route = pci_device_route_intx_to_irq(&vdev->pdev,
288 vdev->intx.pin);
289 }
290 #endif
291
292 ret = event_notifier_init(&vdev->intx.interrupt, 0);
293 if (ret) {
294 error_setg_errno(errp, -ret, "event_notifier_init failed");
295 return false;
296 }
297 fd = event_notifier_get_fd(&vdev->intx.interrupt);
298 qemu_set_fd_handler(fd, vfio_intx_interrupt, NULL, vdev);
299
300 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX, 0,
301 VFIO_IRQ_SET_ACTION_TRIGGER, fd, errp)) {
302 qemu_set_fd_handler(fd, NULL, NULL, vdev);
303 event_notifier_cleanup(&vdev->intx.interrupt);
304 return false;
305 }
306
307 if (!vfio_intx_enable_kvm(vdev, &err)) {
308 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
309 }
310
311 vdev->interrupt = VFIO_INT_INTx;
312
313 trace_vfio_intx_enable(vdev->vbasedev.name);
314 return true;
315 }
316
vfio_intx_disable(VFIOPCIDevice * vdev)317 static void vfio_intx_disable(VFIOPCIDevice *vdev)
318 {
319 int fd;
320
321 timer_del(vdev->intx.mmap_timer);
322 vfio_intx_disable_kvm(vdev);
323 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_INTX_IRQ_INDEX);
324 vdev->intx.pending = false;
325 pci_irq_deassert(&vdev->pdev);
326 vfio_mmap_set_enabled(vdev, true);
327
328 fd = event_notifier_get_fd(&vdev->intx.interrupt);
329 qemu_set_fd_handler(fd, NULL, NULL, vdev);
330 event_notifier_cleanup(&vdev->intx.interrupt);
331
332 vdev->interrupt = VFIO_INT_NONE;
333
334 trace_vfio_intx_disable(vdev->vbasedev.name);
335 }
336
337 /*
338 * MSI/X
339 */
vfio_msi_interrupt(void * opaque)340 static void vfio_msi_interrupt(void *opaque)
341 {
342 VFIOMSIVector *vector = opaque;
343 VFIOPCIDevice *vdev = vector->vdev;
344 MSIMessage (*get_msg)(PCIDevice *dev, unsigned vector);
345 void (*notify)(PCIDevice *dev, unsigned vector);
346 MSIMessage msg;
347 int nr = vector - vdev->msi_vectors;
348
349 if (!event_notifier_test_and_clear(&vector->interrupt)) {
350 return;
351 }
352
353 if (vdev->interrupt == VFIO_INT_MSIX) {
354 get_msg = msix_get_message;
355 notify = msix_notify;
356
357 /* A masked vector firing needs to use the PBA, enable it */
358 if (msix_is_masked(&vdev->pdev, nr)) {
359 set_bit(nr, vdev->msix->pending);
360 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, true);
361 trace_vfio_msix_pba_enable(vdev->vbasedev.name);
362 }
363 } else if (vdev->interrupt == VFIO_INT_MSI) {
364 get_msg = msi_get_message;
365 notify = msi_notify;
366 } else {
367 abort();
368 }
369
370 msg = get_msg(&vdev->pdev, nr);
371 trace_vfio_msi_interrupt(vdev->vbasedev.name, nr, msg.address, msg.data);
372 notify(&vdev->pdev, nr);
373 }
374
375 /*
376 * Get MSI-X enabled, but no vector enabled, by setting vector 0 with an invalid
377 * fd to kernel.
378 */
vfio_enable_msix_no_vec(VFIOPCIDevice * vdev)379 static int vfio_enable_msix_no_vec(VFIOPCIDevice *vdev)
380 {
381 g_autofree struct vfio_irq_set *irq_set = NULL;
382 int ret = 0, argsz;
383 int32_t *fd;
384
385 argsz = sizeof(*irq_set) + sizeof(*fd);
386
387 irq_set = g_malloc0(argsz);
388 irq_set->argsz = argsz;
389 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD |
390 VFIO_IRQ_SET_ACTION_TRIGGER;
391 irq_set->index = VFIO_PCI_MSIX_IRQ_INDEX;
392 irq_set->start = 0;
393 irq_set->count = 1;
394 fd = (int32_t *)&irq_set->data;
395 *fd = -1;
396
397 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
398
399 return ret;
400 }
401
vfio_enable_vectors(VFIOPCIDevice * vdev,bool msix)402 static int vfio_enable_vectors(VFIOPCIDevice *vdev, bool msix)
403 {
404 struct vfio_irq_set *irq_set;
405 int ret = 0, i, argsz;
406 int32_t *fds;
407
408 /*
409 * If dynamic MSI-X allocation is supported, the vectors to be allocated
410 * and enabled can be scattered. Before kernel enabling MSI-X, setting
411 * nr_vectors causes all these vectors to be allocated on host.
412 *
413 * To keep allocation as needed, use vector 0 with an invalid fd to get
414 * MSI-X enabled first, then set vectors with a potentially sparse set of
415 * eventfds to enable interrupts only when enabled in guest.
416 */
417 if (msix && !vdev->msix->noresize) {
418 ret = vfio_enable_msix_no_vec(vdev);
419
420 if (ret) {
421 return ret;
422 }
423 }
424
425 argsz = sizeof(*irq_set) + (vdev->nr_vectors * sizeof(*fds));
426
427 irq_set = g_malloc0(argsz);
428 irq_set->argsz = argsz;
429 irq_set->flags = VFIO_IRQ_SET_DATA_EVENTFD | VFIO_IRQ_SET_ACTION_TRIGGER;
430 irq_set->index = msix ? VFIO_PCI_MSIX_IRQ_INDEX : VFIO_PCI_MSI_IRQ_INDEX;
431 irq_set->start = 0;
432 irq_set->count = vdev->nr_vectors;
433 fds = (int32_t *)&irq_set->data;
434
435 for (i = 0; i < vdev->nr_vectors; i++) {
436 int fd = -1;
437
438 /*
439 * MSI vs MSI-X - The guest has direct access to MSI mask and pending
440 * bits, therefore we always use the KVM signaling path when setup.
441 * MSI-X mask and pending bits are emulated, so we want to use the
442 * KVM signaling path only when configured and unmasked.
443 */
444 if (vdev->msi_vectors[i].use) {
445 if (vdev->msi_vectors[i].virq < 0 ||
446 (msix && msix_is_masked(&vdev->pdev, i))) {
447 fd = event_notifier_get_fd(&vdev->msi_vectors[i].interrupt);
448 } else {
449 fd = event_notifier_get_fd(&vdev->msi_vectors[i].kvm_interrupt);
450 }
451 }
452
453 fds[i] = fd;
454 }
455
456 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_SET_IRQS, irq_set);
457
458 g_free(irq_set);
459
460 return ret;
461 }
462
vfio_add_kvm_msi_virq(VFIOPCIDevice * vdev,VFIOMSIVector * vector,int vector_n,bool msix)463 static void vfio_add_kvm_msi_virq(VFIOPCIDevice *vdev, VFIOMSIVector *vector,
464 int vector_n, bool msix)
465 {
466 if ((msix && vdev->no_kvm_msix) || (!msix && vdev->no_kvm_msi)) {
467 return;
468 }
469
470 vector->virq = kvm_irqchip_add_msi_route(&vfio_route_change,
471 vector_n, &vdev->pdev);
472 }
473
vfio_connect_kvm_msi_virq(VFIOMSIVector * vector)474 static void vfio_connect_kvm_msi_virq(VFIOMSIVector *vector)
475 {
476 if (vector->virq < 0) {
477 return;
478 }
479
480 if (event_notifier_init(&vector->kvm_interrupt, 0)) {
481 goto fail_notifier;
482 }
483
484 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
485 NULL, vector->virq) < 0) {
486 goto fail_kvm;
487 }
488
489 return;
490
491 fail_kvm:
492 event_notifier_cleanup(&vector->kvm_interrupt);
493 fail_notifier:
494 kvm_irqchip_release_virq(kvm_state, vector->virq);
495 vector->virq = -1;
496 }
497
vfio_remove_kvm_msi_virq(VFIOMSIVector * vector)498 static void vfio_remove_kvm_msi_virq(VFIOMSIVector *vector)
499 {
500 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state, &vector->kvm_interrupt,
501 vector->virq);
502 kvm_irqchip_release_virq(kvm_state, vector->virq);
503 vector->virq = -1;
504 event_notifier_cleanup(&vector->kvm_interrupt);
505 }
506
vfio_update_kvm_msi_virq(VFIOMSIVector * vector,MSIMessage msg,PCIDevice * pdev)507 static void vfio_update_kvm_msi_virq(VFIOMSIVector *vector, MSIMessage msg,
508 PCIDevice *pdev)
509 {
510 kvm_irqchip_update_msi_route(kvm_state, vector->virq, msg, pdev);
511 kvm_irqchip_commit_routes(kvm_state);
512 }
513
vfio_msix_vector_do_use(PCIDevice * pdev,unsigned int nr,MSIMessage * msg,IOHandler * handler)514 static int vfio_msix_vector_do_use(PCIDevice *pdev, unsigned int nr,
515 MSIMessage *msg, IOHandler *handler)
516 {
517 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
518 VFIOMSIVector *vector;
519 int ret;
520 bool resizing = !!(vdev->nr_vectors < nr + 1);
521
522 trace_vfio_msix_vector_do_use(vdev->vbasedev.name, nr);
523
524 vector = &vdev->msi_vectors[nr];
525
526 if (!vector->use) {
527 vector->vdev = vdev;
528 vector->virq = -1;
529 if (event_notifier_init(&vector->interrupt, 0)) {
530 error_report("vfio: Error: event_notifier_init failed");
531 }
532 vector->use = true;
533 msix_vector_use(pdev, nr);
534 }
535
536 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
537 handler, NULL, vector);
538
539 /*
540 * Attempt to enable route through KVM irqchip,
541 * default to userspace handling if unavailable.
542 */
543 if (vector->virq >= 0) {
544 if (!msg) {
545 vfio_remove_kvm_msi_virq(vector);
546 } else {
547 vfio_update_kvm_msi_virq(vector, *msg, pdev);
548 }
549 } else {
550 if (msg) {
551 if (vdev->defer_kvm_irq_routing) {
552 vfio_add_kvm_msi_virq(vdev, vector, nr, true);
553 } else {
554 vfio_route_change = kvm_irqchip_begin_route_changes(kvm_state);
555 vfio_add_kvm_msi_virq(vdev, vector, nr, true);
556 kvm_irqchip_commit_route_changes(&vfio_route_change);
557 vfio_connect_kvm_msi_virq(vector);
558 }
559 }
560 }
561
562 /*
563 * When dynamic allocation is not supported, we don't want to have the
564 * host allocate all possible MSI vectors for a device if they're not
565 * in use, so we shutdown and incrementally increase them as needed.
566 * nr_vectors represents the total number of vectors allocated.
567 *
568 * When dynamic allocation is supported, let the host only allocate
569 * and enable a vector when it is in use in guest. nr_vectors represents
570 * the upper bound of vectors being enabled (but not all of the ranges
571 * is allocated or enabled).
572 */
573 if (resizing) {
574 vdev->nr_vectors = nr + 1;
575 }
576
577 if (!vdev->defer_kvm_irq_routing) {
578 if (vdev->msix->noresize && resizing) {
579 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
580 ret = vfio_enable_vectors(vdev, true);
581 if (ret) {
582 error_report("vfio: failed to enable vectors, %d", ret);
583 }
584 } else {
585 Error *err = NULL;
586 int32_t fd;
587
588 if (vector->virq >= 0) {
589 fd = event_notifier_get_fd(&vector->kvm_interrupt);
590 } else {
591 fd = event_notifier_get_fd(&vector->interrupt);
592 }
593
594 if (!vfio_set_irq_signaling(&vdev->vbasedev,
595 VFIO_PCI_MSIX_IRQ_INDEX, nr,
596 VFIO_IRQ_SET_ACTION_TRIGGER, fd,
597 &err)) {
598 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
599 }
600 }
601 }
602
603 /* Disable PBA emulation when nothing more is pending. */
604 clear_bit(nr, vdev->msix->pending);
605 if (find_first_bit(vdev->msix->pending,
606 vdev->nr_vectors) == vdev->nr_vectors) {
607 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
608 trace_vfio_msix_pba_disable(vdev->vbasedev.name);
609 }
610
611 return 0;
612 }
613
vfio_msix_vector_use(PCIDevice * pdev,unsigned int nr,MSIMessage msg)614 static int vfio_msix_vector_use(PCIDevice *pdev,
615 unsigned int nr, MSIMessage msg)
616 {
617 return vfio_msix_vector_do_use(pdev, nr, &msg, vfio_msi_interrupt);
618 }
619
vfio_msix_vector_release(PCIDevice * pdev,unsigned int nr)620 static void vfio_msix_vector_release(PCIDevice *pdev, unsigned int nr)
621 {
622 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
623 VFIOMSIVector *vector = &vdev->msi_vectors[nr];
624
625 trace_vfio_msix_vector_release(vdev->vbasedev.name, nr);
626
627 /*
628 * There are still old guests that mask and unmask vectors on every
629 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of
630 * the KVM setup in place, simply switch VFIO to use the non-bypass
631 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X
632 * core will mask the interrupt and set pending bits, allowing it to
633 * be re-asserted on unmask. Nothing to do if already using QEMU mode.
634 */
635 if (vector->virq >= 0) {
636 int32_t fd = event_notifier_get_fd(&vector->interrupt);
637 Error *err = NULL;
638
639 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX,
640 nr, VFIO_IRQ_SET_ACTION_TRIGGER, fd,
641 &err)) {
642 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
643 }
644 }
645 }
646
vfio_prepare_kvm_msi_virq_batch(VFIOPCIDevice * vdev)647 static void vfio_prepare_kvm_msi_virq_batch(VFIOPCIDevice *vdev)
648 {
649 assert(!vdev->defer_kvm_irq_routing);
650 vdev->defer_kvm_irq_routing = true;
651 vfio_route_change = kvm_irqchip_begin_route_changes(kvm_state);
652 }
653
vfio_commit_kvm_msi_virq_batch(VFIOPCIDevice * vdev)654 static void vfio_commit_kvm_msi_virq_batch(VFIOPCIDevice *vdev)
655 {
656 int i;
657
658 assert(vdev->defer_kvm_irq_routing);
659 vdev->defer_kvm_irq_routing = false;
660
661 kvm_irqchip_commit_route_changes(&vfio_route_change);
662
663 for (i = 0; i < vdev->nr_vectors; i++) {
664 vfio_connect_kvm_msi_virq(&vdev->msi_vectors[i]);
665 }
666 }
667
vfio_msix_enable(VFIOPCIDevice * vdev)668 static void vfio_msix_enable(VFIOPCIDevice *vdev)
669 {
670 int ret;
671
672 vfio_disable_interrupts(vdev);
673
674 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->msix->entries);
675
676 vdev->interrupt = VFIO_INT_MSIX;
677
678 /*
679 * Setting vector notifiers triggers synchronous vector-use
680 * callbacks for each active vector. Deferring to commit the KVM
681 * routes once rather than per vector provides a substantial
682 * performance improvement.
683 */
684 vfio_prepare_kvm_msi_virq_batch(vdev);
685
686 if (msix_set_vector_notifiers(&vdev->pdev, vfio_msix_vector_use,
687 vfio_msix_vector_release, NULL)) {
688 error_report("vfio: msix_set_vector_notifiers failed");
689 }
690
691 vfio_commit_kvm_msi_virq_batch(vdev);
692
693 if (vdev->nr_vectors) {
694 ret = vfio_enable_vectors(vdev, true);
695 if (ret) {
696 error_report("vfio: failed to enable vectors, %d", ret);
697 }
698 } else {
699 /*
700 * Some communication channels between VF & PF or PF & fw rely on the
701 * physical state of the device and expect that enabling MSI-X from the
702 * guest enables the same on the host. When our guest is Linux, the
703 * guest driver call to pci_enable_msix() sets the enabling bit in the
704 * MSI-X capability, but leaves the vector table masked. We therefore
705 * can't rely on a vector_use callback (from request_irq() in the guest)
706 * to switch the physical device into MSI-X mode because that may come a
707 * long time after pci_enable_msix(). This code sets vector 0 with an
708 * invalid fd to make the physical device MSI-X enabled, but with no
709 * vectors enabled, just like the guest view.
710 */
711 ret = vfio_enable_msix_no_vec(vdev);
712 if (ret) {
713 error_report("vfio: failed to enable MSI-X, %d", ret);
714 }
715 }
716
717 trace_vfio_msix_enable(vdev->vbasedev.name);
718 }
719
vfio_msi_enable(VFIOPCIDevice * vdev)720 static void vfio_msi_enable(VFIOPCIDevice *vdev)
721 {
722 int ret, i;
723
724 vfio_disable_interrupts(vdev);
725
726 vdev->nr_vectors = msi_nr_vectors_allocated(&vdev->pdev);
727 retry:
728 /*
729 * Setting vector notifiers needs to enable route for each vector.
730 * Deferring to commit the KVM routes once rather than per vector
731 * provides a substantial performance improvement.
732 */
733 vfio_prepare_kvm_msi_virq_batch(vdev);
734
735 vdev->msi_vectors = g_new0(VFIOMSIVector, vdev->nr_vectors);
736
737 for (i = 0; i < vdev->nr_vectors; i++) {
738 VFIOMSIVector *vector = &vdev->msi_vectors[i];
739
740 vector->vdev = vdev;
741 vector->virq = -1;
742 vector->use = true;
743
744 if (event_notifier_init(&vector->interrupt, 0)) {
745 error_report("vfio: Error: event_notifier_init failed");
746 }
747
748 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
749 vfio_msi_interrupt, NULL, vector);
750
751 /*
752 * Attempt to enable route through KVM irqchip,
753 * default to userspace handling if unavailable.
754 */
755 vfio_add_kvm_msi_virq(vdev, vector, i, false);
756 }
757
758 vfio_commit_kvm_msi_virq_batch(vdev);
759
760 /* Set interrupt type prior to possible interrupts */
761 vdev->interrupt = VFIO_INT_MSI;
762
763 ret = vfio_enable_vectors(vdev, false);
764 if (ret) {
765 if (ret < 0) {
766 error_report("vfio: Error: Failed to setup MSI fds: %m");
767 } else {
768 error_report("vfio: Error: Failed to enable %d "
769 "MSI vectors, retry with %d", vdev->nr_vectors, ret);
770 }
771
772 vfio_msi_disable_common(vdev);
773
774 if (ret > 0) {
775 vdev->nr_vectors = ret;
776 goto retry;
777 }
778
779 /*
780 * Failing to setup MSI doesn't really fall within any specification.
781 * Let's try leaving interrupts disabled and hope the guest figures
782 * out to fall back to INTx for this device.
783 */
784 error_report("vfio: Error: Failed to enable MSI");
785
786 return;
787 }
788
789 trace_vfio_msi_enable(vdev->vbasedev.name, vdev->nr_vectors);
790 }
791
vfio_msi_disable_common(VFIOPCIDevice * vdev)792 static void vfio_msi_disable_common(VFIOPCIDevice *vdev)
793 {
794 int i;
795
796 for (i = 0; i < vdev->nr_vectors; i++) {
797 VFIOMSIVector *vector = &vdev->msi_vectors[i];
798 if (vdev->msi_vectors[i].use) {
799 if (vector->virq >= 0) {
800 vfio_remove_kvm_msi_virq(vector);
801 }
802 qemu_set_fd_handler(event_notifier_get_fd(&vector->interrupt),
803 NULL, NULL, NULL);
804 event_notifier_cleanup(&vector->interrupt);
805 }
806 }
807
808 g_free(vdev->msi_vectors);
809 vdev->msi_vectors = NULL;
810 vdev->nr_vectors = 0;
811 vdev->interrupt = VFIO_INT_NONE;
812 }
813
vfio_msix_disable(VFIOPCIDevice * vdev)814 static void vfio_msix_disable(VFIOPCIDevice *vdev)
815 {
816 Error *err = NULL;
817 int i;
818
819 msix_unset_vector_notifiers(&vdev->pdev);
820
821 /*
822 * MSI-X will only release vectors if MSI-X is still enabled on the
823 * device, check through the rest and release it ourselves if necessary.
824 */
825 for (i = 0; i < vdev->nr_vectors; i++) {
826 if (vdev->msi_vectors[i].use) {
827 vfio_msix_vector_release(&vdev->pdev, i);
828 msix_vector_unuse(&vdev->pdev, i);
829 }
830 }
831
832 /*
833 * Always clear MSI-X IRQ index. A PF device could have enabled
834 * MSI-X with no vectors. See vfio_msix_enable().
835 */
836 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSIX_IRQ_INDEX);
837
838 vfio_msi_disable_common(vdev);
839 if (!vfio_intx_enable(vdev, &err)) {
840 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
841 }
842
843 memset(vdev->msix->pending, 0,
844 BITS_TO_LONGS(vdev->msix->entries) * sizeof(unsigned long));
845
846 trace_vfio_msix_disable(vdev->vbasedev.name);
847 }
848
vfio_msi_disable(VFIOPCIDevice * vdev)849 static void vfio_msi_disable(VFIOPCIDevice *vdev)
850 {
851 Error *err = NULL;
852
853 vfio_disable_irqindex(&vdev->vbasedev, VFIO_PCI_MSI_IRQ_INDEX);
854 vfio_msi_disable_common(vdev);
855 vfio_intx_enable(vdev, &err);
856 if (err) {
857 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
858 }
859
860 trace_vfio_msi_disable(vdev->vbasedev.name);
861 }
862
vfio_update_msi(VFIOPCIDevice * vdev)863 static void vfio_update_msi(VFIOPCIDevice *vdev)
864 {
865 int i;
866
867 for (i = 0; i < vdev->nr_vectors; i++) {
868 VFIOMSIVector *vector = &vdev->msi_vectors[i];
869 MSIMessage msg;
870
871 if (!vector->use || vector->virq < 0) {
872 continue;
873 }
874
875 msg = msi_get_message(&vdev->pdev, i);
876 vfio_update_kvm_msi_virq(vector, msg, &vdev->pdev);
877 }
878 }
879
vfio_pci_load_rom(VFIOPCIDevice * vdev)880 static void vfio_pci_load_rom(VFIOPCIDevice *vdev)
881 {
882 g_autofree struct vfio_region_info *reg_info = NULL;
883 uint64_t size;
884 off_t off = 0;
885 ssize_t bytes;
886
887 if (vfio_get_region_info(&vdev->vbasedev,
888 VFIO_PCI_ROM_REGION_INDEX, ®_info)) {
889 error_report("vfio: Error getting ROM info: %m");
890 return;
891 }
892
893 trace_vfio_pci_load_rom(vdev->vbasedev.name, (unsigned long)reg_info->size,
894 (unsigned long)reg_info->offset,
895 (unsigned long)reg_info->flags);
896
897 vdev->rom_size = size = reg_info->size;
898 vdev->rom_offset = reg_info->offset;
899
900 if (!vdev->rom_size) {
901 vdev->rom_read_failed = true;
902 error_report("vfio-pci: Cannot read device rom at "
903 "%s", vdev->vbasedev.name);
904 error_printf("Device option ROM contents are probably invalid "
905 "(check dmesg).\nSkip option ROM probe with rombar=0, "
906 "or load from file with romfile=\n");
907 return;
908 }
909
910 vdev->rom = g_malloc(size);
911 memset(vdev->rom, 0xff, size);
912
913 while (size) {
914 bytes = pread(vdev->vbasedev.fd, vdev->rom + off,
915 size, vdev->rom_offset + off);
916 if (bytes == 0) {
917 break;
918 } else if (bytes > 0) {
919 off += bytes;
920 size -= bytes;
921 } else {
922 if (errno == EINTR || errno == EAGAIN) {
923 continue;
924 }
925 error_report("vfio: Error reading device ROM: %m");
926 break;
927 }
928 }
929
930 /*
931 * Test the ROM signature against our device, if the vendor is correct
932 * but the device ID doesn't match, store the correct device ID and
933 * recompute the checksum. Intel IGD devices need this and are known
934 * to have bogus checksums so we can't simply adjust the checksum.
935 */
936 if (pci_get_word(vdev->rom) == 0xaa55 &&
937 pci_get_word(vdev->rom + 0x18) + 8 < vdev->rom_size &&
938 !memcmp(vdev->rom + pci_get_word(vdev->rom + 0x18), "PCIR", 4)) {
939 uint16_t vid, did;
940
941 vid = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 4);
942 did = pci_get_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6);
943
944 if (vid == vdev->vendor_id && did != vdev->device_id) {
945 int i;
946 uint8_t csum, *data = vdev->rom;
947
948 pci_set_word(vdev->rom + pci_get_word(vdev->rom + 0x18) + 6,
949 vdev->device_id);
950 data[6] = 0;
951
952 for (csum = 0, i = 0; i < vdev->rom_size; i++) {
953 csum += data[i];
954 }
955
956 data[6] = -csum;
957 }
958 }
959 }
960
vfio_rom_read(void * opaque,hwaddr addr,unsigned size)961 static uint64_t vfio_rom_read(void *opaque, hwaddr addr, unsigned size)
962 {
963 VFIOPCIDevice *vdev = opaque;
964 union {
965 uint8_t byte;
966 uint16_t word;
967 uint32_t dword;
968 uint64_t qword;
969 } val;
970 uint64_t data = 0;
971
972 /* Load the ROM lazily when the guest tries to read it */
973 if (unlikely(!vdev->rom && !vdev->rom_read_failed)) {
974 vfio_pci_load_rom(vdev);
975 }
976
977 memcpy(&val, vdev->rom + addr,
978 (addr < vdev->rom_size) ? MIN(size, vdev->rom_size - addr) : 0);
979
980 switch (size) {
981 case 1:
982 data = val.byte;
983 break;
984 case 2:
985 data = le16_to_cpu(val.word);
986 break;
987 case 4:
988 data = le32_to_cpu(val.dword);
989 break;
990 default:
991 hw_error("vfio: unsupported read size, %d bytes\n", size);
992 break;
993 }
994
995 trace_vfio_rom_read(vdev->vbasedev.name, addr, size, data);
996
997 return data;
998 }
999
vfio_rom_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)1000 static void vfio_rom_write(void *opaque, hwaddr addr,
1001 uint64_t data, unsigned size)
1002 {
1003 }
1004
1005 static const MemoryRegionOps vfio_rom_ops = {
1006 .read = vfio_rom_read,
1007 .write = vfio_rom_write,
1008 .endianness = DEVICE_LITTLE_ENDIAN,
1009 };
1010
vfio_pci_size_rom(VFIOPCIDevice * vdev)1011 static void vfio_pci_size_rom(VFIOPCIDevice *vdev)
1012 {
1013 uint32_t orig, size = cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK);
1014 off_t offset = vdev->config_offset + PCI_ROM_ADDRESS;
1015 char *name;
1016 int fd = vdev->vbasedev.fd;
1017
1018 if (vdev->pdev.romfile || !vdev->pdev.rom_bar) {
1019 /* Since pci handles romfile, just print a message and return */
1020 if (vfio_opt_rom_in_denylist(vdev) && vdev->pdev.romfile) {
1021 warn_report("Device at %s is known to cause system instability"
1022 " issues during option rom execution",
1023 vdev->vbasedev.name);
1024 error_printf("Proceeding anyway since user specified romfile\n");
1025 }
1026 return;
1027 }
1028
1029 /*
1030 * Use the same size ROM BAR as the physical device. The contents
1031 * will get filled in later when the guest tries to read it.
1032 */
1033 if (pread(fd, &orig, 4, offset) != 4 ||
1034 pwrite(fd, &size, 4, offset) != 4 ||
1035 pread(fd, &size, 4, offset) != 4 ||
1036 pwrite(fd, &orig, 4, offset) != 4) {
1037 error_report("%s(%s) failed: %m", __func__, vdev->vbasedev.name);
1038 return;
1039 }
1040
1041 size = ~(le32_to_cpu(size) & PCI_ROM_ADDRESS_MASK) + 1;
1042
1043 if (!size) {
1044 return;
1045 }
1046
1047 if (vfio_opt_rom_in_denylist(vdev)) {
1048 if (vdev->pdev.rom_bar > 0) {
1049 warn_report("Device at %s is known to cause system instability"
1050 " issues during option rom execution",
1051 vdev->vbasedev.name);
1052 error_printf("Proceeding anyway since user specified"
1053 " positive value for rombar\n");
1054 } else {
1055 warn_report("Rom loading for device at %s has been disabled"
1056 " due to system instability issues",
1057 vdev->vbasedev.name);
1058 error_printf("Specify rombar=1 or romfile to force\n");
1059 return;
1060 }
1061 }
1062
1063 trace_vfio_pci_size_rom(vdev->vbasedev.name, size);
1064
1065 name = g_strdup_printf("vfio[%s].rom", vdev->vbasedev.name);
1066
1067 memory_region_init_io(&vdev->pdev.rom, OBJECT(vdev),
1068 &vfio_rom_ops, vdev, name, size);
1069 g_free(name);
1070
1071 pci_register_bar(&vdev->pdev, PCI_ROM_SLOT,
1072 PCI_BASE_ADDRESS_SPACE_MEMORY, &vdev->pdev.rom);
1073
1074 vdev->rom_read_failed = false;
1075 }
1076
vfio_vga_write(void * opaque,hwaddr addr,uint64_t data,unsigned size)1077 void vfio_vga_write(void *opaque, hwaddr addr,
1078 uint64_t data, unsigned size)
1079 {
1080 VFIOVGARegion *region = opaque;
1081 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1082 union {
1083 uint8_t byte;
1084 uint16_t word;
1085 uint32_t dword;
1086 uint64_t qword;
1087 } buf;
1088 off_t offset = vga->fd_offset + region->offset + addr;
1089
1090 switch (size) {
1091 case 1:
1092 buf.byte = data;
1093 break;
1094 case 2:
1095 buf.word = cpu_to_le16(data);
1096 break;
1097 case 4:
1098 buf.dword = cpu_to_le32(data);
1099 break;
1100 default:
1101 hw_error("vfio: unsupported write size, %d bytes", size);
1102 break;
1103 }
1104
1105 if (pwrite(vga->fd, &buf, size, offset) != size) {
1106 error_report("%s(,0x%"HWADDR_PRIx", 0x%"PRIx64", %d) failed: %m",
1107 __func__, region->offset + addr, data, size);
1108 }
1109
1110 trace_vfio_vga_write(region->offset + addr, data, size);
1111 }
1112
vfio_vga_read(void * opaque,hwaddr addr,unsigned size)1113 uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size)
1114 {
1115 VFIOVGARegion *region = opaque;
1116 VFIOVGA *vga = container_of(region, VFIOVGA, region[region->nr]);
1117 union {
1118 uint8_t byte;
1119 uint16_t word;
1120 uint32_t dword;
1121 uint64_t qword;
1122 } buf;
1123 uint64_t data = 0;
1124 off_t offset = vga->fd_offset + region->offset + addr;
1125
1126 if (pread(vga->fd, &buf, size, offset) != size) {
1127 error_report("%s(,0x%"HWADDR_PRIx", %d) failed: %m",
1128 __func__, region->offset + addr, size);
1129 return (uint64_t)-1;
1130 }
1131
1132 switch (size) {
1133 case 1:
1134 data = buf.byte;
1135 break;
1136 case 2:
1137 data = le16_to_cpu(buf.word);
1138 break;
1139 case 4:
1140 data = le32_to_cpu(buf.dword);
1141 break;
1142 default:
1143 hw_error("vfio: unsupported read size, %d bytes", size);
1144 break;
1145 }
1146
1147 trace_vfio_vga_read(region->offset + addr, size, data);
1148
1149 return data;
1150 }
1151
1152 static const MemoryRegionOps vfio_vga_ops = {
1153 .read = vfio_vga_read,
1154 .write = vfio_vga_write,
1155 .endianness = DEVICE_LITTLE_ENDIAN,
1156 };
1157
1158 /*
1159 * Expand memory region of sub-page(size < PAGE_SIZE) MMIO BAR to page
1160 * size if the BAR is in an exclusive page in host so that we could map
1161 * this BAR to guest. But this sub-page BAR may not occupy an exclusive
1162 * page in guest. So we should set the priority of the expanded memory
1163 * region to zero in case of overlap with BARs which share the same page
1164 * with the sub-page BAR in guest. Besides, we should also recover the
1165 * size of this sub-page BAR when its base address is changed in guest
1166 * and not page aligned any more.
1167 */
vfio_sub_page_bar_update_mapping(PCIDevice * pdev,int bar)1168 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar)
1169 {
1170 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1171 VFIORegion *region = &vdev->bars[bar].region;
1172 MemoryRegion *mmap_mr, *region_mr, *base_mr;
1173 PCIIORegion *r;
1174 pcibus_t bar_addr;
1175 uint64_t size = region->size;
1176
1177 /* Make sure that the whole region is allowed to be mmapped */
1178 if (region->nr_mmaps != 1 || !region->mmaps[0].mmap ||
1179 region->mmaps[0].size != region->size) {
1180 return;
1181 }
1182
1183 r = &pdev->io_regions[bar];
1184 bar_addr = r->addr;
1185 base_mr = vdev->bars[bar].mr;
1186 region_mr = region->mem;
1187 mmap_mr = ®ion->mmaps[0].mem;
1188
1189 /* If BAR is mapped and page aligned, update to fill PAGE_SIZE */
1190 if (bar_addr != PCI_BAR_UNMAPPED &&
1191 !(bar_addr & ~qemu_real_host_page_mask())) {
1192 size = qemu_real_host_page_size();
1193 }
1194
1195 memory_region_transaction_begin();
1196
1197 if (vdev->bars[bar].size < size) {
1198 memory_region_set_size(base_mr, size);
1199 }
1200 memory_region_set_size(region_mr, size);
1201 memory_region_set_size(mmap_mr, size);
1202 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) {
1203 memory_region_del_subregion(r->address_space, base_mr);
1204 memory_region_add_subregion_overlap(r->address_space,
1205 bar_addr, base_mr, 0);
1206 }
1207
1208 memory_region_transaction_commit();
1209 }
1210
1211 /*
1212 * PCI config space
1213 */
vfio_pci_read_config(PCIDevice * pdev,uint32_t addr,int len)1214 uint32_t vfio_pci_read_config(PCIDevice *pdev, uint32_t addr, int len)
1215 {
1216 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1217 uint32_t emu_bits = 0, emu_val = 0, phys_val = 0, val;
1218
1219 memcpy(&emu_bits, vdev->emulated_config_bits + addr, len);
1220 emu_bits = le32_to_cpu(emu_bits);
1221
1222 if (emu_bits) {
1223 emu_val = pci_default_read_config(pdev, addr, len);
1224 }
1225
1226 if (~emu_bits & (0xffffffffU >> (32 - len * 8))) {
1227 ssize_t ret;
1228
1229 ret = pread(vdev->vbasedev.fd, &phys_val, len,
1230 vdev->config_offset + addr);
1231 if (ret != len) {
1232 error_report("%s(%s, 0x%x, 0x%x) failed: %m",
1233 __func__, vdev->vbasedev.name, addr, len);
1234 return -errno;
1235 }
1236 phys_val = le32_to_cpu(phys_val);
1237 }
1238
1239 val = (emu_val & emu_bits) | (phys_val & ~emu_bits);
1240
1241 trace_vfio_pci_read_config(vdev->vbasedev.name, addr, len, val);
1242
1243 return val;
1244 }
1245
vfio_pci_write_config(PCIDevice * pdev,uint32_t addr,uint32_t val,int len)1246 void vfio_pci_write_config(PCIDevice *pdev,
1247 uint32_t addr, uint32_t val, int len)
1248 {
1249 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
1250 uint32_t val_le = cpu_to_le32(val);
1251
1252 trace_vfio_pci_write_config(vdev->vbasedev.name, addr, val, len);
1253
1254 /* Write everything to VFIO, let it filter out what we can't write */
1255 if (pwrite(vdev->vbasedev.fd, &val_le, len, vdev->config_offset + addr)
1256 != len) {
1257 error_report("%s(%s, 0x%x, 0x%x, 0x%x) failed: %m",
1258 __func__, vdev->vbasedev.name, addr, val, len);
1259 }
1260
1261 /* MSI/MSI-X Enabling/Disabling */
1262 if (pdev->cap_present & QEMU_PCI_CAP_MSI &&
1263 ranges_overlap(addr, len, pdev->msi_cap, vdev->msi_cap_size)) {
1264 int is_enabled, was_enabled = msi_enabled(pdev);
1265
1266 pci_default_write_config(pdev, addr, val, len);
1267
1268 is_enabled = msi_enabled(pdev);
1269
1270 if (!was_enabled) {
1271 if (is_enabled) {
1272 vfio_msi_enable(vdev);
1273 }
1274 } else {
1275 if (!is_enabled) {
1276 vfio_msi_disable(vdev);
1277 } else {
1278 vfio_update_msi(vdev);
1279 }
1280 }
1281 } else if (pdev->cap_present & QEMU_PCI_CAP_MSIX &&
1282 ranges_overlap(addr, len, pdev->msix_cap, MSIX_CAP_LENGTH)) {
1283 int is_enabled, was_enabled = msix_enabled(pdev);
1284
1285 pci_default_write_config(pdev, addr, val, len);
1286
1287 is_enabled = msix_enabled(pdev);
1288
1289 if (!was_enabled && is_enabled) {
1290 vfio_msix_enable(vdev);
1291 } else if (was_enabled && !is_enabled) {
1292 vfio_msix_disable(vdev);
1293 }
1294 } else if (ranges_overlap(addr, len, PCI_BASE_ADDRESS_0, 24) ||
1295 range_covers_byte(addr, len, PCI_COMMAND)) {
1296 pcibus_t old_addr[PCI_NUM_REGIONS - 1];
1297 int bar;
1298
1299 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1300 old_addr[bar] = pdev->io_regions[bar].addr;
1301 }
1302
1303 pci_default_write_config(pdev, addr, val, len);
1304
1305 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
1306 if (old_addr[bar] != pdev->io_regions[bar].addr &&
1307 vdev->bars[bar].region.size > 0 &&
1308 vdev->bars[bar].region.size < qemu_real_host_page_size()) {
1309 vfio_sub_page_bar_update_mapping(pdev, bar);
1310 }
1311 }
1312 } else {
1313 /* Write everything to QEMU to keep emulated bits correct */
1314 pci_default_write_config(pdev, addr, val, len);
1315 }
1316 }
1317
1318 /*
1319 * Interrupt setup
1320 */
vfio_disable_interrupts(VFIOPCIDevice * vdev)1321 static void vfio_disable_interrupts(VFIOPCIDevice *vdev)
1322 {
1323 /*
1324 * More complicated than it looks. Disabling MSI/X transitions the
1325 * device to INTx mode (if supported). Therefore we need to first
1326 * disable MSI/X and then cleanup by disabling INTx.
1327 */
1328 if (vdev->interrupt == VFIO_INT_MSIX) {
1329 vfio_msix_disable(vdev);
1330 } else if (vdev->interrupt == VFIO_INT_MSI) {
1331 vfio_msi_disable(vdev);
1332 }
1333
1334 if (vdev->interrupt == VFIO_INT_INTx) {
1335 vfio_intx_disable(vdev);
1336 }
1337 }
1338
vfio_msi_setup(VFIOPCIDevice * vdev,int pos,Error ** errp)1339 static bool vfio_msi_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1340 {
1341 uint16_t ctrl;
1342 bool msi_64bit, msi_maskbit;
1343 int ret, entries;
1344 Error *err = NULL;
1345
1346 if (pread(vdev->vbasedev.fd, &ctrl, sizeof(ctrl),
1347 vdev->config_offset + pos + PCI_CAP_FLAGS) != sizeof(ctrl)) {
1348 error_setg_errno(errp, errno, "failed reading MSI PCI_CAP_FLAGS");
1349 return false;
1350 }
1351 ctrl = le16_to_cpu(ctrl);
1352
1353 msi_64bit = !!(ctrl & PCI_MSI_FLAGS_64BIT);
1354 msi_maskbit = !!(ctrl & PCI_MSI_FLAGS_MASKBIT);
1355 entries = 1 << ((ctrl & PCI_MSI_FLAGS_QMASK) >> 1);
1356
1357 trace_vfio_msi_setup(vdev->vbasedev.name, pos);
1358
1359 ret = msi_init(&vdev->pdev, pos, entries, msi_64bit, msi_maskbit, &err);
1360 if (ret < 0) {
1361 if (ret == -ENOTSUP) {
1362 return true;
1363 }
1364 error_propagate_prepend(errp, err, "msi_init failed: ");
1365 return false;
1366 }
1367 vdev->msi_cap_size = 0xa + (msi_maskbit ? 0xa : 0) + (msi_64bit ? 0x4 : 0);
1368
1369 return true;
1370 }
1371
vfio_pci_fixup_msix_region(VFIOPCIDevice * vdev)1372 static void vfio_pci_fixup_msix_region(VFIOPCIDevice *vdev)
1373 {
1374 off_t start, end;
1375 VFIORegion *region = &vdev->bars[vdev->msix->table_bar].region;
1376
1377 /*
1378 * If the host driver allows mapping of a MSIX data, we are going to
1379 * do map the entire BAR and emulate MSIX table on top of that.
1380 */
1381 if (vfio_has_region_cap(&vdev->vbasedev, region->nr,
1382 VFIO_REGION_INFO_CAP_MSIX_MAPPABLE)) {
1383 return;
1384 }
1385
1386 /*
1387 * We expect to find a single mmap covering the whole BAR, anything else
1388 * means it's either unsupported or already setup.
1389 */
1390 if (region->nr_mmaps != 1 || region->mmaps[0].offset ||
1391 region->size != region->mmaps[0].size) {
1392 return;
1393 }
1394
1395 /* MSI-X table start and end aligned to host page size */
1396 start = vdev->msix->table_offset & qemu_real_host_page_mask();
1397 end = REAL_HOST_PAGE_ALIGN((uint64_t)vdev->msix->table_offset +
1398 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE));
1399
1400 /*
1401 * Does the MSI-X table cover the beginning of the BAR? The whole BAR?
1402 * NB - Host page size is necessarily a power of two and so is the PCI
1403 * BAR (not counting EA yet), therefore if we have host page aligned
1404 * @start and @end, then any remainder of the BAR before or after those
1405 * must be at least host page sized and therefore mmap'able.
1406 */
1407 if (!start) {
1408 if (end >= region->size) {
1409 region->nr_mmaps = 0;
1410 g_free(region->mmaps);
1411 region->mmaps = NULL;
1412 trace_vfio_msix_fixup(vdev->vbasedev.name,
1413 vdev->msix->table_bar, 0, 0);
1414 } else {
1415 region->mmaps[0].offset = end;
1416 region->mmaps[0].size = region->size - end;
1417 trace_vfio_msix_fixup(vdev->vbasedev.name,
1418 vdev->msix->table_bar, region->mmaps[0].offset,
1419 region->mmaps[0].offset + region->mmaps[0].size);
1420 }
1421
1422 /* Maybe it's aligned at the end of the BAR */
1423 } else if (end >= region->size) {
1424 region->mmaps[0].size = start;
1425 trace_vfio_msix_fixup(vdev->vbasedev.name,
1426 vdev->msix->table_bar, region->mmaps[0].offset,
1427 region->mmaps[0].offset + region->mmaps[0].size);
1428
1429 /* Otherwise it must split the BAR */
1430 } else {
1431 region->nr_mmaps = 2;
1432 region->mmaps = g_renew(VFIOMmap, region->mmaps, 2);
1433
1434 memcpy(®ion->mmaps[1], ®ion->mmaps[0], sizeof(VFIOMmap));
1435
1436 region->mmaps[0].size = start;
1437 trace_vfio_msix_fixup(vdev->vbasedev.name,
1438 vdev->msix->table_bar, region->mmaps[0].offset,
1439 region->mmaps[0].offset + region->mmaps[0].size);
1440
1441 region->mmaps[1].offset = end;
1442 region->mmaps[1].size = region->size - end;
1443 trace_vfio_msix_fixup(vdev->vbasedev.name,
1444 vdev->msix->table_bar, region->mmaps[1].offset,
1445 region->mmaps[1].offset + region->mmaps[1].size);
1446 }
1447 }
1448
vfio_pci_relocate_msix(VFIOPCIDevice * vdev,Error ** errp)1449 static bool vfio_pci_relocate_msix(VFIOPCIDevice *vdev, Error **errp)
1450 {
1451 int target_bar = -1;
1452 size_t msix_sz;
1453
1454 if (!vdev->msix || vdev->msix_relo == OFF_AUTO_PCIBAR_OFF) {
1455 return true;
1456 }
1457
1458 /* The actual minimum size of MSI-X structures */
1459 msix_sz = (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE) +
1460 (QEMU_ALIGN_UP(vdev->msix->entries, 64) / 8);
1461 /* Round up to host pages, we don't want to share a page */
1462 msix_sz = REAL_HOST_PAGE_ALIGN(msix_sz);
1463 /* PCI BARs must be a power of 2 */
1464 msix_sz = pow2ceil(msix_sz);
1465
1466 if (vdev->msix_relo == OFF_AUTO_PCIBAR_AUTO) {
1467 /*
1468 * TODO: Lookup table for known devices.
1469 *
1470 * Logically we might use an algorithm here to select the BAR adding
1471 * the least additional MMIO space, but we cannot programmatically
1472 * predict the driver dependency on BAR ordering or sizing, therefore
1473 * 'auto' becomes a lookup for combinations reported to work.
1474 */
1475 if (target_bar < 0) {
1476 error_setg(errp, "No automatic MSI-X relocation available for "
1477 "device %04x:%04x", vdev->vendor_id, vdev->device_id);
1478 return false;
1479 }
1480 } else {
1481 target_bar = (int)(vdev->msix_relo - OFF_AUTO_PCIBAR_BAR0);
1482 }
1483
1484 /* I/O port BARs cannot host MSI-X structures */
1485 if (vdev->bars[target_bar].ioport) {
1486 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1487 "I/O port BAR", target_bar);
1488 return false;
1489 }
1490
1491 /* Cannot use a BAR in the "shadow" of a 64-bit BAR */
1492 if (!vdev->bars[target_bar].size &&
1493 target_bar > 0 && vdev->bars[target_bar - 1].mem64) {
1494 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1495 "consumed by 64-bit BAR %d", target_bar, target_bar - 1);
1496 return false;
1497 }
1498
1499 /* 2GB max size for 32-bit BARs, cannot double if already > 1G */
1500 if (vdev->bars[target_bar].size > 1 * GiB &&
1501 !vdev->bars[target_bar].mem64) {
1502 error_setg(errp, "Invalid MSI-X relocation BAR %d, "
1503 "no space to extend 32-bit BAR", target_bar);
1504 return false;
1505 }
1506
1507 /*
1508 * If adding a new BAR, test if we can make it 64bit. We make it
1509 * prefetchable since QEMU MSI-X emulation has no read side effects
1510 * and doing so makes mapping more flexible.
1511 */
1512 if (!vdev->bars[target_bar].size) {
1513 if (target_bar < (PCI_ROM_SLOT - 1) &&
1514 !vdev->bars[target_bar + 1].size) {
1515 vdev->bars[target_bar].mem64 = true;
1516 vdev->bars[target_bar].type = PCI_BASE_ADDRESS_MEM_TYPE_64;
1517 }
1518 vdev->bars[target_bar].type |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1519 vdev->bars[target_bar].size = msix_sz;
1520 vdev->msix->table_offset = 0;
1521 } else {
1522 vdev->bars[target_bar].size = MAX(vdev->bars[target_bar].size * 2,
1523 msix_sz * 2);
1524 /*
1525 * Due to above size calc, MSI-X always starts halfway into the BAR,
1526 * which will always be a separate host page.
1527 */
1528 vdev->msix->table_offset = vdev->bars[target_bar].size / 2;
1529 }
1530
1531 vdev->msix->table_bar = target_bar;
1532 vdev->msix->pba_bar = target_bar;
1533 /* Requires 8-byte alignment, but PCI_MSIX_ENTRY_SIZE guarantees that */
1534 vdev->msix->pba_offset = vdev->msix->table_offset +
1535 (vdev->msix->entries * PCI_MSIX_ENTRY_SIZE);
1536
1537 trace_vfio_msix_relo(vdev->vbasedev.name,
1538 vdev->msix->table_bar, vdev->msix->table_offset);
1539 return true;
1540 }
1541
1542 /*
1543 * We don't have any control over how pci_add_capability() inserts
1544 * capabilities into the chain. In order to setup MSI-X we need a
1545 * MemoryRegion for the BAR. In order to setup the BAR and not
1546 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
1547 * need to first look for where the MSI-X table lives. So we
1548 * unfortunately split MSI-X setup across two functions.
1549 */
vfio_msix_early_setup(VFIOPCIDevice * vdev,Error ** errp)1550 static bool vfio_msix_early_setup(VFIOPCIDevice *vdev, Error **errp)
1551 {
1552 uint8_t pos;
1553 uint16_t ctrl;
1554 uint32_t table, pba;
1555 int ret, fd = vdev->vbasedev.fd;
1556 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info),
1557 .index = VFIO_PCI_MSIX_IRQ_INDEX };
1558 VFIOMSIXInfo *msix;
1559
1560 pos = pci_find_capability(&vdev->pdev, PCI_CAP_ID_MSIX);
1561 if (!pos) {
1562 return true;
1563 }
1564
1565 if (pread(fd, &ctrl, sizeof(ctrl),
1566 vdev->config_offset + pos + PCI_MSIX_FLAGS) != sizeof(ctrl)) {
1567 error_setg_errno(errp, errno, "failed to read PCI MSIX FLAGS");
1568 return false;
1569 }
1570
1571 if (pread(fd, &table, sizeof(table),
1572 vdev->config_offset + pos + PCI_MSIX_TABLE) != sizeof(table)) {
1573 error_setg_errno(errp, errno, "failed to read PCI MSIX TABLE");
1574 return false;
1575 }
1576
1577 if (pread(fd, &pba, sizeof(pba),
1578 vdev->config_offset + pos + PCI_MSIX_PBA) != sizeof(pba)) {
1579 error_setg_errno(errp, errno, "failed to read PCI MSIX PBA");
1580 return false;
1581 }
1582
1583 ctrl = le16_to_cpu(ctrl);
1584 table = le32_to_cpu(table);
1585 pba = le32_to_cpu(pba);
1586
1587 msix = g_malloc0(sizeof(*msix));
1588 msix->table_bar = table & PCI_MSIX_FLAGS_BIRMASK;
1589 msix->table_offset = table & ~PCI_MSIX_FLAGS_BIRMASK;
1590 msix->pba_bar = pba & PCI_MSIX_FLAGS_BIRMASK;
1591 msix->pba_offset = pba & ~PCI_MSIX_FLAGS_BIRMASK;
1592 msix->entries = (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
1593
1594 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
1595 if (ret < 0) {
1596 error_setg_errno(errp, -ret, "failed to get MSI-X irq info");
1597 g_free(msix);
1598 return false;
1599 }
1600
1601 msix->noresize = !!(irq_info.flags & VFIO_IRQ_INFO_NORESIZE);
1602
1603 /*
1604 * Test the size of the pba_offset variable and catch if it extends outside
1605 * of the specified BAR. If it is the case, we need to apply a hardware
1606 * specific quirk if the device is known or we have a broken configuration.
1607 */
1608 if (msix->pba_offset >= vdev->bars[msix->pba_bar].region.size) {
1609 /*
1610 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5
1611 * adapters. The T5 hardware returns an incorrect value of 0x8000 for
1612 * the VF PBA offset while the BAR itself is only 8k. The correct value
1613 * is 0x1000, so we hard code that here.
1614 */
1615 if (vdev->vendor_id == PCI_VENDOR_ID_CHELSIO &&
1616 (vdev->device_id & 0xff00) == 0x5800) {
1617 msix->pba_offset = 0x1000;
1618 /*
1619 * BAIDU KUNLUN Virtual Function devices for KUNLUN AI processor
1620 * return an incorrect value of 0x460000 for the VF PBA offset while
1621 * the BAR itself is only 0x10000. The correct value is 0xb400.
1622 */
1623 } else if (vfio_pci_is(vdev, PCI_VENDOR_ID_BAIDU,
1624 PCI_DEVICE_ID_KUNLUN_VF)) {
1625 msix->pba_offset = 0xb400;
1626 } else if (vdev->msix_relo == OFF_AUTO_PCIBAR_OFF) {
1627 error_setg(errp, "hardware reports invalid configuration, "
1628 "MSIX PBA outside of specified BAR");
1629 g_free(msix);
1630 return false;
1631 }
1632 }
1633
1634 trace_vfio_msix_early_setup(vdev->vbasedev.name, pos, msix->table_bar,
1635 msix->table_offset, msix->entries,
1636 msix->noresize);
1637 vdev->msix = msix;
1638
1639 vfio_pci_fixup_msix_region(vdev);
1640
1641 return vfio_pci_relocate_msix(vdev, errp);
1642 }
1643
vfio_msix_setup(VFIOPCIDevice * vdev,int pos,Error ** errp)1644 static bool vfio_msix_setup(VFIOPCIDevice *vdev, int pos, Error **errp)
1645 {
1646 int ret;
1647 Error *err = NULL;
1648
1649 vdev->msix->pending = g_new0(unsigned long,
1650 BITS_TO_LONGS(vdev->msix->entries));
1651 ret = msix_init(&vdev->pdev, vdev->msix->entries,
1652 vdev->bars[vdev->msix->table_bar].mr,
1653 vdev->msix->table_bar, vdev->msix->table_offset,
1654 vdev->bars[vdev->msix->pba_bar].mr,
1655 vdev->msix->pba_bar, vdev->msix->pba_offset, pos,
1656 &err);
1657 if (ret < 0) {
1658 if (ret == -ENOTSUP) {
1659 warn_report_err(err);
1660 return true;
1661 }
1662
1663 error_propagate(errp, err);
1664 return false;
1665 }
1666
1667 /*
1668 * The PCI spec suggests that devices provide additional alignment for
1669 * MSI-X structures and avoid overlapping non-MSI-X related registers.
1670 * For an assigned device, this hopefully means that emulation of MSI-X
1671 * structures does not affect the performance of the device. If devices
1672 * fail to provide that alignment, a significant performance penalty may
1673 * result, for instance Mellanox MT27500 VFs:
1674 * http://www.spinics.net/lists/kvm/msg125881.html
1675 *
1676 * The PBA is simply not that important for such a serious regression and
1677 * most drivers do not appear to look at it. The solution for this is to
1678 * disable the PBA MemoryRegion unless it's being used. We disable it
1679 * here and only enable it if a masked vector fires through QEMU. As the
1680 * vector-use notifier is called, which occurs on unmask, we test whether
1681 * PBA emulation is needed and again disable if not.
1682 */
1683 memory_region_set_enabled(&vdev->pdev.msix_pba_mmio, false);
1684
1685 /*
1686 * The emulated machine may provide a paravirt interface for MSIX setup
1687 * so it is not strictly necessary to emulate MSIX here. This becomes
1688 * helpful when frequently accessed MMIO registers are located in
1689 * subpages adjacent to the MSIX table but the MSIX data containing page
1690 * cannot be mapped because of a host page size bigger than the MSIX table
1691 * alignment.
1692 */
1693 if (object_property_get_bool(OBJECT(qdev_get_machine()),
1694 "vfio-no-msix-emulation", NULL)) {
1695 memory_region_set_enabled(&vdev->pdev.msix_table_mmio, false);
1696 }
1697
1698 return true;
1699 }
1700
vfio_teardown_msi(VFIOPCIDevice * vdev)1701 static void vfio_teardown_msi(VFIOPCIDevice *vdev)
1702 {
1703 msi_uninit(&vdev->pdev);
1704
1705 if (vdev->msix) {
1706 msix_uninit(&vdev->pdev,
1707 vdev->bars[vdev->msix->table_bar].mr,
1708 vdev->bars[vdev->msix->pba_bar].mr);
1709 g_free(vdev->msix->pending);
1710 }
1711 }
1712
1713 /*
1714 * Resource setup
1715 */
vfio_mmap_set_enabled(VFIOPCIDevice * vdev,bool enabled)1716 static void vfio_mmap_set_enabled(VFIOPCIDevice *vdev, bool enabled)
1717 {
1718 int i;
1719
1720 for (i = 0; i < PCI_ROM_SLOT; i++) {
1721 vfio_region_mmaps_set_enabled(&vdev->bars[i].region, enabled);
1722 }
1723 }
1724
vfio_bar_prepare(VFIOPCIDevice * vdev,int nr)1725 static void vfio_bar_prepare(VFIOPCIDevice *vdev, int nr)
1726 {
1727 VFIOBAR *bar = &vdev->bars[nr];
1728
1729 uint32_t pci_bar;
1730 int ret;
1731
1732 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
1733 if (!bar->region.size) {
1734 return;
1735 }
1736
1737 /* Determine what type of BAR this is for registration */
1738 ret = pread(vdev->vbasedev.fd, &pci_bar, sizeof(pci_bar),
1739 vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr));
1740 if (ret != sizeof(pci_bar)) {
1741 error_report("vfio: Failed to read BAR %d (%m)", nr);
1742 return;
1743 }
1744
1745 pci_bar = le32_to_cpu(pci_bar);
1746 bar->ioport = (pci_bar & PCI_BASE_ADDRESS_SPACE_IO);
1747 bar->mem64 = bar->ioport ? 0 : (pci_bar & PCI_BASE_ADDRESS_MEM_TYPE_64);
1748 bar->type = pci_bar & (bar->ioport ? ~PCI_BASE_ADDRESS_IO_MASK :
1749 ~PCI_BASE_ADDRESS_MEM_MASK);
1750 bar->size = bar->region.size;
1751 }
1752
vfio_bars_prepare(VFIOPCIDevice * vdev)1753 static void vfio_bars_prepare(VFIOPCIDevice *vdev)
1754 {
1755 int i;
1756
1757 for (i = 0; i < PCI_ROM_SLOT; i++) {
1758 vfio_bar_prepare(vdev, i);
1759 }
1760 }
1761
vfio_bar_register(VFIOPCIDevice * vdev,int nr)1762 static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)
1763 {
1764 VFIOBAR *bar = &vdev->bars[nr];
1765 char *name;
1766
1767 if (!bar->size) {
1768 return;
1769 }
1770
1771 bar->mr = g_new0(MemoryRegion, 1);
1772 name = g_strdup_printf("%s base BAR %d", vdev->vbasedev.name, nr);
1773 memory_region_init_io(bar->mr, OBJECT(vdev), NULL, NULL, name, bar->size);
1774 g_free(name);
1775
1776 if (bar->region.size) {
1777 memory_region_add_subregion(bar->mr, 0, bar->region.mem);
1778
1779 if (vfio_region_mmap(&bar->region)) {
1780 error_report("Failed to mmap %s BAR %d. Performance may be slow",
1781 vdev->vbasedev.name, nr);
1782 }
1783 }
1784
1785 pci_register_bar(&vdev->pdev, nr, bar->type, bar->mr);
1786 }
1787
vfio_bars_register(VFIOPCIDevice * vdev)1788 static void vfio_bars_register(VFIOPCIDevice *vdev)
1789 {
1790 int i;
1791
1792 for (i = 0; i < PCI_ROM_SLOT; i++) {
1793 vfio_bar_register(vdev, i);
1794 }
1795 }
1796
vfio_bars_exit(VFIOPCIDevice * vdev)1797 static void vfio_bars_exit(VFIOPCIDevice *vdev)
1798 {
1799 int i;
1800
1801 for (i = 0; i < PCI_ROM_SLOT; i++) {
1802 VFIOBAR *bar = &vdev->bars[i];
1803
1804 vfio_bar_quirk_exit(vdev, i);
1805 vfio_region_exit(&bar->region);
1806 if (bar->region.size) {
1807 memory_region_del_subregion(bar->mr, bar->region.mem);
1808 }
1809 }
1810
1811 if (vdev->vga) {
1812 pci_unregister_vga(&vdev->pdev);
1813 vfio_vga_quirk_exit(vdev);
1814 }
1815 }
1816
vfio_bars_finalize(VFIOPCIDevice * vdev)1817 static void vfio_bars_finalize(VFIOPCIDevice *vdev)
1818 {
1819 int i;
1820
1821 for (i = 0; i < PCI_ROM_SLOT; i++) {
1822 VFIOBAR *bar = &vdev->bars[i];
1823
1824 vfio_bar_quirk_finalize(vdev, i);
1825 vfio_region_finalize(&bar->region);
1826 if (bar->mr) {
1827 assert(bar->size);
1828 object_unparent(OBJECT(bar->mr));
1829 g_free(bar->mr);
1830 bar->mr = NULL;
1831 }
1832 }
1833
1834 if (vdev->vga) {
1835 vfio_vga_quirk_finalize(vdev);
1836 for (i = 0; i < ARRAY_SIZE(vdev->vga->region); i++) {
1837 object_unparent(OBJECT(&vdev->vga->region[i].mem));
1838 }
1839 g_free(vdev->vga);
1840 }
1841 }
1842
1843 /*
1844 * General setup
1845 */
vfio_std_cap_max_size(PCIDevice * pdev,uint8_t pos)1846 static uint8_t vfio_std_cap_max_size(PCIDevice *pdev, uint8_t pos)
1847 {
1848 uint8_t tmp;
1849 uint16_t next = PCI_CONFIG_SPACE_SIZE;
1850
1851 for (tmp = pdev->config[PCI_CAPABILITY_LIST]; tmp;
1852 tmp = pdev->config[tmp + PCI_CAP_LIST_NEXT]) {
1853 if (tmp > pos && tmp < next) {
1854 next = tmp;
1855 }
1856 }
1857
1858 return next - pos;
1859 }
1860
1861
vfio_ext_cap_max_size(const uint8_t * config,uint16_t pos)1862 static uint16_t vfio_ext_cap_max_size(const uint8_t *config, uint16_t pos)
1863 {
1864 uint16_t tmp, next = PCIE_CONFIG_SPACE_SIZE;
1865
1866 for (tmp = PCI_CONFIG_SPACE_SIZE; tmp;
1867 tmp = PCI_EXT_CAP_NEXT(pci_get_long(config + tmp))) {
1868 if (tmp > pos && tmp < next) {
1869 next = tmp;
1870 }
1871 }
1872
1873 return next - pos;
1874 }
1875
vfio_set_word_bits(uint8_t * buf,uint16_t val,uint16_t mask)1876 static void vfio_set_word_bits(uint8_t *buf, uint16_t val, uint16_t mask)
1877 {
1878 pci_set_word(buf, (pci_get_word(buf) & ~mask) | val);
1879 }
1880
vfio_add_emulated_word(VFIOPCIDevice * vdev,int pos,uint16_t val,uint16_t mask)1881 static void vfio_add_emulated_word(VFIOPCIDevice *vdev, int pos,
1882 uint16_t val, uint16_t mask)
1883 {
1884 vfio_set_word_bits(vdev->pdev.config + pos, val, mask);
1885 vfio_set_word_bits(vdev->pdev.wmask + pos, ~mask, mask);
1886 vfio_set_word_bits(vdev->emulated_config_bits + pos, mask, mask);
1887 }
1888
vfio_set_long_bits(uint8_t * buf,uint32_t val,uint32_t mask)1889 static void vfio_set_long_bits(uint8_t *buf, uint32_t val, uint32_t mask)
1890 {
1891 pci_set_long(buf, (pci_get_long(buf) & ~mask) | val);
1892 }
1893
vfio_add_emulated_long(VFIOPCIDevice * vdev,int pos,uint32_t val,uint32_t mask)1894 static void vfio_add_emulated_long(VFIOPCIDevice *vdev, int pos,
1895 uint32_t val, uint32_t mask)
1896 {
1897 vfio_set_long_bits(vdev->pdev.config + pos, val, mask);
1898 vfio_set_long_bits(vdev->pdev.wmask + pos, ~mask, mask);
1899 vfio_set_long_bits(vdev->emulated_config_bits + pos, mask, mask);
1900 }
1901
vfio_pci_enable_rp_atomics(VFIOPCIDevice * vdev)1902 static void vfio_pci_enable_rp_atomics(VFIOPCIDevice *vdev)
1903 {
1904 struct vfio_device_info_cap_pci_atomic_comp *cap;
1905 g_autofree struct vfio_device_info *info = NULL;
1906 PCIBus *bus = pci_get_bus(&vdev->pdev);
1907 PCIDevice *parent = bus->parent_dev;
1908 struct vfio_info_cap_header *hdr;
1909 uint32_t mask = 0;
1910 uint8_t *pos;
1911
1912 /*
1913 * PCIe Atomic Ops completer support is only added automatically for single
1914 * function devices downstream of a root port supporting DEVCAP2. Support
1915 * is added during realize and, if added, removed during device exit. The
1916 * single function requirement avoids conflicting requirements should a
1917 * slot be composed of multiple devices with differing capabilities.
1918 */
1919 if (pci_bus_is_root(bus) || !parent || !parent->exp.exp_cap ||
1920 pcie_cap_get_type(parent) != PCI_EXP_TYPE_ROOT_PORT ||
1921 pcie_cap_get_version(parent) != PCI_EXP_FLAGS_VER2 ||
1922 vdev->pdev.devfn ||
1923 vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
1924 return;
1925 }
1926
1927 pos = parent->config + parent->exp.exp_cap + PCI_EXP_DEVCAP2;
1928
1929 /* Abort if there'a already an Atomic Ops configuration on the root port */
1930 if (pci_get_long(pos) & (PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1931 PCI_EXP_DEVCAP2_ATOMIC_COMP64 |
1932 PCI_EXP_DEVCAP2_ATOMIC_COMP128)) {
1933 return;
1934 }
1935
1936 info = vfio_get_device_info(vdev->vbasedev.fd);
1937 if (!info) {
1938 return;
1939 }
1940
1941 hdr = vfio_get_device_info_cap(info, VFIO_DEVICE_INFO_CAP_PCI_ATOMIC_COMP);
1942 if (!hdr) {
1943 return;
1944 }
1945
1946 cap = (void *)hdr;
1947 if (cap->flags & VFIO_PCI_ATOMIC_COMP32) {
1948 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP32;
1949 }
1950 if (cap->flags & VFIO_PCI_ATOMIC_COMP64) {
1951 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP64;
1952 }
1953 if (cap->flags & VFIO_PCI_ATOMIC_COMP128) {
1954 mask |= PCI_EXP_DEVCAP2_ATOMIC_COMP128;
1955 }
1956
1957 if (!mask) {
1958 return;
1959 }
1960
1961 pci_long_test_and_set_mask(pos, mask);
1962 vdev->clear_parent_atomics_on_exit = true;
1963 }
1964
vfio_pci_disable_rp_atomics(VFIOPCIDevice * vdev)1965 static void vfio_pci_disable_rp_atomics(VFIOPCIDevice *vdev)
1966 {
1967 if (vdev->clear_parent_atomics_on_exit) {
1968 PCIDevice *parent = pci_get_bus(&vdev->pdev)->parent_dev;
1969 uint8_t *pos = parent->config + parent->exp.exp_cap + PCI_EXP_DEVCAP2;
1970
1971 pci_long_test_and_clear_mask(pos, PCI_EXP_DEVCAP2_ATOMIC_COMP32 |
1972 PCI_EXP_DEVCAP2_ATOMIC_COMP64 |
1973 PCI_EXP_DEVCAP2_ATOMIC_COMP128);
1974 }
1975 }
1976
vfio_setup_pcie_cap(VFIOPCIDevice * vdev,int pos,uint8_t size,Error ** errp)1977 static bool vfio_setup_pcie_cap(VFIOPCIDevice *vdev, int pos, uint8_t size,
1978 Error **errp)
1979 {
1980 uint16_t flags;
1981 uint8_t type;
1982
1983 flags = pci_get_word(vdev->pdev.config + pos + PCI_CAP_FLAGS);
1984 type = (flags & PCI_EXP_FLAGS_TYPE) >> 4;
1985
1986 if (type != PCI_EXP_TYPE_ENDPOINT &&
1987 type != PCI_EXP_TYPE_LEG_END &&
1988 type != PCI_EXP_TYPE_RC_END) {
1989
1990 error_setg(errp, "assignment of PCIe type 0x%x "
1991 "devices is not currently supported", type);
1992 return false;
1993 }
1994
1995 if (!pci_bus_is_express(pci_get_bus(&vdev->pdev))) {
1996 PCIBus *bus = pci_get_bus(&vdev->pdev);
1997 PCIDevice *bridge;
1998
1999 /*
2000 * Traditionally PCI device assignment exposes the PCIe capability
2001 * as-is on non-express buses. The reason being that some drivers
2002 * simply assume that it's there, for example tg3. However when
2003 * we're running on a native PCIe machine type, like Q35, we need
2004 * to hide the PCIe capability. The reason for this is twofold;
2005 * first Windows guests get a Code 10 error when the PCIe capability
2006 * is exposed in this configuration. Therefore express devices won't
2007 * work at all unless they're attached to express buses in the VM.
2008 * Second, a native PCIe machine introduces the possibility of fine
2009 * granularity IOMMUs supporting both translation and isolation.
2010 * Guest code to discover the IOMMU visibility of a device, such as
2011 * IOMMU grouping code on Linux, is very aware of device types and
2012 * valid transitions between bus types. An express device on a non-
2013 * express bus is not a valid combination on bare metal systems.
2014 *
2015 * Drivers that require a PCIe capability to make the device
2016 * functional are simply going to need to have their devices placed
2017 * on a PCIe bus in the VM.
2018 */
2019 while (!pci_bus_is_root(bus)) {
2020 bridge = pci_bridge_get_device(bus);
2021 bus = pci_get_bus(bridge);
2022 }
2023
2024 if (pci_bus_is_express(bus)) {
2025 return true;
2026 }
2027
2028 } else if (pci_bus_is_root(pci_get_bus(&vdev->pdev))) {
2029 /*
2030 * On a Root Complex bus Endpoints become Root Complex Integrated
2031 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2032 */
2033 if (type == PCI_EXP_TYPE_ENDPOINT) {
2034 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2035 PCI_EXP_TYPE_RC_END << 4,
2036 PCI_EXP_FLAGS_TYPE);
2037
2038 /* Link Capabilities, Status, and Control goes away */
2039 if (size > PCI_EXP_LNKCTL) {
2040 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP, 0, ~0);
2041 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2042 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA, 0, ~0);
2043
2044 #ifndef PCI_EXP_LNKCAP2
2045 #define PCI_EXP_LNKCAP2 44
2046 #endif
2047 #ifndef PCI_EXP_LNKSTA2
2048 #define PCI_EXP_LNKSTA2 50
2049 #endif
2050 /* Link 2 Capabilities, Status, and Control goes away */
2051 if (size > PCI_EXP_LNKCAP2) {
2052 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP2, 0, ~0);
2053 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL2, 0, ~0);
2054 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKSTA2, 0, ~0);
2055 }
2056 }
2057
2058 } else if (type == PCI_EXP_TYPE_LEG_END) {
2059 /*
2060 * Legacy endpoints don't belong on the root complex. Windows
2061 * seems to be happier with devices if we skip the capability.
2062 */
2063 return true;
2064 }
2065
2066 } else {
2067 /*
2068 * Convert Root Complex Integrated Endpoints to regular endpoints.
2069 * These devices don't support LNK/LNK2 capabilities, so make them up.
2070 */
2071 if (type == PCI_EXP_TYPE_RC_END) {
2072 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2073 PCI_EXP_TYPE_ENDPOINT << 4,
2074 PCI_EXP_FLAGS_TYPE);
2075 vfio_add_emulated_long(vdev, pos + PCI_EXP_LNKCAP,
2076 QEMU_PCI_EXP_LNKCAP_MLW(QEMU_PCI_EXP_LNK_X1) |
2077 QEMU_PCI_EXP_LNKCAP_MLS(QEMU_PCI_EXP_LNK_2_5GT), ~0);
2078 vfio_add_emulated_word(vdev, pos + PCI_EXP_LNKCTL, 0, ~0);
2079 }
2080
2081 vfio_pci_enable_rp_atomics(vdev);
2082 }
2083
2084 /*
2085 * Intel 82599 SR-IOV VFs report an invalid PCIe capability version 0
2086 * (Niantic errate #35) causing Windows to error with a Code 10 for the
2087 * device on Q35. Fixup any such devices to report version 1. If we
2088 * were to remove the capability entirely the guest would lose extended
2089 * config space.
2090 */
2091 if ((flags & PCI_EXP_FLAGS_VERS) == 0) {
2092 vfio_add_emulated_word(vdev, pos + PCI_CAP_FLAGS,
2093 1, PCI_EXP_FLAGS_VERS);
2094 }
2095
2096 pos = pci_add_capability(&vdev->pdev, PCI_CAP_ID_EXP, pos, size,
2097 errp);
2098 if (pos < 0) {
2099 return false;
2100 }
2101
2102 vdev->pdev.exp.exp_cap = pos;
2103
2104 return true;
2105 }
2106
vfio_check_pcie_flr(VFIOPCIDevice * vdev,uint8_t pos)2107 static void vfio_check_pcie_flr(VFIOPCIDevice *vdev, uint8_t pos)
2108 {
2109 uint32_t cap = pci_get_long(vdev->pdev.config + pos + PCI_EXP_DEVCAP);
2110
2111 if (cap & PCI_EXP_DEVCAP_FLR) {
2112 trace_vfio_check_pcie_flr(vdev->vbasedev.name);
2113 vdev->has_flr = true;
2114 }
2115 }
2116
vfio_check_pm_reset(VFIOPCIDevice * vdev,uint8_t pos)2117 static void vfio_check_pm_reset(VFIOPCIDevice *vdev, uint8_t pos)
2118 {
2119 uint16_t csr = pci_get_word(vdev->pdev.config + pos + PCI_PM_CTRL);
2120
2121 if (!(csr & PCI_PM_CTRL_NO_SOFT_RESET)) {
2122 trace_vfio_check_pm_reset(vdev->vbasedev.name);
2123 vdev->has_pm_reset = true;
2124 }
2125 }
2126
vfio_check_af_flr(VFIOPCIDevice * vdev,uint8_t pos)2127 static void vfio_check_af_flr(VFIOPCIDevice *vdev, uint8_t pos)
2128 {
2129 uint8_t cap = pci_get_byte(vdev->pdev.config + pos + PCI_AF_CAP);
2130
2131 if ((cap & PCI_AF_CAP_TP) && (cap & PCI_AF_CAP_FLR)) {
2132 trace_vfio_check_af_flr(vdev->vbasedev.name);
2133 vdev->has_flr = true;
2134 }
2135 }
2136
vfio_add_vendor_specific_cap(VFIOPCIDevice * vdev,int pos,uint8_t size,Error ** errp)2137 static bool vfio_add_vendor_specific_cap(VFIOPCIDevice *vdev, int pos,
2138 uint8_t size, Error **errp)
2139 {
2140 PCIDevice *pdev = &vdev->pdev;
2141
2142 pos = pci_add_capability(pdev, PCI_CAP_ID_VNDR, pos, size, errp);
2143 if (pos < 0) {
2144 return false;
2145 }
2146
2147 /*
2148 * Exempt config space check for Vendor Specific Information during
2149 * restore/load.
2150 * Config space check is still enforced for 3 byte VSC header.
2151 */
2152 if (vdev->skip_vsc_check && size > 3) {
2153 memset(pdev->cmask + pos + 3, 0, size - 3);
2154 }
2155
2156 return true;
2157 }
2158
vfio_add_std_cap(VFIOPCIDevice * vdev,uint8_t pos,Error ** errp)2159 static bool vfio_add_std_cap(VFIOPCIDevice *vdev, uint8_t pos, Error **errp)
2160 {
2161 ERRP_GUARD();
2162 PCIDevice *pdev = &vdev->pdev;
2163 uint8_t cap_id, next, size;
2164 bool ret;
2165
2166 cap_id = pdev->config[pos];
2167 next = pdev->config[pos + PCI_CAP_LIST_NEXT];
2168
2169 /*
2170 * If it becomes important to configure capabilities to their actual
2171 * size, use this as the default when it's something we don't recognize.
2172 * Since QEMU doesn't actually handle many of the config accesses,
2173 * exact size doesn't seem worthwhile.
2174 */
2175 size = vfio_std_cap_max_size(pdev, pos);
2176
2177 /*
2178 * pci_add_capability always inserts the new capability at the head
2179 * of the chain. Therefore to end up with a chain that matches the
2180 * physical device, we insert from the end by making this recursive.
2181 * This is also why we pre-calculate size above as cached config space
2182 * will be changed as we unwind the stack.
2183 */
2184 if (next) {
2185 if (!vfio_add_std_cap(vdev, next, errp)) {
2186 return false;
2187 }
2188 } else {
2189 /* Begin the rebuild, use QEMU emulated list bits */
2190 pdev->config[PCI_CAPABILITY_LIST] = 0;
2191 vdev->emulated_config_bits[PCI_CAPABILITY_LIST] = 0xff;
2192 vdev->emulated_config_bits[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
2193
2194 if (!vfio_add_virt_caps(vdev, errp)) {
2195 return false;
2196 }
2197 }
2198
2199 /* Scale down size, esp in case virt caps were added above */
2200 size = MIN(size, vfio_std_cap_max_size(pdev, pos));
2201
2202 /* Use emulated next pointer to allow dropping caps */
2203 pci_set_byte(vdev->emulated_config_bits + pos + PCI_CAP_LIST_NEXT, 0xff);
2204
2205 switch (cap_id) {
2206 case PCI_CAP_ID_MSI:
2207 ret = vfio_msi_setup(vdev, pos, errp);
2208 break;
2209 case PCI_CAP_ID_EXP:
2210 vfio_check_pcie_flr(vdev, pos);
2211 ret = vfio_setup_pcie_cap(vdev, pos, size, errp);
2212 break;
2213 case PCI_CAP_ID_MSIX:
2214 ret = vfio_msix_setup(vdev, pos, errp);
2215 break;
2216 case PCI_CAP_ID_PM:
2217 vfio_check_pm_reset(vdev, pos);
2218 ret = pci_pm_init(pdev, pos, errp) >= 0;
2219 /*
2220 * PCI-core config space emulation needs write access to the power
2221 * state enabled for tracking BAR mapping relative to PM state.
2222 */
2223 pci_set_word(pdev->wmask + pos + PCI_PM_CTRL, PCI_PM_CTRL_STATE_MASK);
2224 break;
2225 case PCI_CAP_ID_AF:
2226 vfio_check_af_flr(vdev, pos);
2227 ret = pci_add_capability(pdev, cap_id, pos, size, errp) >= 0;
2228 break;
2229 case PCI_CAP_ID_VNDR:
2230 ret = vfio_add_vendor_specific_cap(vdev, pos, size, errp);
2231 break;
2232 default:
2233 ret = pci_add_capability(pdev, cap_id, pos, size, errp) >= 0;
2234 break;
2235 }
2236
2237 if (!ret) {
2238 error_prepend(errp,
2239 "failed to add PCI capability 0x%x[0x%x]@0x%x: ",
2240 cap_id, size, pos);
2241 }
2242
2243 return ret;
2244 }
2245
vfio_setup_rebar_ecap(VFIOPCIDevice * vdev,uint16_t pos)2246 static int vfio_setup_rebar_ecap(VFIOPCIDevice *vdev, uint16_t pos)
2247 {
2248 uint32_t ctrl;
2249 int i, nbar;
2250
2251 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL);
2252 nbar = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> PCI_REBAR_CTRL_NBAR_SHIFT;
2253
2254 for (i = 0; i < nbar; i++) {
2255 uint32_t cap;
2256 int size;
2257
2258 ctrl = pci_get_long(vdev->pdev.config + pos + PCI_REBAR_CTRL + (i * 8));
2259 size = (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
2260
2261 /* The cap register reports sizes 1MB to 128TB, with 4 reserved bits */
2262 cap = size <= 27 ? 1U << (size + 4) : 0;
2263
2264 /*
2265 * The PCIe spec (v6.0.1, 7.8.6) requires HW to support at least one
2266 * size in the range 1MB to 512GB. We intend to mask all sizes except
2267 * the one currently enabled in the size field, therefore if it's
2268 * outside the range, hide the whole capability as this virtualization
2269 * trick won't work. If >512GB resizable BARs start to appear, we
2270 * might need an opt-in or reservation scheme in the kernel.
2271 */
2272 if (!(cap & PCI_REBAR_CAP_SIZES)) {
2273 return -EINVAL;
2274 }
2275
2276 /* Hide all sizes reported in the ctrl reg per above requirement. */
2277 ctrl &= (PCI_REBAR_CTRL_BAR_SIZE |
2278 PCI_REBAR_CTRL_NBAR_MASK |
2279 PCI_REBAR_CTRL_BAR_IDX);
2280
2281 /*
2282 * The BAR size field is RW, however we've mangled the capability
2283 * register such that we only report a single size, ie. the current
2284 * BAR size. A write of an unsupported value is undefined, therefore
2285 * the register field is essentially RO.
2286 */
2287 vfio_add_emulated_long(vdev, pos + PCI_REBAR_CAP + (i * 8), cap, ~0);
2288 vfio_add_emulated_long(vdev, pos + PCI_REBAR_CTRL + (i * 8), ctrl, ~0);
2289 }
2290
2291 return 0;
2292 }
2293
vfio_add_ext_cap(VFIOPCIDevice * vdev)2294 static void vfio_add_ext_cap(VFIOPCIDevice *vdev)
2295 {
2296 PCIDevice *pdev = &vdev->pdev;
2297 uint32_t header;
2298 uint16_t cap_id, next, size;
2299 uint8_t cap_ver;
2300 uint8_t *config;
2301
2302 /* Only add extended caps if we have them and the guest can see them */
2303 if (!pci_is_express(pdev) || !pci_bus_is_express(pci_get_bus(pdev)) ||
2304 !pci_get_long(pdev->config + PCI_CONFIG_SPACE_SIZE)) {
2305 return;
2306 }
2307
2308 /*
2309 * pcie_add_capability always inserts the new capability at the tail
2310 * of the chain. Therefore to end up with a chain that matches the
2311 * physical device, we cache the config space to avoid overwriting
2312 * the original config space when we parse the extended capabilities.
2313 */
2314 config = g_memdup(pdev->config, vdev->config_size);
2315
2316 /*
2317 * Extended capabilities are chained with each pointing to the next, so we
2318 * can drop anything other than the head of the chain simply by modifying
2319 * the previous next pointer. Seed the head of the chain here such that
2320 * we can simply skip any capabilities we want to drop below, regardless
2321 * of their position in the chain. If this stub capability still exists
2322 * after we add the capabilities we want to expose, update the capability
2323 * ID to zero. Note that we cannot seed with the capability header being
2324 * zero as this conflicts with definition of an absent capability chain
2325 * and prevents capabilities beyond the head of the list from being added.
2326 * By replacing the dummy capability ID with zero after walking the device
2327 * chain, we also transparently mark extended capabilities as absent if
2328 * no capabilities were added. Note that the PCIe spec defines an absence
2329 * of extended capabilities to be determined by a value of zero for the
2330 * capability ID, version, AND next pointer. A non-zero next pointer
2331 * should be sufficient to indicate additional capabilities are present,
2332 * which will occur if we call pcie_add_capability() below. The entire
2333 * first dword is emulated to support this.
2334 *
2335 * NB. The kernel side does similar masking, so be prepared that our
2336 * view of the device may also contain a capability ID zero in the head
2337 * of the chain. Skip it for the same reason that we cannot seed the
2338 * chain with a zero capability.
2339 */
2340 pci_set_long(pdev->config + PCI_CONFIG_SPACE_SIZE,
2341 PCI_EXT_CAP(0xFFFF, 0, 0));
2342 pci_set_long(pdev->wmask + PCI_CONFIG_SPACE_SIZE, 0);
2343 pci_set_long(vdev->emulated_config_bits + PCI_CONFIG_SPACE_SIZE, ~0);
2344
2345 for (next = PCI_CONFIG_SPACE_SIZE; next;
2346 next = PCI_EXT_CAP_NEXT(pci_get_long(config + next))) {
2347 header = pci_get_long(config + next);
2348 cap_id = PCI_EXT_CAP_ID(header);
2349 cap_ver = PCI_EXT_CAP_VER(header);
2350
2351 /*
2352 * If it becomes important to configure extended capabilities to their
2353 * actual size, use this as the default when it's something we don't
2354 * recognize. Since QEMU doesn't actually handle many of the config
2355 * accesses, exact size doesn't seem worthwhile.
2356 */
2357 size = vfio_ext_cap_max_size(config, next);
2358
2359 /* Use emulated next pointer to allow dropping extended caps */
2360 pci_long_test_and_set_mask(vdev->emulated_config_bits + next,
2361 PCI_EXT_CAP_NEXT_MASK);
2362
2363 switch (cap_id) {
2364 case 0: /* kernel masked capability */
2365 case PCI_EXT_CAP_ID_SRIOV: /* Read-only VF BARs confuse OVMF */
2366 case PCI_EXT_CAP_ID_ARI: /* XXX Needs next function virtualization */
2367 trace_vfio_add_ext_cap_dropped(vdev->vbasedev.name, cap_id, next);
2368 break;
2369 case PCI_EXT_CAP_ID_REBAR:
2370 if (!vfio_setup_rebar_ecap(vdev, next)) {
2371 pcie_add_capability(pdev, cap_id, cap_ver, next, size);
2372 }
2373 break;
2374 default:
2375 pcie_add_capability(pdev, cap_id, cap_ver, next, size);
2376 }
2377
2378 }
2379
2380 /* Cleanup chain head ID if necessary */
2381 if (pci_get_word(pdev->config + PCI_CONFIG_SPACE_SIZE) == 0xFFFF) {
2382 pci_set_word(pdev->config + PCI_CONFIG_SPACE_SIZE, 0);
2383 }
2384
2385 g_free(config);
2386 return;
2387 }
2388
vfio_add_capabilities(VFIOPCIDevice * vdev,Error ** errp)2389 static bool vfio_add_capabilities(VFIOPCIDevice *vdev, Error **errp)
2390 {
2391 PCIDevice *pdev = &vdev->pdev;
2392
2393 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST) ||
2394 !pdev->config[PCI_CAPABILITY_LIST]) {
2395 return true; /* Nothing to add */
2396 }
2397
2398 if (!vfio_add_std_cap(vdev, pdev->config[PCI_CAPABILITY_LIST], errp)) {
2399 return false;
2400 }
2401
2402 vfio_add_ext_cap(vdev);
2403 return true;
2404 }
2405
vfio_pci_pre_reset(VFIOPCIDevice * vdev)2406 void vfio_pci_pre_reset(VFIOPCIDevice *vdev)
2407 {
2408 PCIDevice *pdev = &vdev->pdev;
2409 uint16_t cmd;
2410
2411 vfio_disable_interrupts(vdev);
2412
2413 /*
2414 * Stop any ongoing DMA by disconnecting I/O, MMIO, and bus master.
2415 * Also put INTx Disable in known state.
2416 */
2417 cmd = vfio_pci_read_config(pdev, PCI_COMMAND, 2);
2418 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
2419 PCI_COMMAND_INTX_DISABLE);
2420 vfio_pci_write_config(pdev, PCI_COMMAND, cmd, 2);
2421
2422 /* Make sure the device is in D0 */
2423 if (pdev->pm_cap) {
2424 uint16_t pmcsr;
2425 uint8_t state;
2426
2427 pmcsr = vfio_pci_read_config(pdev, pdev->pm_cap + PCI_PM_CTRL, 2);
2428 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2429 if (state) {
2430 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2431 vfio_pci_write_config(pdev, pdev->pm_cap + PCI_PM_CTRL, pmcsr, 2);
2432 /* vfio handles the necessary delay here */
2433 pmcsr = vfio_pci_read_config(pdev, pdev->pm_cap + PCI_PM_CTRL, 2);
2434 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
2435 if (state) {
2436 error_report("vfio: Unable to power on device, stuck in D%d",
2437 state);
2438 }
2439 }
2440 }
2441 }
2442
vfio_pci_post_reset(VFIOPCIDevice * vdev)2443 void vfio_pci_post_reset(VFIOPCIDevice *vdev)
2444 {
2445 Error *err = NULL;
2446 int nr;
2447
2448 if (!vfio_intx_enable(vdev, &err)) {
2449 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2450 }
2451
2452 for (nr = 0; nr < PCI_NUM_REGIONS - 1; ++nr) {
2453 off_t addr = vdev->config_offset + PCI_BASE_ADDRESS_0 + (4 * nr);
2454 uint32_t val = 0;
2455 uint32_t len = sizeof(val);
2456
2457 if (pwrite(vdev->vbasedev.fd, &val, len, addr) != len) {
2458 error_report("%s(%s) reset bar %d failed: %m", __func__,
2459 vdev->vbasedev.name, nr);
2460 }
2461 }
2462
2463 vfio_quirk_reset(vdev);
2464 }
2465
vfio_pci_host_match(PCIHostDeviceAddress * addr,const char * name)2466 bool vfio_pci_host_match(PCIHostDeviceAddress *addr, const char *name)
2467 {
2468 char tmp[13];
2469
2470 sprintf(tmp, "%04x:%02x:%02x.%1x", addr->domain,
2471 addr->bus, addr->slot, addr->function);
2472
2473 return (strcmp(tmp, name) == 0);
2474 }
2475
vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice * vdev,struct vfio_pci_hot_reset_info ** info_p)2476 int vfio_pci_get_pci_hot_reset_info(VFIOPCIDevice *vdev,
2477 struct vfio_pci_hot_reset_info **info_p)
2478 {
2479 struct vfio_pci_hot_reset_info *info;
2480 int ret, count;
2481
2482 assert(info_p && !*info_p);
2483
2484 info = g_malloc0(sizeof(*info));
2485 info->argsz = sizeof(*info);
2486
2487 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2488 if (ret && errno != ENOSPC) {
2489 ret = -errno;
2490 g_free(info);
2491 if (!vdev->has_pm_reset) {
2492 error_report("vfio: Cannot reset device %s, "
2493 "no available reset mechanism.", vdev->vbasedev.name);
2494 }
2495 return ret;
2496 }
2497
2498 count = info->count;
2499 info = g_realloc(info, sizeof(*info) + (count * sizeof(info->devices[0])));
2500 info->argsz = sizeof(*info) + (count * sizeof(info->devices[0]));
2501
2502 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, info);
2503 if (ret) {
2504 ret = -errno;
2505 g_free(info);
2506 error_report("vfio: hot reset info failed: %m");
2507 return ret;
2508 }
2509
2510 *info_p = info;
2511 return 0;
2512 }
2513
vfio_pci_hot_reset(VFIOPCIDevice * vdev,bool single)2514 static int vfio_pci_hot_reset(VFIOPCIDevice *vdev, bool single)
2515 {
2516 VFIODevice *vbasedev = &vdev->vbasedev;
2517 const VFIOIOMMUClass *vioc = VFIO_IOMMU_GET_CLASS(vbasedev->bcontainer);
2518
2519 return vioc->pci_hot_reset(vbasedev, single);
2520 }
2521
2522 /*
2523 * We want to differentiate hot reset of multiple in-use devices vs hot reset
2524 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case
2525 * of doing hot resets when there is only a single device per bus. The in-use
2526 * here refers to how many VFIODevices are affected. A hot reset that affects
2527 * multiple devices, but only a single in-use device, means that we can call
2528 * it from our bus ->reset() callback since the extent is effectively a single
2529 * device. This allows us to make use of it in the hotplug path. When there
2530 * are multiple in-use devices, we can only trigger the hot reset during a
2531 * system reset and thus from our reset handler. We separate _one vs _multi
2532 * here so that we don't overlap and do a double reset on the system reset
2533 * path where both our reset handler and ->reset() callback are used. Calling
2534 * _one() will only do a hot reset for the one in-use devices case, calling
2535 * _multi() will do nothing if a _one() would have been sufficient.
2536 */
vfio_pci_hot_reset_one(VFIOPCIDevice * vdev)2537 static int vfio_pci_hot_reset_one(VFIOPCIDevice *vdev)
2538 {
2539 return vfio_pci_hot_reset(vdev, true);
2540 }
2541
vfio_pci_hot_reset_multi(VFIODevice * vbasedev)2542 static int vfio_pci_hot_reset_multi(VFIODevice *vbasedev)
2543 {
2544 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2545 return vfio_pci_hot_reset(vdev, false);
2546 }
2547
vfio_pci_compute_needs_reset(VFIODevice * vbasedev)2548 static void vfio_pci_compute_needs_reset(VFIODevice *vbasedev)
2549 {
2550 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2551 if (!vbasedev->reset_works || (!vdev->has_flr && vdev->has_pm_reset)) {
2552 vbasedev->needs_reset = true;
2553 }
2554 }
2555
vfio_pci_get_object(VFIODevice * vbasedev)2556 static Object *vfio_pci_get_object(VFIODevice *vbasedev)
2557 {
2558 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2559
2560 return OBJECT(vdev);
2561 }
2562
vfio_msix_present(void * opaque,int version_id)2563 static bool vfio_msix_present(void *opaque, int version_id)
2564 {
2565 PCIDevice *pdev = opaque;
2566
2567 return msix_present(pdev);
2568 }
2569
vfio_display_migration_needed(void * opaque)2570 static bool vfio_display_migration_needed(void *opaque)
2571 {
2572 VFIOPCIDevice *vdev = opaque;
2573
2574 /*
2575 * We need to migrate the VFIODisplay object if ramfb *migration* was
2576 * explicitly requested (in which case we enforced both ramfb=on and
2577 * display=on), or ramfb migration was left at the default "auto"
2578 * setting, and *ramfb* was explicitly requested (in which case we
2579 * enforced display=on).
2580 */
2581 return vdev->ramfb_migrate == ON_OFF_AUTO_ON ||
2582 (vdev->ramfb_migrate == ON_OFF_AUTO_AUTO && vdev->enable_ramfb);
2583 }
2584
2585 static const VMStateDescription vmstate_vfio_display = {
2586 .name = "VFIOPCIDevice/VFIODisplay",
2587 .version_id = 1,
2588 .minimum_version_id = 1,
2589 .needed = vfio_display_migration_needed,
2590 .fields = (const VMStateField[]){
2591 VMSTATE_STRUCT_POINTER(dpy, VFIOPCIDevice, vfio_display_vmstate,
2592 VFIODisplay),
2593 VMSTATE_END_OF_LIST()
2594 }
2595 };
2596
2597 static const VMStateDescription vmstate_vfio_pci_config = {
2598 .name = "VFIOPCIDevice",
2599 .version_id = 1,
2600 .minimum_version_id = 1,
2601 .fields = (const VMStateField[]) {
2602 VMSTATE_PCI_DEVICE(pdev, VFIOPCIDevice),
2603 VMSTATE_MSIX_TEST(pdev, VFIOPCIDevice, vfio_msix_present),
2604 VMSTATE_END_OF_LIST()
2605 },
2606 .subsections = (const VMStateDescription * const []) {
2607 &vmstate_vfio_display,
2608 NULL
2609 }
2610 };
2611
vfio_pci_save_config(VFIODevice * vbasedev,QEMUFile * f,Error ** errp)2612 static int vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f, Error **errp)
2613 {
2614 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2615
2616 return vmstate_save_state_with_err(f, &vmstate_vfio_pci_config, vdev, NULL,
2617 errp);
2618 }
2619
vfio_pci_load_config(VFIODevice * vbasedev,QEMUFile * f)2620 static int vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f)
2621 {
2622 VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
2623 PCIDevice *pdev = &vdev->pdev;
2624 pcibus_t old_addr[PCI_NUM_REGIONS - 1];
2625 int bar, ret;
2626
2627 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
2628 old_addr[bar] = pdev->io_regions[bar].addr;
2629 }
2630
2631 ret = vmstate_load_state(f, &vmstate_vfio_pci_config, vdev, 1);
2632 if (ret) {
2633 return ret;
2634 }
2635
2636 vfio_pci_write_config(pdev, PCI_COMMAND,
2637 pci_get_word(pdev->config + PCI_COMMAND), 2);
2638
2639 for (bar = 0; bar < PCI_ROM_SLOT; bar++) {
2640 /*
2641 * The address may not be changed in some scenarios
2642 * (e.g. the VF driver isn't loaded in VM).
2643 */
2644 if (old_addr[bar] != pdev->io_regions[bar].addr &&
2645 vdev->bars[bar].region.size > 0 &&
2646 vdev->bars[bar].region.size < qemu_real_host_page_size()) {
2647 vfio_sub_page_bar_update_mapping(pdev, bar);
2648 }
2649 }
2650
2651 if (msi_enabled(pdev)) {
2652 vfio_msi_enable(vdev);
2653 } else if (msix_enabled(pdev)) {
2654 vfio_msix_enable(vdev);
2655 }
2656
2657 return ret;
2658 }
2659
2660 static VFIODeviceOps vfio_pci_ops = {
2661 .vfio_compute_needs_reset = vfio_pci_compute_needs_reset,
2662 .vfio_hot_reset_multi = vfio_pci_hot_reset_multi,
2663 .vfio_eoi = vfio_intx_eoi,
2664 .vfio_get_object = vfio_pci_get_object,
2665 .vfio_save_config = vfio_pci_save_config,
2666 .vfio_load_config = vfio_pci_load_config,
2667 };
2668
vfio_populate_vga(VFIOPCIDevice * vdev,Error ** errp)2669 bool vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp)
2670 {
2671 VFIODevice *vbasedev = &vdev->vbasedev;
2672 g_autofree struct vfio_region_info *reg_info = NULL;
2673 int ret;
2674
2675 ret = vfio_get_region_info(vbasedev, VFIO_PCI_VGA_REGION_INDEX, ®_info);
2676 if (ret) {
2677 error_setg_errno(errp, -ret,
2678 "failed getting region info for VGA region index %d",
2679 VFIO_PCI_VGA_REGION_INDEX);
2680 return false;
2681 }
2682
2683 if (!(reg_info->flags & VFIO_REGION_INFO_FLAG_READ) ||
2684 !(reg_info->flags & VFIO_REGION_INFO_FLAG_WRITE) ||
2685 reg_info->size < 0xbffff + 1) {
2686 error_setg(errp, "unexpected VGA info, flags 0x%lx, size 0x%lx",
2687 (unsigned long)reg_info->flags,
2688 (unsigned long)reg_info->size);
2689 return false;
2690 }
2691
2692 vdev->vga = g_new0(VFIOVGA, 1);
2693
2694 vdev->vga->fd_offset = reg_info->offset;
2695 vdev->vga->fd = vdev->vbasedev.fd;
2696
2697 vdev->vga->region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE;
2698 vdev->vga->region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM;
2699 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_MEM].quirks);
2700
2701 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2702 OBJECT(vdev), &vfio_vga_ops,
2703 &vdev->vga->region[QEMU_PCI_VGA_MEM],
2704 "vfio-vga-mmio@0xa0000",
2705 QEMU_PCI_VGA_MEM_SIZE);
2706
2707 vdev->vga->region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE;
2708 vdev->vga->region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO;
2709 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].quirks);
2710
2711 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2712 OBJECT(vdev), &vfio_vga_ops,
2713 &vdev->vga->region[QEMU_PCI_VGA_IO_LO],
2714 "vfio-vga-io@0x3b0",
2715 QEMU_PCI_VGA_IO_LO_SIZE);
2716
2717 vdev->vga->region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE;
2718 vdev->vga->region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI;
2719 QLIST_INIT(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].quirks);
2720
2721 memory_region_init_io(&vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem,
2722 OBJECT(vdev), &vfio_vga_ops,
2723 &vdev->vga->region[QEMU_PCI_VGA_IO_HI],
2724 "vfio-vga-io@0x3c0",
2725 QEMU_PCI_VGA_IO_HI_SIZE);
2726
2727 pci_register_vga(&vdev->pdev, &vdev->vga->region[QEMU_PCI_VGA_MEM].mem,
2728 &vdev->vga->region[QEMU_PCI_VGA_IO_LO].mem,
2729 &vdev->vga->region[QEMU_PCI_VGA_IO_HI].mem);
2730
2731 return true;
2732 }
2733
vfio_populate_device(VFIOPCIDevice * vdev,Error ** errp)2734 static bool vfio_populate_device(VFIOPCIDevice *vdev, Error **errp)
2735 {
2736 VFIODevice *vbasedev = &vdev->vbasedev;
2737 g_autofree struct vfio_region_info *reg_info = NULL;
2738 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
2739 int i, ret = -1;
2740
2741 /* Sanity check device */
2742 if (!(vbasedev->flags & VFIO_DEVICE_FLAGS_PCI)) {
2743 error_setg(errp, "this isn't a PCI device");
2744 return false;
2745 }
2746
2747 if (vbasedev->num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) {
2748 error_setg(errp, "unexpected number of io regions %u",
2749 vbasedev->num_regions);
2750 return false;
2751 }
2752
2753 if (vbasedev->num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) {
2754 error_setg(errp, "unexpected number of irqs %u", vbasedev->num_irqs);
2755 return false;
2756 }
2757
2758 for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) {
2759 char *name = g_strdup_printf("%s BAR %d", vbasedev->name, i);
2760
2761 ret = vfio_region_setup(OBJECT(vdev), vbasedev,
2762 &vdev->bars[i].region, i, name);
2763 g_free(name);
2764
2765 if (ret) {
2766 error_setg_errno(errp, -ret, "failed to get region %d info", i);
2767 return false;
2768 }
2769
2770 QLIST_INIT(&vdev->bars[i].quirks);
2771 }
2772
2773 ret = vfio_get_region_info(vbasedev,
2774 VFIO_PCI_CONFIG_REGION_INDEX, ®_info);
2775 if (ret) {
2776 error_setg_errno(errp, -ret, "failed to get config info");
2777 return false;
2778 }
2779
2780 trace_vfio_populate_device_config(vdev->vbasedev.name,
2781 (unsigned long)reg_info->size,
2782 (unsigned long)reg_info->offset,
2783 (unsigned long)reg_info->flags);
2784
2785 vdev->config_size = reg_info->size;
2786 if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
2787 vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
2788 }
2789 vdev->config_offset = reg_info->offset;
2790
2791 if (vdev->features & VFIO_FEATURE_ENABLE_VGA) {
2792 if (!vfio_populate_vga(vdev, errp)) {
2793 error_append_hint(errp, "device does not support "
2794 "requested feature x-vga\n");
2795 return false;
2796 }
2797 }
2798
2799 irq_info.index = VFIO_PCI_ERR_IRQ_INDEX;
2800
2801 ret = ioctl(vdev->vbasedev.fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
2802 if (ret) {
2803 /* This can fail for an old kernel or legacy PCI dev */
2804 trace_vfio_populate_device_get_irq_info_failure(strerror(errno));
2805 } else if (irq_info.count == 1) {
2806 vdev->pci_aer = true;
2807 } else {
2808 warn_report(VFIO_MSG_PREFIX
2809 "Could not enable error recovery for the device",
2810 vbasedev->name);
2811 }
2812
2813 return true;
2814 }
2815
vfio_pci_put_device(VFIOPCIDevice * vdev)2816 static void vfio_pci_put_device(VFIOPCIDevice *vdev)
2817 {
2818 vfio_detach_device(&vdev->vbasedev);
2819
2820 g_free(vdev->vbasedev.name);
2821 g_free(vdev->msix);
2822 }
2823
vfio_err_notifier_handler(void * opaque)2824 static void vfio_err_notifier_handler(void *opaque)
2825 {
2826 VFIOPCIDevice *vdev = opaque;
2827
2828 if (!event_notifier_test_and_clear(&vdev->err_notifier)) {
2829 return;
2830 }
2831
2832 /*
2833 * TBD. Retrieve the error details and decide what action
2834 * needs to be taken. One of the actions could be to pass
2835 * the error to the guest and have the guest driver recover
2836 * from the error. This requires that PCIe capabilities be
2837 * exposed to the guest. For now, we just terminate the
2838 * guest to contain the error.
2839 */
2840
2841 error_report("%s(%s) Unrecoverable error detected. Please collect any data possible and then kill the guest", __func__, vdev->vbasedev.name);
2842
2843 vm_stop(RUN_STATE_INTERNAL_ERROR);
2844 }
2845
2846 /*
2847 * Registers error notifier for devices supporting error recovery.
2848 * If we encounter a failure in this function, we report an error
2849 * and continue after disabling error recovery support for the
2850 * device.
2851 */
vfio_register_err_notifier(VFIOPCIDevice * vdev)2852 static void vfio_register_err_notifier(VFIOPCIDevice *vdev)
2853 {
2854 Error *err = NULL;
2855 int32_t fd;
2856
2857 if (!vdev->pci_aer) {
2858 return;
2859 }
2860
2861 if (event_notifier_init(&vdev->err_notifier, 0)) {
2862 error_report("vfio: Unable to init event notifier for error detection");
2863 vdev->pci_aer = false;
2864 return;
2865 }
2866
2867 fd = event_notifier_get_fd(&vdev->err_notifier);
2868 qemu_set_fd_handler(fd, vfio_err_notifier_handler, NULL, vdev);
2869
2870 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_ERR_IRQ_INDEX, 0,
2871 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
2872 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2873 qemu_set_fd_handler(fd, NULL, NULL, vdev);
2874 event_notifier_cleanup(&vdev->err_notifier);
2875 vdev->pci_aer = false;
2876 }
2877 }
2878
vfio_unregister_err_notifier(VFIOPCIDevice * vdev)2879 static void vfio_unregister_err_notifier(VFIOPCIDevice *vdev)
2880 {
2881 Error *err = NULL;
2882
2883 if (!vdev->pci_aer) {
2884 return;
2885 }
2886
2887 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_ERR_IRQ_INDEX, 0,
2888 VFIO_IRQ_SET_ACTION_TRIGGER, -1, &err)) {
2889 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2890 }
2891 qemu_set_fd_handler(event_notifier_get_fd(&vdev->err_notifier),
2892 NULL, NULL, vdev);
2893 event_notifier_cleanup(&vdev->err_notifier);
2894 }
2895
vfio_req_notifier_handler(void * opaque)2896 static void vfio_req_notifier_handler(void *opaque)
2897 {
2898 VFIOPCIDevice *vdev = opaque;
2899 Error *err = NULL;
2900
2901 if (!event_notifier_test_and_clear(&vdev->req_notifier)) {
2902 return;
2903 }
2904
2905 qdev_unplug(DEVICE(vdev), &err);
2906 if (err) {
2907 warn_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2908 }
2909 }
2910
vfio_register_req_notifier(VFIOPCIDevice * vdev)2911 static void vfio_register_req_notifier(VFIOPCIDevice *vdev)
2912 {
2913 struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info),
2914 .index = VFIO_PCI_REQ_IRQ_INDEX };
2915 Error *err = NULL;
2916 int32_t fd;
2917
2918 if (!(vdev->features & VFIO_FEATURE_ENABLE_REQ)) {
2919 return;
2920 }
2921
2922 if (ioctl(vdev->vbasedev.fd,
2923 VFIO_DEVICE_GET_IRQ_INFO, &irq_info) < 0 || irq_info.count < 1) {
2924 return;
2925 }
2926
2927 if (event_notifier_init(&vdev->req_notifier, 0)) {
2928 error_report("vfio: Unable to init event notifier for device request");
2929 return;
2930 }
2931
2932 fd = event_notifier_get_fd(&vdev->req_notifier);
2933 qemu_set_fd_handler(fd, vfio_req_notifier_handler, NULL, vdev);
2934
2935 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_REQ_IRQ_INDEX, 0,
2936 VFIO_IRQ_SET_ACTION_TRIGGER, fd, &err)) {
2937 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2938 qemu_set_fd_handler(fd, NULL, NULL, vdev);
2939 event_notifier_cleanup(&vdev->req_notifier);
2940 } else {
2941 vdev->req_enabled = true;
2942 }
2943 }
2944
vfio_unregister_req_notifier(VFIOPCIDevice * vdev)2945 static void vfio_unregister_req_notifier(VFIOPCIDevice *vdev)
2946 {
2947 Error *err = NULL;
2948
2949 if (!vdev->req_enabled) {
2950 return;
2951 }
2952
2953 if (!vfio_set_irq_signaling(&vdev->vbasedev, VFIO_PCI_REQ_IRQ_INDEX, 0,
2954 VFIO_IRQ_SET_ACTION_TRIGGER, -1, &err)) {
2955 error_reportf_err(err, VFIO_MSG_PREFIX, vdev->vbasedev.name);
2956 }
2957 qemu_set_fd_handler(event_notifier_get_fd(&vdev->req_notifier),
2958 NULL, NULL, vdev);
2959 event_notifier_cleanup(&vdev->req_notifier);
2960
2961 vdev->req_enabled = false;
2962 }
2963
vfio_realize(PCIDevice * pdev,Error ** errp)2964 static void vfio_realize(PCIDevice *pdev, Error **errp)
2965 {
2966 ERRP_GUARD();
2967 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
2968 VFIODevice *vbasedev = &vdev->vbasedev;
2969 int i, ret;
2970 char uuid[UUID_STR_LEN];
2971 g_autofree char *name = NULL;
2972
2973 if (vbasedev->fd < 0 && !vbasedev->sysfsdev) {
2974 if (!(~vdev->host.domain || ~vdev->host.bus ||
2975 ~vdev->host.slot || ~vdev->host.function)) {
2976 error_setg(errp, "No provided host device");
2977 error_append_hint(errp, "Use -device vfio-pci,host=DDDD:BB:DD.F "
2978 #ifdef CONFIG_IOMMUFD
2979 "or -device vfio-pci,fd=DEVICE_FD "
2980 #endif
2981 "or -device vfio-pci,sysfsdev=PATH_TO_DEVICE\n");
2982 return;
2983 }
2984 vbasedev->sysfsdev =
2985 g_strdup_printf("/sys/bus/pci/devices/%04x:%02x:%02x.%01x",
2986 vdev->host.domain, vdev->host.bus,
2987 vdev->host.slot, vdev->host.function);
2988 }
2989
2990 if (!vfio_device_get_name(vbasedev, errp)) {
2991 return;
2992 }
2993
2994 /*
2995 * Mediated devices *might* operate compatibly with discarding of RAM, but
2996 * we cannot know for certain, it depends on whether the mdev vendor driver
2997 * stays in sync with the active working set of the guest driver. Prevent
2998 * the x-balloon-allowed option unless this is minimally an mdev device.
2999 */
3000 vbasedev->mdev = vfio_device_is_mdev(vbasedev);
3001
3002 trace_vfio_mdev(vbasedev->name, vbasedev->mdev);
3003
3004 if (vbasedev->ram_block_discard_allowed && !vbasedev->mdev) {
3005 error_setg(errp, "x-balloon-allowed only potentially compatible "
3006 "with mdev devices");
3007 goto error;
3008 }
3009
3010 if (!qemu_uuid_is_null(&vdev->vf_token)) {
3011 qemu_uuid_unparse(&vdev->vf_token, uuid);
3012 name = g_strdup_printf("%s vf_token=%s", vbasedev->name, uuid);
3013 } else {
3014 name = g_strdup(vbasedev->name);
3015 }
3016
3017 if (!vfio_attach_device(name, vbasedev,
3018 pci_device_iommu_address_space(pdev), errp)) {
3019 goto error;
3020 }
3021
3022 if (!vfio_populate_device(vdev, errp)) {
3023 goto error;
3024 }
3025
3026 /* Get a copy of config space */
3027 ret = pread(vbasedev->fd, vdev->pdev.config,
3028 MIN(pci_config_size(&vdev->pdev), vdev->config_size),
3029 vdev->config_offset);
3030 if (ret < (int)MIN(pci_config_size(&vdev->pdev), vdev->config_size)) {
3031 ret = ret < 0 ? -errno : -EFAULT;
3032 error_setg_errno(errp, -ret, "failed to read device config space");
3033 goto error;
3034 }
3035
3036 /* vfio emulates a lot for us, but some bits need extra love */
3037 vdev->emulated_config_bits = g_malloc0(vdev->config_size);
3038
3039 /* QEMU can choose to expose the ROM or not */
3040 memset(vdev->emulated_config_bits + PCI_ROM_ADDRESS, 0xff, 4);
3041 /* QEMU can also add or extend BARs */
3042 memset(vdev->emulated_config_bits + PCI_BASE_ADDRESS_0, 0xff, 6 * 4);
3043
3044 /*
3045 * The PCI spec reserves vendor ID 0xffff as an invalid value. The
3046 * device ID is managed by the vendor and need only be a 16-bit value.
3047 * Allow any 16-bit value for subsystem so they can be hidden or changed.
3048 */
3049 if (vdev->vendor_id != PCI_ANY_ID) {
3050 if (vdev->vendor_id >= 0xffff) {
3051 error_setg(errp, "invalid PCI vendor ID provided");
3052 goto error;
3053 }
3054 vfio_add_emulated_word(vdev, PCI_VENDOR_ID, vdev->vendor_id, ~0);
3055 trace_vfio_pci_emulated_vendor_id(vbasedev->name, vdev->vendor_id);
3056 } else {
3057 vdev->vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
3058 }
3059
3060 if (vdev->device_id != PCI_ANY_ID) {
3061 if (vdev->device_id > 0xffff) {
3062 error_setg(errp, "invalid PCI device ID provided");
3063 goto error;
3064 }
3065 vfio_add_emulated_word(vdev, PCI_DEVICE_ID, vdev->device_id, ~0);
3066 trace_vfio_pci_emulated_device_id(vbasedev->name, vdev->device_id);
3067 } else {
3068 vdev->device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
3069 }
3070
3071 if (vdev->sub_vendor_id != PCI_ANY_ID) {
3072 if (vdev->sub_vendor_id > 0xffff) {
3073 error_setg(errp, "invalid PCI subsystem vendor ID provided");
3074 goto error;
3075 }
3076 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_VENDOR_ID,
3077 vdev->sub_vendor_id, ~0);
3078 trace_vfio_pci_emulated_sub_vendor_id(vbasedev->name,
3079 vdev->sub_vendor_id);
3080 }
3081
3082 if (vdev->sub_device_id != PCI_ANY_ID) {
3083 if (vdev->sub_device_id > 0xffff) {
3084 error_setg(errp, "invalid PCI subsystem device ID provided");
3085 goto error;
3086 }
3087 vfio_add_emulated_word(vdev, PCI_SUBSYSTEM_ID, vdev->sub_device_id, ~0);
3088 trace_vfio_pci_emulated_sub_device_id(vbasedev->name,
3089 vdev->sub_device_id);
3090 }
3091
3092 /* QEMU can change multi-function devices to single function, or reverse */
3093 vdev->emulated_config_bits[PCI_HEADER_TYPE] =
3094 PCI_HEADER_TYPE_MULTI_FUNCTION;
3095
3096 /* Restore or clear multifunction, this is always controlled by QEMU */
3097 if (vdev->pdev.cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
3098 vdev->pdev.config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
3099 } else {
3100 vdev->pdev.config[PCI_HEADER_TYPE] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
3101 }
3102
3103 /*
3104 * Clear host resource mapping info. If we choose not to register a
3105 * BAR, such as might be the case with the option ROM, we can get
3106 * confusing, unwritable, residual addresses from the host here.
3107 */
3108 memset(&vdev->pdev.config[PCI_BASE_ADDRESS_0], 0, 24);
3109 memset(&vdev->pdev.config[PCI_ROM_ADDRESS], 0, 4);
3110
3111 vfio_pci_size_rom(vdev);
3112
3113 vfio_bars_prepare(vdev);
3114
3115 if (!vfio_msix_early_setup(vdev, errp)) {
3116 goto error;
3117 }
3118
3119 vfio_bars_register(vdev);
3120
3121 if (!vbasedev->mdev &&
3122 !pci_device_set_iommu_device(pdev, vbasedev->hiod, errp)) {
3123 error_prepend(errp, "Failed to set vIOMMU: ");
3124 goto out_teardown;
3125 }
3126
3127 if (!vfio_add_capabilities(vdev, errp)) {
3128 goto out_unset_idev;
3129 }
3130
3131 if (!vfio_config_quirk_setup(vdev, errp)) {
3132 goto out_unset_idev;
3133 }
3134
3135 if (vdev->vga) {
3136 vfio_vga_quirk_setup(vdev);
3137 }
3138
3139 for (i = 0; i < PCI_ROM_SLOT; i++) {
3140 vfio_bar_quirk_setup(vdev, i);
3141 }
3142
3143 /* QEMU emulates all of MSI & MSIX */
3144 if (pdev->cap_present & QEMU_PCI_CAP_MSIX) {
3145 memset(vdev->emulated_config_bits + pdev->msix_cap, 0xff,
3146 MSIX_CAP_LENGTH);
3147 }
3148
3149 if (pdev->cap_present & QEMU_PCI_CAP_MSI) {
3150 memset(vdev->emulated_config_bits + pdev->msi_cap, 0xff,
3151 vdev->msi_cap_size);
3152 }
3153
3154 if (vfio_pci_read_config(&vdev->pdev, PCI_INTERRUPT_PIN, 1)) {
3155 vdev->intx.mmap_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL,
3156 vfio_intx_mmap_enable, vdev);
3157 pci_device_set_intx_routing_notifier(&vdev->pdev,
3158 vfio_intx_routing_notifier);
3159 vdev->irqchip_change_notifier.notify = vfio_irqchip_change;
3160 kvm_irqchip_add_change_notifier(&vdev->irqchip_change_notifier);
3161 if (!vfio_intx_enable(vdev, errp)) {
3162 goto out_deregister;
3163 }
3164 }
3165
3166 if (vdev->display != ON_OFF_AUTO_OFF) {
3167 if (!vfio_display_probe(vdev, errp)) {
3168 goto out_deregister;
3169 }
3170 }
3171 if (vdev->enable_ramfb && vdev->dpy == NULL) {
3172 error_setg(errp, "ramfb=on requires display=on");
3173 goto out_deregister;
3174 }
3175 if (vdev->display_xres || vdev->display_yres) {
3176 if (vdev->dpy == NULL) {
3177 error_setg(errp, "xres and yres properties require display=on");
3178 goto out_deregister;
3179 }
3180 if (vdev->dpy->edid_regs == NULL) {
3181 error_setg(errp, "xres and yres properties need edid support");
3182 goto out_deregister;
3183 }
3184 }
3185
3186 if (vdev->ramfb_migrate == ON_OFF_AUTO_ON && !vdev->enable_ramfb) {
3187 warn_report("x-ramfb-migrate=on but ramfb=off. "
3188 "Forcing x-ramfb-migrate to off.");
3189 vdev->ramfb_migrate = ON_OFF_AUTO_OFF;
3190 }
3191 if (vbasedev->enable_migration == ON_OFF_AUTO_OFF) {
3192 if (vdev->ramfb_migrate == ON_OFF_AUTO_AUTO) {
3193 vdev->ramfb_migrate = ON_OFF_AUTO_OFF;
3194 } else if (vdev->ramfb_migrate == ON_OFF_AUTO_ON) {
3195 error_setg(errp, "x-ramfb-migrate requires enable-migration");
3196 goto out_deregister;
3197 }
3198 }
3199
3200 if (!pdev->failover_pair_id) {
3201 if (!vfio_migration_realize(vbasedev, errp)) {
3202 goto out_deregister;
3203 }
3204 }
3205
3206 vfio_register_err_notifier(vdev);
3207 vfio_register_req_notifier(vdev);
3208 vfio_setup_resetfn_quirk(vdev);
3209
3210 return;
3211
3212 out_deregister:
3213 if (vdev->interrupt == VFIO_INT_INTx) {
3214 vfio_intx_disable(vdev);
3215 }
3216 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3217 if (vdev->irqchip_change_notifier.notify) {
3218 kvm_irqchip_remove_change_notifier(&vdev->irqchip_change_notifier);
3219 }
3220 if (vdev->intx.mmap_timer) {
3221 timer_free(vdev->intx.mmap_timer);
3222 }
3223 out_unset_idev:
3224 if (!vbasedev->mdev) {
3225 pci_device_unset_iommu_device(pdev);
3226 }
3227 out_teardown:
3228 vfio_teardown_msi(vdev);
3229 vfio_bars_exit(vdev);
3230 error:
3231 error_prepend(errp, VFIO_MSG_PREFIX, vbasedev->name);
3232 }
3233
vfio_instance_finalize(Object * obj)3234 static void vfio_instance_finalize(Object *obj)
3235 {
3236 VFIOPCIDevice *vdev = VFIO_PCI(obj);
3237
3238 vfio_display_finalize(vdev);
3239 vfio_bars_finalize(vdev);
3240 g_free(vdev->emulated_config_bits);
3241 g_free(vdev->rom);
3242 /*
3243 * XXX Leaking igd_opregion is not an oversight, we can't remove the
3244 * fw_cfg entry therefore leaking this allocation seems like the safest
3245 * option.
3246 *
3247 * g_free(vdev->igd_opregion);
3248 */
3249 vfio_pci_put_device(vdev);
3250 }
3251
vfio_exitfn(PCIDevice * pdev)3252 static void vfio_exitfn(PCIDevice *pdev)
3253 {
3254 VFIOPCIDevice *vdev = VFIO_PCI(pdev);
3255 VFIODevice *vbasedev = &vdev->vbasedev;
3256
3257 vfio_unregister_req_notifier(vdev);
3258 vfio_unregister_err_notifier(vdev);
3259 pci_device_set_intx_routing_notifier(&vdev->pdev, NULL);
3260 if (vdev->irqchip_change_notifier.notify) {
3261 kvm_irqchip_remove_change_notifier(&vdev->irqchip_change_notifier);
3262 }
3263 vfio_disable_interrupts(vdev);
3264 if (vdev->intx.mmap_timer) {
3265 timer_free(vdev->intx.mmap_timer);
3266 }
3267 vfio_teardown_msi(vdev);
3268 vfio_pci_disable_rp_atomics(vdev);
3269 vfio_bars_exit(vdev);
3270 vfio_migration_exit(vbasedev);
3271 if (!vbasedev->mdev) {
3272 pci_device_unset_iommu_device(pdev);
3273 }
3274 }
3275
vfio_pci_reset(DeviceState * dev)3276 static void vfio_pci_reset(DeviceState *dev)
3277 {
3278 VFIOPCIDevice *vdev = VFIO_PCI(dev);
3279
3280 trace_vfio_pci_reset(vdev->vbasedev.name);
3281
3282 vfio_pci_pre_reset(vdev);
3283
3284 if (vdev->display != ON_OFF_AUTO_OFF) {
3285 vfio_display_reset(vdev);
3286 }
3287
3288 if (vdev->resetfn && !vdev->resetfn(vdev)) {
3289 goto post_reset;
3290 }
3291
3292 if (vdev->vbasedev.reset_works &&
3293 (vdev->has_flr || !vdev->has_pm_reset) &&
3294 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3295 trace_vfio_pci_reset_flr(vdev->vbasedev.name);
3296 goto post_reset;
3297 }
3298
3299 /* See if we can do our own bus reset */
3300 if (!vfio_pci_hot_reset_one(vdev)) {
3301 goto post_reset;
3302 }
3303
3304 /* If nothing else works and the device supports PM reset, use it */
3305 if (vdev->vbasedev.reset_works && vdev->has_pm_reset &&
3306 !ioctl(vdev->vbasedev.fd, VFIO_DEVICE_RESET)) {
3307 trace_vfio_pci_reset_pm(vdev->vbasedev.name);
3308 goto post_reset;
3309 }
3310
3311 post_reset:
3312 vfio_pci_post_reset(vdev);
3313 }
3314
vfio_instance_init(Object * obj)3315 static void vfio_instance_init(Object *obj)
3316 {
3317 PCIDevice *pci_dev = PCI_DEVICE(obj);
3318 VFIOPCIDevice *vdev = VFIO_PCI(obj);
3319 VFIODevice *vbasedev = &vdev->vbasedev;
3320
3321 device_add_bootindex_property(obj, &vdev->bootindex,
3322 "bootindex", NULL,
3323 &pci_dev->qdev);
3324 vdev->host.domain = ~0U;
3325 vdev->host.bus = ~0U;
3326 vdev->host.slot = ~0U;
3327 vdev->host.function = ~0U;
3328
3329 vfio_device_init(vbasedev, VFIO_DEVICE_TYPE_PCI, &vfio_pci_ops,
3330 DEVICE(vdev), false);
3331
3332 vdev->nv_gpudirect_clique = 0xFF;
3333
3334 /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command
3335 * line, therefore, no need to wait to realize like other devices */
3336 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
3337 }
3338
3339 static PropertyInfo vfio_pci_migration_multifd_transfer_prop;
3340
3341 static const Property vfio_pci_dev_properties[] = {
3342 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice, host),
3343 DEFINE_PROP_UUID_NODEFAULT("vf-token", VFIOPCIDevice, vf_token),
3344 DEFINE_PROP_STRING("sysfsdev", VFIOPCIDevice, vbasedev.sysfsdev),
3345 DEFINE_PROP_ON_OFF_AUTO("x-pre-copy-dirty-page-tracking", VFIOPCIDevice,
3346 vbasedev.pre_copy_dirty_page_tracking,
3347 ON_OFF_AUTO_ON),
3348 DEFINE_PROP_ON_OFF_AUTO("x-device-dirty-page-tracking", VFIOPCIDevice,
3349 vbasedev.device_dirty_page_tracking,
3350 ON_OFF_AUTO_ON),
3351 DEFINE_PROP_ON_OFF_AUTO("display", VFIOPCIDevice,
3352 display, ON_OFF_AUTO_OFF),
3353 DEFINE_PROP_UINT32("xres", VFIOPCIDevice, display_xres, 0),
3354 DEFINE_PROP_UINT32("yres", VFIOPCIDevice, display_yres, 0),
3355 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice,
3356 intx.mmap_timeout, 1100),
3357 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice, features,
3358 VFIO_FEATURE_ENABLE_VGA_BIT, false),
3359 DEFINE_PROP_BIT("x-req", VFIOPCIDevice, features,
3360 VFIO_FEATURE_ENABLE_REQ_BIT, true),
3361 DEFINE_PROP_BIT("x-igd-opregion", VFIOPCIDevice, features,
3362 VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT, false),
3363 DEFINE_PROP_BIT("x-igd-lpc", VFIOPCIDevice, features,
3364 VFIO_FEATURE_ENABLE_IGD_LPC_BIT, false),
3365 DEFINE_PROP_ON_OFF_AUTO("x-igd-legacy-mode", VFIOPCIDevice,
3366 igd_legacy_mode, ON_OFF_AUTO_AUTO),
3367 DEFINE_PROP_ON_OFF_AUTO("enable-migration", VFIOPCIDevice,
3368 vbasedev.enable_migration, ON_OFF_AUTO_AUTO),
3369 DEFINE_PROP("x-migration-multifd-transfer", VFIOPCIDevice,
3370 vbasedev.migration_multifd_transfer,
3371 vfio_pci_migration_multifd_transfer_prop, OnOffAuto,
3372 .set_default = true, .defval.i = ON_OFF_AUTO_AUTO),
3373 DEFINE_PROP_BOOL("migration-events", VFIOPCIDevice,
3374 vbasedev.migration_events, false),
3375 DEFINE_PROP_BOOL("x-no-mmap", VFIOPCIDevice, vbasedev.no_mmap, false),
3376 DEFINE_PROP_BOOL("x-balloon-allowed", VFIOPCIDevice,
3377 vbasedev.ram_block_discard_allowed, false),
3378 DEFINE_PROP_BOOL("x-no-kvm-intx", VFIOPCIDevice, no_kvm_intx, false),
3379 DEFINE_PROP_BOOL("x-no-kvm-msi", VFIOPCIDevice, no_kvm_msi, false),
3380 DEFINE_PROP_BOOL("x-no-kvm-msix", VFIOPCIDevice, no_kvm_msix, false),
3381 DEFINE_PROP_BOOL("x-no-geforce-quirks", VFIOPCIDevice,
3382 no_geforce_quirks, false),
3383 DEFINE_PROP_BOOL("x-no-kvm-ioeventfd", VFIOPCIDevice, no_kvm_ioeventfd,
3384 false),
3385 DEFINE_PROP_BOOL("x-no-vfio-ioeventfd", VFIOPCIDevice, no_vfio_ioeventfd,
3386 false),
3387 DEFINE_PROP_UINT32("x-pci-vendor-id", VFIOPCIDevice, vendor_id, PCI_ANY_ID),
3388 DEFINE_PROP_UINT32("x-pci-device-id", VFIOPCIDevice, device_id, PCI_ANY_ID),
3389 DEFINE_PROP_UINT32("x-pci-sub-vendor-id", VFIOPCIDevice,
3390 sub_vendor_id, PCI_ANY_ID),
3391 DEFINE_PROP_UINT32("x-pci-sub-device-id", VFIOPCIDevice,
3392 sub_device_id, PCI_ANY_ID),
3393 DEFINE_PROP_UINT32("x-igd-gms", VFIOPCIDevice, igd_gms, 0),
3394 DEFINE_PROP_UNSIGNED_NODEFAULT("x-nv-gpudirect-clique", VFIOPCIDevice,
3395 nv_gpudirect_clique,
3396 qdev_prop_nv_gpudirect_clique, uint8_t),
3397 DEFINE_PROP_OFF_AUTO_PCIBAR("x-msix-relocation", VFIOPCIDevice, msix_relo,
3398 OFF_AUTO_PCIBAR_OFF),
3399 #ifdef CONFIG_IOMMUFD
3400 DEFINE_PROP_LINK("iommufd", VFIOPCIDevice, vbasedev.iommufd,
3401 TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *),
3402 #endif
3403 DEFINE_PROP_BOOL("skip-vsc-check", VFIOPCIDevice, skip_vsc_check, true),
3404 };
3405
3406 #ifdef CONFIG_IOMMUFD
vfio_pci_set_fd(Object * obj,const char * str,Error ** errp)3407 static void vfio_pci_set_fd(Object *obj, const char *str, Error **errp)
3408 {
3409 vfio_device_set_fd(&VFIO_PCI(obj)->vbasedev, str, errp);
3410 }
3411 #endif
3412
vfio_pci_dev_class_init(ObjectClass * klass,void * data)3413 static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
3414 {
3415 DeviceClass *dc = DEVICE_CLASS(klass);
3416 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(klass);
3417
3418 device_class_set_legacy_reset(dc, vfio_pci_reset);
3419 device_class_set_props(dc, vfio_pci_dev_properties);
3420 #ifdef CONFIG_IOMMUFD
3421 object_class_property_add_str(klass, "fd", NULL, vfio_pci_set_fd);
3422 #endif
3423 dc->desc = "VFIO-based PCI device assignment";
3424 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
3425 pdc->realize = vfio_realize;
3426 pdc->exit = vfio_exitfn;
3427 pdc->config_read = vfio_pci_read_config;
3428 pdc->config_write = vfio_pci_write_config;
3429
3430 object_class_property_set_description(klass, /* 1.3 */
3431 "host",
3432 "Host PCI address [domain:]<bus:slot.function> of assigned device");
3433 object_class_property_set_description(klass, /* 1.3 */
3434 "x-intx-mmap-timeout-ms",
3435 "When EOI is not provided by KVM/QEMU, wait time "
3436 "(milliseconds) to re-enable device direct access "
3437 "after INTx (DEBUG)");
3438 object_class_property_set_description(klass, /* 1.5 */
3439 "x-vga",
3440 "Expose VGA address spaces for device");
3441 object_class_property_set_description(klass, /* 2.3 */
3442 "x-req",
3443 "Disable device request notification support (DEBUG)");
3444 object_class_property_set_description(klass, /* 2.4 and 2.5 */
3445 "x-no-mmap",
3446 "Disable MMAP for device. Allows to trace MMIO "
3447 "accesses (DEBUG)");
3448 object_class_property_set_description(klass, /* 2.5 */
3449 "x-no-kvm-intx",
3450 "Disable direct VFIO->KVM INTx injection. Allows to "
3451 "trace INTx interrupts (DEBUG)");
3452 object_class_property_set_description(klass, /* 2.5 */
3453 "x-no-kvm-msi",
3454 "Disable direct VFIO->KVM MSI injection. Allows to "
3455 "trace MSI interrupts (DEBUG)");
3456 object_class_property_set_description(klass, /* 2.5 */
3457 "x-no-kvm-msix",
3458 "Disable direct VFIO->KVM MSIx injection. Allows to "
3459 "trace MSIx interrupts (DEBUG)");
3460 object_class_property_set_description(klass, /* 2.5 */
3461 "x-pci-vendor-id",
3462 "Override PCI Vendor ID with provided value (DEBUG)");
3463 object_class_property_set_description(klass, /* 2.5 */
3464 "x-pci-device-id",
3465 "Override PCI device ID with provided value (DEBUG)");
3466 object_class_property_set_description(klass, /* 2.5 */
3467 "x-pci-sub-vendor-id",
3468 "Override PCI Subsystem Vendor ID with provided value "
3469 "(DEBUG)");
3470 object_class_property_set_description(klass, /* 2.5 */
3471 "x-pci-sub-device-id",
3472 "Override PCI Subsystem Device ID with provided value "
3473 "(DEBUG)");
3474 object_class_property_set_description(klass, /* 2.6 */
3475 "sysfsdev",
3476 "Host sysfs path of assigned device");
3477 object_class_property_set_description(klass, /* 2.7 */
3478 "x-igd-opregion",
3479 "Expose host IGD OpRegion to guest");
3480 object_class_property_set_description(klass, /* 2.7 (See c4c45e943e51) */
3481 "x-igd-gms",
3482 "Override IGD data stolen memory size (32MiB units)");
3483 object_class_property_set_description(klass, /* 2.11 */
3484 "x-nv-gpudirect-clique",
3485 "Add NVIDIA GPUDirect capability indicating P2P DMA "
3486 "clique for device [0-15]");
3487 object_class_property_set_description(klass, /* 2.12 */
3488 "x-no-geforce-quirks",
3489 "Disable GeForce quirks (for NVIDIA Quadro/GRID/Tesla). "
3490 "Improves performance");
3491 object_class_property_set_description(klass, /* 2.12 */
3492 "display",
3493 "Enable display support for device, ex. vGPU");
3494 object_class_property_set_description(klass, /* 2.12 */
3495 "x-msix-relocation",
3496 "Specify MSI-X MMIO relocation to the end of specified "
3497 "existing BAR or new BAR to avoid virtualization overhead "
3498 "due to adjacent device registers");
3499 object_class_property_set_description(klass, /* 3.0 */
3500 "x-no-kvm-ioeventfd",
3501 "Disable registration of ioeventfds with KVM (DEBUG)");
3502 object_class_property_set_description(klass, /* 3.0 */
3503 "x-no-vfio-ioeventfd",
3504 "Disable linking of KVM ioeventfds to VFIO ioeventfds "
3505 "(DEBUG)");
3506 object_class_property_set_description(klass, /* 3.1 */
3507 "x-balloon-allowed",
3508 "Override allowing ballooning with device (DEBUG, DANGER)");
3509 object_class_property_set_description(klass, /* 3.2 */
3510 "xres",
3511 "Set X display resolution the vGPU should use");
3512 object_class_property_set_description(klass, /* 3.2 */
3513 "yres",
3514 "Set Y display resolution the vGPU should use");
3515 object_class_property_set_description(klass, /* 5.2 */
3516 "x-pre-copy-dirty-page-tracking",
3517 "Disable dirty pages tracking during iterative phase "
3518 "(DEBUG)");
3519 object_class_property_set_description(klass, /* 5.2, 8.0 non-experimetal */
3520 "enable-migration",
3521 "Enale device migration. Also requires a host VFIO PCI "
3522 "variant or mdev driver with migration support enabled");
3523 object_class_property_set_description(klass, /* 8.1 */
3524 "vf-token",
3525 "Specify UUID VF token. Required for VF when PF is owned "
3526 "by another VFIO driver");
3527 #ifdef CONFIG_IOMMUFD
3528 object_class_property_set_description(klass, /* 9.0 */
3529 "iommufd",
3530 "Set host IOMMUFD backend device");
3531 #endif
3532 object_class_property_set_description(klass, /* 9.1 */
3533 "x-device-dirty-page-tracking",
3534 "Disable device dirty page tracking and use "
3535 "container-based dirty page tracking");
3536 object_class_property_set_description(klass, /* 9.1 */
3537 "migration-events",
3538 "Emit VFIO migration QAPI event when a VFIO device "
3539 "changes its migration state. For management applications");
3540 object_class_property_set_description(klass, /* 9.1 */
3541 "skip-vsc-check",
3542 "Skip config space check for Vendor Specific Capability. "
3543 "Setting to false will enforce strict checking of VSC content "
3544 "(DEBUG)");
3545 object_class_property_set_description(klass, /* 10.0 */
3546 "x-migration-multifd-transfer",
3547 "Transfer this device state via "
3548 "multifd channels when live migrating it");
3549 }
3550
3551 static const TypeInfo vfio_pci_dev_info = {
3552 .name = TYPE_VFIO_PCI,
3553 .parent = TYPE_PCI_DEVICE,
3554 .instance_size = sizeof(VFIOPCIDevice),
3555 .class_init = vfio_pci_dev_class_init,
3556 .instance_init = vfio_instance_init,
3557 .instance_finalize = vfio_instance_finalize,
3558 .interfaces = (InterfaceInfo[]) {
3559 { INTERFACE_PCIE_DEVICE },
3560 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
3561 { }
3562 },
3563 };
3564
3565 static const Property vfio_pci_dev_nohotplug_properties[] = {
3566 DEFINE_PROP_BOOL("ramfb", VFIOPCIDevice, enable_ramfb, false),
3567 DEFINE_PROP_ON_OFF_AUTO("x-ramfb-migrate", VFIOPCIDevice, ramfb_migrate,
3568 ON_OFF_AUTO_AUTO),
3569 };
3570
vfio_pci_nohotplug_dev_class_init(ObjectClass * klass,void * data)3571 static void vfio_pci_nohotplug_dev_class_init(ObjectClass *klass, void *data)
3572 {
3573 DeviceClass *dc = DEVICE_CLASS(klass);
3574
3575 device_class_set_props(dc, vfio_pci_dev_nohotplug_properties);
3576 dc->hotpluggable = false;
3577
3578 object_class_property_set_description(klass, /* 3.1 */
3579 "ramfb",
3580 "Enable ramfb to provide pre-boot graphics for devices "
3581 "enabling display option");
3582 object_class_property_set_description(klass, /* 8.2 */
3583 "x-ramfb-migrate",
3584 "Override default migration support for ramfb support "
3585 "(DEBUG)");
3586 }
3587
3588 static const TypeInfo vfio_pci_nohotplug_dev_info = {
3589 .name = TYPE_VFIO_PCI_NOHOTPLUG,
3590 .parent = TYPE_VFIO_PCI,
3591 .instance_size = sizeof(VFIOPCIDevice),
3592 .class_init = vfio_pci_nohotplug_dev_class_init,
3593 };
3594
register_vfio_pci_dev_type(void)3595 static void register_vfio_pci_dev_type(void)
3596 {
3597 /*
3598 * Ordinary ON_OFF_AUTO property isn't runtime-mutable, but source VM can
3599 * run for a long time before being migrated so it is desirable to have a
3600 * fallback mechanism to the old way of transferring VFIO device state if
3601 * it turns to be necessary.
3602 * The following makes this type of property have the same mutability level
3603 * as ordinary migration parameters.
3604 */
3605 vfio_pci_migration_multifd_transfer_prop = qdev_prop_on_off_auto;
3606 vfio_pci_migration_multifd_transfer_prop.realized_set_allowed = true;
3607
3608 type_register_static(&vfio_pci_dev_info);
3609 type_register_static(&vfio_pci_nohotplug_dev_info);
3610 }
3611
3612 type_init(register_vfio_pci_dev_type)
3613