1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28 #include "soc15.h"
29
30 #include "oss/osssys_4_2_0_offset.h"
31 #include "oss/osssys_4_2_0_sh_mask.h"
32
33 #include "soc15_common.h"
34 #include "vega20_ih.h"
35
36 #define MAX_REARM_RETRY 10
37
38 #define mmIH_CHICKEN_ALDEBARAN 0x18d
39 #define mmIH_CHICKEN_ALDEBARAN_BASE_IDX 0
40
41 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN 0x00ea
42 #define mmIH_RETRY_INT_CAM_CNTL_ALDEBARAN_BASE_IDX 0
43 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE__SHIFT 0x10
44 #define IH_RETRY_INT_CAM_CNTL_ALDEBARAN__ENABLE_MASK 0x00010000L
45
46 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev);
47
48 /**
49 * vega20_ih_init_register_offset - Initialize register offset for ih rings
50 *
51 * @adev: amdgpu_device pointer
52 *
53 * Initialize register offset ih rings (VEGA20).
54 */
vega20_ih_init_register_offset(struct amdgpu_device * adev)55 static void vega20_ih_init_register_offset(struct amdgpu_device *adev)
56 {
57 struct amdgpu_ih_regs *ih_regs;
58
59 if (adev->irq.ih.ring_size) {
60 ih_regs = &adev->irq.ih.ih_regs;
61 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE);
62 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI);
63 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL);
64 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR);
65 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR);
66 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR);
67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
68 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI);
69 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
70 }
71
72 if (adev->irq.ih1.ring_size) {
73 ih_regs = &adev->irq.ih1.ih_regs;
74 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING1);
75 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING1);
76 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING1);
77 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING1);
78 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING1);
79 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING1);
80 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
81 }
82
83 if (adev->irq.ih2.ring_size) {
84 ih_regs = &adev->irq.ih2.ih_regs;
85 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_RING2);
86 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_BASE_HI_RING2);
87 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_CNTL_RING2);
88 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_RING2);
89 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_RPTR_RING2);
90 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_DOORBELL_RPTR_RING2);
91 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING2;
92 }
93 }
94
95 /**
96 * vega20_ih_toggle_ring_interrupts - toggle the interrupt ring buffer
97 *
98 * @adev: amdgpu_device pointer
99 * @ih: amdgpu_ih_ring pointer
100 * @enable: true - enable the interrupts, false - disable the interrupts
101 *
102 * Toggle the interrupt ring buffer (VEGA20)
103 */
vega20_ih_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)104 static int vega20_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
105 struct amdgpu_ih_ring *ih,
106 bool enable)
107 {
108 struct amdgpu_ih_regs *ih_regs;
109 uint32_t tmp;
110
111 ih_regs = &ih->ih_regs;
112
113 tmp = RREG32(ih_regs->ih_rb_cntl);
114 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
115 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_GPU_TS_ENABLE, 1);
116
117 if (enable) {
118 /* Unset the CLEAR_OVERFLOW bit to make sure the next step
119 * is switching the bit from 0 to 1
120 */
121 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
122 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
123 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
124 return -ETIMEDOUT;
125 } else {
126 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
127 }
128
129 /* Clear RB_OVERFLOW bit */
130 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
131 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
132 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
133 return -ETIMEDOUT;
134 } else {
135 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
136 }
137
138 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
139 * can be detected.
140 */
141 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
142 }
143
144 /* enable_intr field is only valid in ring0 */
145 if (ih == &adev->irq.ih)
146 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
147 if (amdgpu_sriov_vf(adev)) {
148 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
149 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
150 return -ETIMEDOUT;
151 }
152 } else {
153 WREG32(ih_regs->ih_rb_cntl, tmp);
154 }
155
156 if (enable) {
157 ih->enabled = true;
158 } else {
159 /* set rptr, wptr to 0 */
160 WREG32(ih_regs->ih_rb_rptr, 0);
161 WREG32(ih_regs->ih_rb_wptr, 0);
162 ih->enabled = false;
163 ih->rptr = 0;
164 }
165
166 return 0;
167 }
168
169 /**
170 * vega20_ih_toggle_interrupts - Toggle all the available interrupt ring buffers
171 *
172 * @adev: amdgpu_device pointer
173 * @enable: enable or disable interrupt ring buffers
174 *
175 * Toggle all the available interrupt ring buffers (VEGA20).
176 */
vega20_ih_toggle_interrupts(struct amdgpu_device * adev,bool enable)177 static int vega20_ih_toggle_interrupts(struct amdgpu_device *adev, bool enable)
178 {
179 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
180 int i;
181 int r;
182
183 for (i = 0; i < ARRAY_SIZE(ih); i++) {
184 if (ih[i]->ring_size) {
185 r = vega20_ih_toggle_ring_interrupts(adev, ih[i], enable);
186 if (r)
187 return r;
188 }
189 }
190
191 return 0;
192 }
193
vega20_ih_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)194 static uint32_t vega20_ih_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
195 {
196 int rb_bufsz = order_base_2(ih->ring_size / 4);
197
198 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
199 MC_SPACE, ih->use_bus_addr ? 1 : 4);
200 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
201 WPTR_OVERFLOW_CLEAR, 1);
202 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
203 WPTR_OVERFLOW_ENABLE, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
205 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
206 * value is written to memory
207 */
208 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
209 WPTR_WRITEBACK_ENABLE, 1);
210 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
211 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
212 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
213
214 return ih_rb_cntl;
215 }
216
vega20_ih_doorbell_rptr(struct amdgpu_ih_ring * ih)217 static uint32_t vega20_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
218 {
219 u32 ih_doorbell_rtpr = 0;
220
221 if (ih->use_doorbell) {
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223 IH_DOORBELL_RPTR, OFFSET,
224 ih->doorbell_index);
225 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
226 IH_DOORBELL_RPTR,
227 ENABLE, 1);
228 } else {
229 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
230 IH_DOORBELL_RPTR,
231 ENABLE, 0);
232 }
233 return ih_doorbell_rtpr;
234 }
235
236 /**
237 * vega20_ih_enable_ring - enable an ih ring buffer
238 *
239 * @adev: amdgpu_device pointer
240 * @ih: amdgpu_ih_ring pointer
241 *
242 * Enable an ih ring buffer (VEGA20)
243 */
vega20_ih_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)244 static int vega20_ih_enable_ring(struct amdgpu_device *adev,
245 struct amdgpu_ih_ring *ih)
246 {
247 struct amdgpu_ih_regs *ih_regs;
248 uint32_t tmp;
249
250 ih_regs = &ih->ih_regs;
251
252 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
253 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
254 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
255
256 tmp = RREG32(ih_regs->ih_rb_cntl);
257 tmp = vega20_ih_rb_cntl(ih, tmp);
258 if (ih == &adev->irq.ih)
259 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
260 if (ih == &adev->irq.ih1)
261 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
262 if (amdgpu_sriov_vf(adev)) {
263 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
264 dev_err(adev->dev, "PSP program IH_RB_CNTL failed!\n");
265 return -ETIMEDOUT;
266 }
267 } else {
268 WREG32(ih_regs->ih_rb_cntl, tmp);
269 }
270
271 if (ih == &adev->irq.ih) {
272 /* set the ih ring 0 writeback address whether it's enabled or not */
273 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
274 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
275 }
276
277 /* set rptr, wptr to 0 */
278 WREG32(ih_regs->ih_rb_wptr, 0);
279 WREG32(ih_regs->ih_rb_rptr, 0);
280
281 WREG32(ih_regs->ih_doorbell_rptr, vega20_ih_doorbell_rptr(ih));
282
283 return 0;
284 }
285
vega20_setup_retry_doorbell(u32 doorbell_index)286 static uint32_t vega20_setup_retry_doorbell(u32 doorbell_index)
287 {
288 u32 val = 0;
289
290 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, OFFSET, doorbell_index);
291 val = REG_SET_FIELD(val, IH_DOORBELL_RPTR, ENABLE, 1);
292
293 return val;
294 }
295
296 /**
297 * vega20_ih_irq_init - init and enable the interrupt ring
298 *
299 * @adev: amdgpu_device pointer
300 *
301 * Allocate a ring buffer for the interrupt controller,
302 * enable the RLC, disable interrupts, enable the IH
303 * ring buffer and enable it (VI).
304 * Called at device load and reume.
305 * Returns 0 for success, errors for failure.
306 */
vega20_ih_irq_init(struct amdgpu_device * adev)307 static int vega20_ih_irq_init(struct amdgpu_device *adev)
308 {
309 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1, &adev->irq.ih2};
310 u32 ih_chicken;
311 int ret;
312 int i;
313
314 /* disable irqs */
315 ret = vega20_ih_toggle_interrupts(adev, false);
316 if (ret)
317 return ret;
318
319 adev->nbio.funcs->ih_control(adev);
320
321 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) &&
322 adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
323 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);
324 if (adev->irq.ih.use_bus_addr) {
325 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
326 MC_SPACE_GPA_ENABLE, 1);
327 }
328 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN, ih_chicken);
329 }
330
331 /* psp firmware won't program IH_CHICKEN for aldebaran
332 * driver needs to program it properly according to
333 * MC_SPACE type in IH_RB_CNTL */
334 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) ||
335 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) {
336 ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN);
337 if (adev->irq.ih.use_bus_addr) {
338 ih_chicken = REG_SET_FIELD(ih_chicken, IH_CHICKEN,
339 MC_SPACE_GPA_ENABLE, 1);
340 }
341 WREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN_ALDEBARAN, ih_chicken);
342 }
343
344 for (i = 0; i < ARRAY_SIZE(ih); i++) {
345 if (ih[i]->ring_size) {
346 ret = vega20_ih_enable_ring(adev, ih[i]);
347 if (ret)
348 return ret;
349 }
350 }
351
352 if (!amdgpu_sriov_vf(adev))
353 adev->nbio.funcs->ih_doorbell_range(adev, adev->irq.ih.use_doorbell,
354 adev->irq.ih.doorbell_index);
355
356 pci_set_master(adev->pdev);
357
358 /* Allocate the doorbell for IH Retry CAM */
359 adev->irq.retry_cam_doorbell_index = (adev->doorbell_index.ih + 3) << 1;
360 WREG32_SOC15(OSSSYS, 0, mmIH_DOORBELL_RETRY_CAM,
361 vega20_setup_retry_doorbell(adev->irq.retry_cam_doorbell_index));
362
363 /* Enable IH Retry CAM */
364 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0) ||
365 adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))
366 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL_ALDEBARAN,
367 ENABLE, 1);
368 else
369 WREG32_FIELD15(OSSSYS, 0, IH_RETRY_INT_CAM_CNTL, ENABLE, 1);
370
371 adev->irq.retry_cam_enabled = true;
372
373 /* enable interrupts */
374 ret = vega20_ih_toggle_interrupts(adev, true);
375 if (ret)
376 return ret;
377
378 if (adev->irq.ih_soft.ring_size)
379 adev->irq.ih_soft.enabled = true;
380
381 return 0;
382 }
383
384 /**
385 * vega20_ih_irq_disable - disable interrupts
386 *
387 * @adev: amdgpu_device pointer
388 *
389 * Disable interrupts on the hw (VEGA20).
390 */
vega20_ih_irq_disable(struct amdgpu_device * adev)391 static void vega20_ih_irq_disable(struct amdgpu_device *adev)
392 {
393 vega20_ih_toggle_interrupts(adev, false);
394
395 /* Wait and acknowledge irq */
396 mdelay(1);
397 }
398
399 /**
400 * vega20_ih_get_wptr - get the IH ring buffer wptr
401 *
402 * @adev: amdgpu_device pointer
403 * @ih: amdgpu_ih_ring pointer
404 *
405 * Get the IH ring buffer wptr from either the register
406 * or the writeback memory buffer (VEGA20). Also check for
407 * ring buffer overflow and deal with it.
408 * Returns the value of the wptr.
409 */
vega20_ih_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)410 static u32 vega20_ih_get_wptr(struct amdgpu_device *adev,
411 struct amdgpu_ih_ring *ih)
412 {
413 u32 wptr, tmp;
414 struct amdgpu_ih_regs *ih_regs;
415
416 if (ih == &adev->irq.ih || ih == &adev->irq.ih_soft) {
417 /* Only ring0 supports writeback. On other rings fall back
418 * to register-based code with overflow checking below.
419 * ih_soft ring doesn't have any backing hardware registers,
420 * update wptr and return.
421 */
422 wptr = le32_to_cpu(*ih->wptr_cpu);
423
424 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
425 goto out;
426 }
427
428 ih_regs = &ih->ih_regs;
429
430 /* Double check that the overflow wasn't already cleared. */
431 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
432 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
433 goto out;
434
435 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
436
437 /* When a ring buffer overflow happen start parsing interrupt
438 * from the last not overwritten vector (wptr + 32). Hopefully
439 * this should allow us to catchup.
440 */
441 tmp = (wptr + 32) & ih->ptr_mask;
442 dev_warn(adev->dev, "IH ring buffer overflow "
443 "(0x%08X, 0x%08X, 0x%08X)\n",
444 wptr, ih->rptr, tmp);
445 ih->rptr = tmp;
446
447 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
448 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
449 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
450
451 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
452 * can be detected.
453 */
454 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
455 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
456
457 out:
458 return (wptr & ih->ptr_mask);
459 }
460
461 /**
462 * vega20_ih_irq_rearm - rearm IRQ if lost
463 *
464 * @adev: amdgpu_device pointer
465 * @ih: amdgpu_ih_ring pointer
466 *
467 */
vega20_ih_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)468 static void vega20_ih_irq_rearm(struct amdgpu_device *adev,
469 struct amdgpu_ih_ring *ih)
470 {
471 uint32_t v = 0;
472 uint32_t i = 0;
473 struct amdgpu_ih_regs *ih_regs;
474
475 ih_regs = &ih->ih_regs;
476
477 /* Rearm IRQ / re-wwrite doorbell if doorbell write is lost */
478 for (i = 0; i < MAX_REARM_RETRY; i++) {
479 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
480 if ((v < ih->ring_size) && (v != ih->rptr))
481 WDOORBELL32(ih->doorbell_index, ih->rptr);
482 else
483 break;
484 }
485 }
486
487 /**
488 * vega20_ih_set_rptr - set the IH ring buffer rptr
489 *
490 * @adev: amdgpu_device pointer
491 * @ih: amdgpu_ih_ring pointer
492 *
493 * Set the IH ring buffer rptr.
494 */
vega20_ih_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)495 static void vega20_ih_set_rptr(struct amdgpu_device *adev,
496 struct amdgpu_ih_ring *ih)
497 {
498 struct amdgpu_ih_regs *ih_regs;
499
500 if (ih == &adev->irq.ih_soft)
501 return;
502
503 if (ih->use_doorbell) {
504 /* XXX check if swapping is necessary on BE */
505 *ih->rptr_cpu = ih->rptr;
506 WDOORBELL32(ih->doorbell_index, ih->rptr);
507
508 if (amdgpu_sriov_vf(adev))
509 vega20_ih_irq_rearm(adev, ih);
510 } else {
511 ih_regs = &ih->ih_regs;
512 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
513 }
514 }
515
516 /**
517 * vega20_ih_self_irq - dispatch work for ring 1 and 2
518 *
519 * @adev: amdgpu_device pointer
520 * @source: irq source
521 * @entry: IV with WPTR update
522 *
523 * Update the WPTR from the IV and schedule work to handle the entries.
524 */
vega20_ih_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)525 static int vega20_ih_self_irq(struct amdgpu_device *adev,
526 struct amdgpu_irq_src *source,
527 struct amdgpu_iv_entry *entry)
528 {
529 switch (entry->ring_id) {
530 case 1:
531 schedule_work(&adev->irq.ih1_work);
532 break;
533 case 2:
534 schedule_work(&adev->irq.ih2_work);
535 break;
536 default:
537 break;
538 }
539 return 0;
540 }
541
542 static const struct amdgpu_irq_src_funcs vega20_ih_self_irq_funcs = {
543 .process = vega20_ih_self_irq,
544 };
545
vega20_ih_set_self_irq_funcs(struct amdgpu_device * adev)546 static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev)
547 {
548 adev->irq.self_irq.num_types = 0;
549 adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs;
550 }
551
vega20_ih_early_init(void * handle)552 static int vega20_ih_early_init(void *handle)
553 {
554 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
555
556 vega20_ih_set_interrupt_funcs(adev);
557 vega20_ih_set_self_irq_funcs(adev);
558 return 0;
559 }
560
vega20_ih_sw_init(void * handle)561 static int vega20_ih_sw_init(void *handle)
562 {
563 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
564 bool use_bus_addr = true;
565 int r;
566
567 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0,
568 &adev->irq.self_irq);
569 if (r)
570 return r;
571
572 if ((adev->flags & AMD_IS_APU) &&
573 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)))
574 use_bus_addr = false;
575
576 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
577 if (r)
578 return r;
579
580 adev->irq.ih.use_doorbell = true;
581 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
582
583 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, PAGE_SIZE, use_bus_addr);
584 if (r)
585 return r;
586
587 adev->irq.ih1.use_doorbell = true;
588 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
589
590 if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) {
591 r = amdgpu_ih_ring_init(adev, &adev->irq.ih2, PAGE_SIZE, true);
592 if (r)
593 return r;
594
595 adev->irq.ih2.use_doorbell = true;
596 adev->irq.ih2.doorbell_index = (adev->doorbell_index.ih + 2) << 1;
597 }
598
599 /* initialize ih control registers offset */
600 vega20_ih_init_register_offset(adev);
601
602 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
603 if (r)
604 return r;
605
606 r = amdgpu_irq_init(adev);
607
608 return r;
609 }
610
vega20_ih_sw_fini(void * handle)611 static int vega20_ih_sw_fini(void *handle)
612 {
613 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
614
615 amdgpu_irq_fini_sw(adev);
616
617 return 0;
618 }
619
vega20_ih_hw_init(void * handle)620 static int vega20_ih_hw_init(void *handle)
621 {
622 int r;
623 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
624
625 r = vega20_ih_irq_init(adev);
626 if (r)
627 return r;
628
629 return 0;
630 }
631
vega20_ih_hw_fini(void * handle)632 static int vega20_ih_hw_fini(void *handle)
633 {
634 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
635
636 vega20_ih_irq_disable(adev);
637
638 return 0;
639 }
640
vega20_ih_suspend(void * handle)641 static int vega20_ih_suspend(void *handle)
642 {
643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
644
645 return vega20_ih_hw_fini(adev);
646 }
647
vega20_ih_resume(void * handle)648 static int vega20_ih_resume(void *handle)
649 {
650 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
651
652 return vega20_ih_hw_init(adev);
653 }
654
vega20_ih_is_idle(void * handle)655 static bool vega20_ih_is_idle(void *handle)
656 {
657 /* todo */
658 return true;
659 }
660
vega20_ih_wait_for_idle(void * handle)661 static int vega20_ih_wait_for_idle(void *handle)
662 {
663 /* todo */
664 return -ETIMEDOUT;
665 }
666
vega20_ih_soft_reset(void * handle)667 static int vega20_ih_soft_reset(void *handle)
668 {
669 /* todo */
670
671 return 0;
672 }
673
vega20_ih_update_clockgating_state(struct amdgpu_device * adev,bool enable)674 static void vega20_ih_update_clockgating_state(struct amdgpu_device *adev,
675 bool enable)
676 {
677 uint32_t data, def, field_val;
678
679 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
680 def = data = RREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL);
681 field_val = enable ? 0 : 1;
682 data = REG_SET_FIELD(data, IH_CLK_CTRL,
683 IH_RETRY_INT_CAM_MEM_CLK_SOFT_OVERRIDE, field_val);
684 data = REG_SET_FIELD(data, IH_CLK_CTRL,
685 IH_BUFFER_MEM_CLK_SOFT_OVERRIDE, field_val);
686 data = REG_SET_FIELD(data, IH_CLK_CTRL,
687 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
688 data = REG_SET_FIELD(data, IH_CLK_CTRL,
689 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
690 data = REG_SET_FIELD(data, IH_CLK_CTRL,
691 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
692 data = REG_SET_FIELD(data, IH_CLK_CTRL,
693 DYN_CLK_SOFT_OVERRIDE, field_val);
694 data = REG_SET_FIELD(data, IH_CLK_CTRL,
695 REG_CLK_SOFT_OVERRIDE, field_val);
696 if (def != data)
697 WREG32_SOC15(OSSSYS, 0, mmIH_CLK_CTRL, data);
698 }
699 }
700
vega20_ih_set_clockgating_state(void * handle,enum amd_clockgating_state state)701 static int vega20_ih_set_clockgating_state(void *handle,
702 enum amd_clockgating_state state)
703 {
704 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
705
706 vega20_ih_update_clockgating_state(adev,
707 state == AMD_CG_STATE_GATE);
708 return 0;
709
710 }
711
vega20_ih_set_powergating_state(void * handle,enum amd_powergating_state state)712 static int vega20_ih_set_powergating_state(void *handle,
713 enum amd_powergating_state state)
714 {
715 return 0;
716 }
717
718 const struct amd_ip_funcs vega20_ih_ip_funcs = {
719 .name = "vega20_ih",
720 .early_init = vega20_ih_early_init,
721 .late_init = NULL,
722 .sw_init = vega20_ih_sw_init,
723 .sw_fini = vega20_ih_sw_fini,
724 .hw_init = vega20_ih_hw_init,
725 .hw_fini = vega20_ih_hw_fini,
726 .suspend = vega20_ih_suspend,
727 .resume = vega20_ih_resume,
728 .is_idle = vega20_ih_is_idle,
729 .wait_for_idle = vega20_ih_wait_for_idle,
730 .soft_reset = vega20_ih_soft_reset,
731 .set_clockgating_state = vega20_ih_set_clockgating_state,
732 .set_powergating_state = vega20_ih_set_powergating_state,
733 };
734
735 static const struct amdgpu_ih_funcs vega20_ih_funcs = {
736 .get_wptr = vega20_ih_get_wptr,
737 .decode_iv = amdgpu_ih_decode_iv_helper,
738 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
739 .set_rptr = vega20_ih_set_rptr
740 };
741
vega20_ih_set_interrupt_funcs(struct amdgpu_device * adev)742 static void vega20_ih_set_interrupt_funcs(struct amdgpu_device *adev)
743 {
744 adev->irq.ih_funcs = &vega20_ih_funcs;
745 }
746
747 const struct amdgpu_ip_block_version vega20_ih_ip_block = {
748 .type = AMD_IP_BLOCK_TYPE_IH,
749 .major = 4,
750 .minor = 2,
751 .rev = 0,
752 .funcs = &vega20_ih_ip_funcs,
753 };
754