1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include "qmi.h"
15 #include "htc.h"
16 #include "wmi.h"
17 #include "hal.h"
18 #include "dp.h"
19 #include "ce.h"
20 #include "mac.h"
21 #include "hw.h"
22 #include "hal_rx.h"
23 #include "reg.h"
24 #include "dbring.h"
25
26 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
27
28 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
29
30 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
31
32 /* Pending management packets threshold for dropping probe responses */
33 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
34
35 #define ATH12K_INVALID_HW_MAC_ID 0xFF
36 #define ATH12K_RX_RATE_TABLE_NUM 320
37 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
38
39 #define ATH12K_MON_TIMER_INTERVAL 10
40 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
41 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
42 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
43 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
44 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
45 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
46
47 enum wme_ac {
48 WME_AC_BE,
49 WME_AC_BK,
50 WME_AC_VI,
51 WME_AC_VO,
52 WME_NUM_AC
53 };
54
55 #define ATH12K_HT_MCS_MAX 7
56 #define ATH12K_VHT_MCS_MAX 9
57 #define ATH12K_HE_MCS_MAX 11
58
59 enum ath12k_crypt_mode {
60 /* Only use hardware crypto engine */
61 ATH12K_CRYPT_MODE_HW,
62 /* Only use software crypto */
63 ATH12K_CRYPT_MODE_SW,
64 };
65
ath12k_tid_to_ac(u32 tid)66 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
67 {
68 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
69 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
70 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
71 WME_AC_VO);
72 }
73
74 enum ath12k_skb_flags {
75 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
76 ATH12K_SKB_CIPHER_SET = BIT(1),
77 };
78
79 struct ath12k_skb_cb {
80 dma_addr_t paddr;
81 struct ath12k *ar;
82 struct ieee80211_vif *vif;
83 dma_addr_t paddr_ext_desc;
84 u32 cipher;
85 u8 flags;
86 };
87
88 struct ath12k_skb_rxcb {
89 dma_addr_t paddr;
90 bool is_first_msdu;
91 bool is_last_msdu;
92 bool is_continuation;
93 bool is_mcbc;
94 bool is_eapol;
95 struct hal_rx_desc *rx_desc;
96 u8 err_rel_src;
97 u8 err_code;
98 u8 mac_id;
99 u8 unmapped;
100 u8 is_frag;
101 u8 tid;
102 u16 peer_id;
103 };
104
105 enum ath12k_hw_rev {
106 ATH12K_HW_QCN9274_HW10,
107 ATH12K_HW_QCN9274_HW20,
108 ATH12K_HW_WCN7850_HW20
109 };
110
111 enum ath12k_firmware_mode {
112 /* the default mode, standard 802.11 functionality */
113 ATH12K_FIRMWARE_MODE_NORMAL,
114
115 /* factory tests etc */
116 ATH12K_FIRMWARE_MODE_FTM,
117 };
118
119 #define ATH12K_IRQ_NUM_MAX 57
120 #define ATH12K_EXT_IRQ_NUM_MAX 16
121
122 struct ath12k_ext_irq_grp {
123 struct ath12k_base *ab;
124 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
125 u32 num_irq;
126 u32 grp_id;
127 u64 timestamp;
128 bool napi_enabled;
129 struct napi_struct napi;
130 struct net_device napi_ndev;
131 };
132
133 #define HEHANDLE_CAP_PHYINFO_SIZE 3
134 #define HECAP_PHYINFO_SIZE 9
135 #define HECAP_MACINFO_SIZE 5
136 #define HECAP_TXRX_MCS_NSS_SIZE 2
137 #define HECAP_PPET16_PPET8_MAX_SIZE 25
138
139 #define HE_PPET16_PPET8_SIZE 8
140
141 /* 802.11ax PPE (PPDU packet Extension) threshold */
142 struct he_ppe_threshold {
143 u32 numss_m1;
144 u32 ru_mask;
145 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
146 };
147
148 struct ath12k_he {
149 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
150 u32 hecap_rxmcsnssmap;
151 u32 hecap_txmcsnssmap;
152 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
153 struct he_ppe_threshold hecap_ppet;
154 u32 heop_param;
155 };
156
157 #define MAX_RADIOS 3
158
159 enum {
160 WMI_HOST_TP_SCALE_MAX = 0,
161 WMI_HOST_TP_SCALE_50 = 1,
162 WMI_HOST_TP_SCALE_25 = 2,
163 WMI_HOST_TP_SCALE_12 = 3,
164 WMI_HOST_TP_SCALE_MIN = 4,
165 WMI_HOST_TP_SCALE_SIZE = 5,
166 };
167
168 enum ath12k_scan_state {
169 ATH12K_SCAN_IDLE,
170 ATH12K_SCAN_STARTING,
171 ATH12K_SCAN_RUNNING,
172 ATH12K_SCAN_ABORTING,
173 };
174
175 enum ath12k_dev_flags {
176 ATH12K_CAC_RUNNING,
177 ATH12K_FLAG_CRASH_FLUSH,
178 ATH12K_FLAG_RAW_MODE,
179 ATH12K_FLAG_HW_CRYPTO_DISABLED,
180 ATH12K_FLAG_RECOVERY,
181 ATH12K_FLAG_UNREGISTERING,
182 ATH12K_FLAG_REGISTERED,
183 ATH12K_FLAG_QMI_FAIL,
184 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
185 ATH12K_FLAG_CE_IRQ_ENABLED,
186 ATH12K_FLAG_EXT_IRQ_ENABLED,
187 };
188
189 enum ath12k_monitor_flags {
190 ATH12K_FLAG_MONITOR_ENABLED,
191 };
192
193 struct ath12k_vif {
194 u32 vdev_id;
195 enum wmi_vdev_type vdev_type;
196 enum wmi_vdev_subtype vdev_subtype;
197 u32 beacon_interval;
198 u32 dtim_period;
199 u16 ast_hash;
200 u16 ast_idx;
201 u16 tcl_metadata;
202 u8 hal_addr_search_flags;
203 u8 search_type;
204
205 struct ath12k *ar;
206 struct ieee80211_vif *vif;
207
208 int bank_id;
209 u8 vdev_id_check_en;
210
211 struct wmi_wmm_params_all_arg wmm_params;
212 struct list_head list;
213 union {
214 struct {
215 u32 uapsd;
216 } sta;
217 struct {
218 /* 127 stations; wmi limit */
219 u8 tim_bitmap[16];
220 u8 tim_len;
221 u32 ssid_len;
222 u8 ssid[IEEE80211_MAX_SSID_LEN];
223 bool hidden_ssid;
224 /* P2P_IE with NoA attribute for P2P_GO case */
225 u32 noa_len;
226 u8 *noa_data;
227 } ap;
228 } u;
229
230 bool is_started;
231 bool is_up;
232 u32 aid;
233 u8 bssid[ETH_ALEN];
234 struct cfg80211_bitrate_mask bitrate_mask;
235 int num_legacy_stations;
236 int rtscts_prot_mode;
237 int txpower;
238 bool rsnie_present;
239 bool wpaie_present;
240 struct ieee80211_chanctx_conf chanctx;
241 u32 key_cipher;
242 u8 tx_encap_type;
243 u8 vdev_stats_id;
244 u32 punct_bitmap;
245 };
246
247 struct ath12k_vif_iter {
248 u32 vdev_id;
249 struct ath12k_vif *arvif;
250 };
251
252 #define HAL_AST_IDX_INVALID 0xFFFF
253 #define HAL_RX_MAX_MCS 12
254 #define HAL_RX_MAX_MCS_HT 31
255 #define HAL_RX_MAX_MCS_VHT 9
256 #define HAL_RX_MAX_MCS_HE 11
257 #define HAL_RX_MAX_NSS 8
258 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
259 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
260 #define ATH12K_RX_RATE_TABLE_NUM 320
261
262 struct ath12k_rx_peer_rate_stats {
263 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
264 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
265 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
266 u64 nss_count[HAL_RX_MAX_NSS];
267 u64 bw_count[HAL_RX_BW_MAX];
268 u64 gi_count[HAL_RX_GI_MAX];
269 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
270 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM];
271 };
272
273 struct ath12k_rx_peer_stats {
274 u64 num_msdu;
275 u64 num_mpdu_fcs_ok;
276 u64 num_mpdu_fcs_err;
277 u64 tcp_msdu_count;
278 u64 udp_msdu_count;
279 u64 other_msdu_count;
280 u64 ampdu_msdu_count;
281 u64 non_ampdu_msdu_count;
282 u64 stbc_count;
283 u64 beamformed_count;
284 u64 mcs_count[HAL_RX_MAX_MCS + 1];
285 u64 nss_count[HAL_RX_MAX_NSS];
286 u64 bw_count[HAL_RX_BW_MAX];
287 u64 gi_count[HAL_RX_GI_MAX];
288 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
289 u64 tid_count[IEEE80211_NUM_TIDS + 1];
290 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
291 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
292 u64 rx_duration;
293 u64 dcm_count;
294 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
295 struct ath12k_rx_peer_rate_stats pkt_stats;
296 struct ath12k_rx_peer_rate_stats byte_stats;
297 };
298
299 #define ATH12K_HE_MCS_NUM 12
300 #define ATH12K_VHT_MCS_NUM 10
301 #define ATH12K_BW_NUM 5
302 #define ATH12K_NSS_NUM 4
303 #define ATH12K_LEGACY_NUM 12
304 #define ATH12K_GI_NUM 4
305 #define ATH12K_HT_MCS_NUM 32
306
307 enum ath12k_pkt_rx_err {
308 ATH12K_PKT_RX_ERR_FCS,
309 ATH12K_PKT_RX_ERR_TKIP,
310 ATH12K_PKT_RX_ERR_CRYPT,
311 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
312 ATH12K_PKT_RX_ERR_MAX,
313 };
314
315 enum ath12k_ampdu_subfrm_num {
316 ATH12K_AMPDU_SUBFRM_NUM_10,
317 ATH12K_AMPDU_SUBFRM_NUM_20,
318 ATH12K_AMPDU_SUBFRM_NUM_30,
319 ATH12K_AMPDU_SUBFRM_NUM_40,
320 ATH12K_AMPDU_SUBFRM_NUM_50,
321 ATH12K_AMPDU_SUBFRM_NUM_60,
322 ATH12K_AMPDU_SUBFRM_NUM_MORE,
323 ATH12K_AMPDU_SUBFRM_NUM_MAX,
324 };
325
326 enum ath12k_amsdu_subfrm_num {
327 ATH12K_AMSDU_SUBFRM_NUM_1,
328 ATH12K_AMSDU_SUBFRM_NUM_2,
329 ATH12K_AMSDU_SUBFRM_NUM_3,
330 ATH12K_AMSDU_SUBFRM_NUM_4,
331 ATH12K_AMSDU_SUBFRM_NUM_MORE,
332 ATH12K_AMSDU_SUBFRM_NUM_MAX,
333 };
334
335 enum ath12k_counter_type {
336 ATH12K_COUNTER_TYPE_BYTES,
337 ATH12K_COUNTER_TYPE_PKTS,
338 ATH12K_COUNTER_TYPE_MAX,
339 };
340
341 enum ath12k_stats_type {
342 ATH12K_STATS_TYPE_SUCC,
343 ATH12K_STATS_TYPE_FAIL,
344 ATH12K_STATS_TYPE_RETRY,
345 ATH12K_STATS_TYPE_AMPDU,
346 ATH12K_STATS_TYPE_MAX,
347 };
348
349 struct ath12k_htt_data_stats {
350 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
351 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
352 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
353 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
354 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
355 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
356 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
357 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
358 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
359 };
360
361 struct ath12k_htt_tx_stats {
362 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
363 u64 tx_duration;
364 u64 ba_fails;
365 u64 ack_fails;
366 u16 ru_start;
367 u16 ru_tones;
368 u32 mu_group[MAX_MU_GROUP_ID];
369 };
370
371 struct ath12k_per_ppdu_tx_stats {
372 u16 succ_pkts;
373 u16 failed_pkts;
374 u16 retry_pkts;
375 u32 succ_bytes;
376 u32 failed_bytes;
377 u32 retry_bytes;
378 };
379
380 struct ath12k_wbm_tx_stats {
381 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
382 };
383
384 struct ath12k_sta {
385 struct ath12k_vif *arvif;
386
387 /* the following are protected by ar->data_lock */
388 u32 changed; /* IEEE80211_RC_* */
389 u32 bw;
390 u32 nss;
391 u32 smps;
392 enum hal_pn_type pn_type;
393
394 struct work_struct update_wk;
395 struct rate_info txrate;
396 struct rate_info last_txrate;
397 u64 rx_duration;
398 u64 tx_duration;
399 u8 rssi_comb;
400 struct ath12k_rx_peer_stats *rx_stats;
401 struct ath12k_wbm_tx_stats *wbm_tx_stats;
402 u32 bw_prev;
403 };
404
405 #define ATH12K_MIN_5G_FREQ 4150
406 #define ATH12K_MIN_6G_FREQ 5925
407 #define ATH12K_MAX_6G_FREQ 7115
408 #define ATH12K_NUM_CHANS 100
409 #define ATH12K_MAX_5G_CHAN 173
410
411 enum ath12k_state {
412 ATH12K_STATE_OFF,
413 ATH12K_STATE_ON,
414 ATH12K_STATE_RESTARTING,
415 ATH12K_STATE_RESTARTED,
416 ATH12K_STATE_WEDGED,
417 /* Add other states as required */
418 };
419
420 /* Antenna noise floor */
421 #define ATH12K_DEFAULT_NOISE_FLOOR -95
422
423 struct ath12k_fw_stats {
424 u32 pdev_id;
425 u32 stats_id;
426 struct list_head pdevs;
427 struct list_head vdevs;
428 struct list_head bcn;
429 };
430
431 struct ath12k_per_peer_tx_stats {
432 u32 succ_bytes;
433 u32 retry_bytes;
434 u32 failed_bytes;
435 u32 duration;
436 u16 succ_pkts;
437 u16 retry_pkts;
438 u16 failed_pkts;
439 u16 ru_start;
440 u16 ru_tones;
441 u8 ba_fails;
442 u8 ppdu_type;
443 u32 mu_grpid;
444 u32 mu_pos;
445 bool is_ampdu;
446 };
447
448 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
449 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
450
451 struct ath12k {
452 struct ath12k_base *ab;
453 struct ath12k_pdev *pdev;
454 struct ieee80211_hw *hw;
455 struct ieee80211_ops *ops;
456 struct ath12k_wmi_pdev *wmi;
457 struct ath12k_pdev_dp dp;
458 u8 mac_addr[ETH_ALEN];
459 u32 ht_cap_info;
460 u32 vht_cap_info;
461 struct ath12k_he ar_he;
462 enum ath12k_state state;
463 bool supports_6ghz;
464 struct {
465 struct completion started;
466 struct completion completed;
467 struct completion on_channel;
468 struct delayed_work timeout;
469 enum ath12k_scan_state state;
470 bool is_roc;
471 int vdev_id;
472 int roc_freq;
473 bool roc_notify;
474 } scan;
475
476 struct {
477 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
478 struct ieee80211_sband_iftype_data
479 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
480 } mac;
481
482 unsigned long dev_flags;
483 unsigned int filter_flags;
484 unsigned long monitor_flags;
485 u32 min_tx_power;
486 u32 max_tx_power;
487 u32 txpower_limit_2g;
488 u32 txpower_limit_5g;
489 u32 txpower_scale;
490 u32 power_scale;
491 u32 chan_tx_pwr;
492 u32 num_stations;
493 u32 max_num_stations;
494 bool monitor_present;
495 /* To synchronize concurrent synchronous mac80211 callback operations,
496 * concurrent debugfs configuration and concurrent FW statistics events.
497 */
498 struct mutex conf_mutex;
499 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
500 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info,
501 * channel context data, survey info, test mode data.
502 */
503 spinlock_t data_lock;
504
505 struct list_head arvifs;
506 /* should never be NULL; needed for regular htt rx */
507 struct ieee80211_channel *rx_channel;
508
509 /* valid during scan; needed for mgmt rx during scan */
510 struct ieee80211_channel *scan_channel;
511
512 u8 cfg_tx_chainmask;
513 u8 cfg_rx_chainmask;
514 u8 num_rx_chains;
515 u8 num_tx_chains;
516 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
517 u8 pdev_idx;
518 u8 lmac_id;
519
520 struct completion peer_assoc_done;
521 struct completion peer_delete_done;
522
523 int install_key_status;
524 struct completion install_key_done;
525
526 int last_wmi_vdev_start_status;
527 struct completion vdev_setup_done;
528 struct completion vdev_delete_done;
529
530 int num_peers;
531 int max_num_peers;
532 u32 num_started_vdevs;
533 u32 num_created_vdevs;
534 unsigned long long allocated_vdev_map;
535
536 struct idr txmgmt_idr;
537 /* protects txmgmt_idr data */
538 spinlock_t txmgmt_idr_lock;
539 atomic_t num_pending_mgmt_tx;
540 wait_queue_head_t txmgmt_empty_waitq;
541
542 /* cycle count is reported twice for each visited channel during scan.
543 * access protected by data_lock
544 */
545 u32 survey_last_rx_clear_count;
546 u32 survey_last_cycle_count;
547
548 /* Channel info events are expected to come in pairs without and with
549 * COMPLETE flag set respectively for each channel visit during scan.
550 *
551 * However there are deviations from this rule. This flag is used to
552 * avoid reporting garbage data.
553 */
554 bool ch_info_can_report_survey;
555 struct survey_info survey[ATH12K_NUM_CHANS];
556 struct completion bss_survey_done;
557
558 struct work_struct regd_update_work;
559
560 struct work_struct wmi_mgmt_tx_work;
561 struct sk_buff_head wmi_mgmt_tx_queue;
562
563 struct ath12k_per_peer_tx_stats peer_tx_stats;
564 struct list_head ppdu_stats_info;
565 u32 ppdu_stat_list_depth;
566
567 struct ath12k_per_peer_tx_stats cached_stats;
568 u32 last_ppdu_id;
569 u32 cached_ppdu_id;
570
571 bool dfs_block_radar_events;
572 bool monitor_conf_enabled;
573 bool monitor_vdev_created;
574 bool monitor_started;
575 int monitor_vdev_id;
576 };
577
578 struct ath12k_band_cap {
579 u32 phy_id;
580 u32 max_bw_supported;
581 u32 ht_cap_info;
582 u32 he_cap_info[2];
583 u32 he_mcs;
584 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
585 struct ath12k_wmi_ppe_threshold_arg he_ppet;
586 u16 he_6ghz_capa;
587 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
588 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
589 u32 eht_mcs_20_only;
590 u32 eht_mcs_80;
591 u32 eht_mcs_160;
592 u32 eht_mcs_320;
593 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
594 u32 eht_cap_info_internal;
595 };
596
597 struct ath12k_pdev_cap {
598 u32 supported_bands;
599 u32 ampdu_density;
600 u32 vht_cap;
601 u32 vht_mcs;
602 u32 he_mcs;
603 u32 tx_chain_mask;
604 u32 rx_chain_mask;
605 u32 tx_chain_mask_shift;
606 u32 rx_chain_mask_shift;
607 struct ath12k_band_cap band[NUM_NL80211_BANDS];
608 };
609
610 struct mlo_timestamp {
611 u32 info;
612 u32 sync_timestamp_lo_us;
613 u32 sync_timestamp_hi_us;
614 u32 mlo_offset_lo;
615 u32 mlo_offset_hi;
616 u32 mlo_offset_clks;
617 u32 mlo_comp_clks;
618 u32 mlo_comp_timer;
619 };
620
621 struct ath12k_pdev {
622 struct ath12k *ar;
623 u32 pdev_id;
624 struct ath12k_pdev_cap cap;
625 u8 mac_addr[ETH_ALEN];
626 struct mlo_timestamp timestamp;
627 };
628
629 struct ath12k_fw_pdev {
630 u32 pdev_id;
631 u32 phy_id;
632 u32 supported_bands;
633 };
634
635 struct ath12k_board_data {
636 const struct firmware *fw;
637 const void *data;
638 size_t len;
639 };
640
641 struct ath12k_soc_dp_tx_err_stats {
642 /* TCL Ring Descriptor unavailable */
643 u32 desc_na[DP_TCL_NUM_RING_MAX];
644 /* Other failures during dp_tx due to mem allocation failure
645 * idr unavailable etc.
646 */
647 atomic_t misc_fail;
648 };
649
650 struct ath12k_soc_dp_stats {
651 u32 err_ring_pkts;
652 u32 invalid_rbm;
653 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
654 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
655 u32 hal_reo_error[DP_REO_DST_RING_MAX];
656 struct ath12k_soc_dp_tx_err_stats tx_err;
657 };
658
659 /* Master structure to hold the hw data which may be used in core module */
660 struct ath12k_base {
661 enum ath12k_hw_rev hw_rev;
662 struct platform_device *pdev;
663 struct device *dev;
664 struct ath12k_qmi qmi;
665 struct ath12k_wmi_base wmi_ab;
666 struct completion fw_ready;
667 int num_radios;
668 /* HW channel counters frequency value in hertz common to all MACs */
669 u32 cc_freq_hz;
670
671 struct ath12k_htc htc;
672
673 struct ath12k_dp dp;
674
675 void __iomem *mem;
676 unsigned long mem_len;
677
678 struct {
679 enum ath12k_bus bus;
680 const struct ath12k_hif_ops *ops;
681 } hif;
682
683 struct ath12k_ce ce;
684 struct timer_list rx_replenish_retry;
685 struct ath12k_hal hal;
686 /* To synchronize core_start/core_stop */
687 struct mutex core_lock;
688 /* Protects data like peers */
689 spinlock_t base_lock;
690
691 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
692 *
693 * Firmware maintains data for all bands but advertises a single
694 * phy to the host which is stored as a single element in this
695 * array.
696 *
697 * Other devices:
698 *
699 * This array will contain as many elements as the number of
700 * radios.
701 */
702 struct ath12k_pdev pdevs[MAX_RADIOS];
703
704 /* struct ath12k_hw_params::single_pdev_only devices use this to
705 * store phy specific data
706 */
707 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
708 u8 fw_pdev_count;
709
710 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
711 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
712 unsigned long long free_vdev_map;
713 unsigned long long free_vdev_stats_id_map;
714 struct list_head peers;
715 wait_queue_head_t peer_mapping_wq;
716 u8 mac_addr[ETH_ALEN];
717 bool wmi_ready;
718 u32 wlan_init_status;
719 int irq_num[ATH12K_IRQ_NUM_MAX];
720 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
721 struct napi_struct *napi;
722 struct ath12k_wmi_target_cap_arg target_caps;
723 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
724 bool pdevs_macaddr_valid;
725 int bd_api;
726
727 const struct ath12k_hw_params *hw_params;
728
729 const struct firmware *cal_file;
730
731 /* Below regd's are protected by ab->data_lock */
732 /* This is the regd set for every radio
733 * by the firmware during initialization
734 */
735 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
736 /* This regd is set during dynamic country setting
737 * This may or may not be used during the runtime
738 */
739 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
740
741 /* Current DFS Regulatory */
742 enum ath12k_dfs_region dfs_region;
743 struct ath12k_soc_dp_stats soc_stats;
744
745 unsigned long dev_flags;
746 struct completion driver_recovery;
747 struct workqueue_struct *workqueue;
748 struct work_struct restart_work;
749 struct workqueue_struct *workqueue_aux;
750 struct work_struct reset_work;
751 atomic_t reset_count;
752 atomic_t recovery_count;
753 atomic_t recovery_start_count;
754 bool is_reset;
755 struct completion reset_complete;
756 struct completion reconfigure_complete;
757 struct completion recovery_start;
758 /* continuous recovery fail count */
759 atomic_t fail_cont_count;
760 unsigned long reset_fail_timeout;
761 struct {
762 /* protected by data_lock */
763 u32 fw_crash_counter;
764 } stats;
765 u32 pktlog_defs_checksum;
766
767 struct ath12k_dbring_cap *db_caps;
768 u32 num_db_cap;
769
770 struct timer_list mon_reap_timer;
771
772 struct completion htc_suspend;
773
774 u64 fw_soc_drop_count;
775 bool static_window_map;
776
777 /* must be last */
778 u8 drv_priv[] __aligned(sizeof(void *));
779 };
780
781 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
782 int ath12k_core_pre_init(struct ath12k_base *ab);
783 int ath12k_core_init(struct ath12k_base *ath12k);
784 void ath12k_core_deinit(struct ath12k_base *ath12k);
785 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
786 enum ath12k_bus bus);
787 void ath12k_core_free(struct ath12k_base *ath12k);
788 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
789 struct ath12k_board_data *bd,
790 char *filename);
791 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
792 struct ath12k_board_data *bd);
793 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
794
795 void ath12k_core_halt(struct ath12k *ar);
796 int ath12k_core_resume(struct ath12k_base *ab);
797 int ath12k_core_suspend(struct ath12k_base *ab);
798
799 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
800 const char *filename);
801
ath12k_scan_state_str(enum ath12k_scan_state state)802 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
803 {
804 switch (state) {
805 case ATH12K_SCAN_IDLE:
806 return "idle";
807 case ATH12K_SCAN_STARTING:
808 return "starting";
809 case ATH12K_SCAN_RUNNING:
810 return "running";
811 case ATH12K_SCAN_ABORTING:
812 return "aborting";
813 }
814
815 return "unknown";
816 }
817
ATH12K_SKB_CB(struct sk_buff * skb)818 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
819 {
820 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
821 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
822 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
823 }
824
ATH12K_SKB_RXCB(struct sk_buff * skb)825 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
826 {
827 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
828 return (struct ath12k_skb_rxcb *)skb->cb;
829 }
830
ath12k_vif_to_arvif(struct ieee80211_vif * vif)831 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif)
832 {
833 return (struct ath12k_vif *)vif->drv_priv;
834 }
835
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)836 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
837 int mac_id)
838 {
839 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
840 }
841
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)842 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
843 const char *filename,
844 void *buf, size_t buf_len)
845 {
846 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
847 ab->hw_params->fw.dir, filename);
848 }
849
ath12k_bus_str(enum ath12k_bus bus)850 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
851 {
852 switch (bus) {
853 case ATH12K_BUS_PCI:
854 return "pci";
855 }
856
857 return "unknown";
858 }
859
860 #endif /* _CORE_H_ */
861