1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Driver for the Texas Instruments TAS2764 CODEC
4 // Copyright (C) 2020 Texas Instruments Inc.
5
6 #include <linux/module.h>
7 #include <linux/moduleparam.h>
8 #include <linux/err.h>
9 #include <linux/init.h>
10 #include <linux/delay.h>
11 #include <linux/pm.h>
12 #include <linux/i2c.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/regmap.h>
17 #include <linux/of.h>
18 #include <linux/of_gpio.h>
19 #include <linux/slab.h>
20 #include <sound/soc.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/initval.h>
24 #include <sound/tlv.h>
25
26 #include "tas2764.h"
27
28 struct tas2764_priv {
29 struct snd_soc_component *component;
30 struct gpio_desc *reset_gpio;
31 struct gpio_desc *sdz_gpio;
32 struct regmap *regmap;
33 struct device *dev;
34 int irq;
35
36 int v_sense_slot;
37 int i_sense_slot;
38
39 bool dac_powered;
40 bool unmuted;
41 };
42
43 static const char *tas2764_int_ltch0_msgs[8] = {
44 "fault: over temperature", /* INT_LTCH0 & BIT(0) */
45 "fault: over current",
46 "fault: bad TDM clock",
47 "limiter active",
48 "fault: PVDD below limiter inflection point",
49 "fault: limiter max attenuation",
50 "fault: BOP infinite hold",
51 "fault: BOP mute", /* INT_LTCH0 & BIT(7) */
52 };
53
54 static const unsigned int tas2764_int_readout_regs[6] = {
55 TAS2764_INT_LTCH0,
56 TAS2764_INT_LTCH1,
57 TAS2764_INT_LTCH1_0,
58 TAS2764_INT_LTCH2,
59 TAS2764_INT_LTCH3,
60 TAS2764_INT_LTCH4,
61 };
62
tas2764_irq(int irq,void * data)63 static irqreturn_t tas2764_irq(int irq, void *data)
64 {
65 struct tas2764_priv *tas2764 = data;
66 u8 latched[6] = {0, 0, 0, 0, 0, 0};
67 int ret = IRQ_NONE;
68 int i;
69
70 for (i = 0; i < ARRAY_SIZE(latched); i++)
71 latched[i] = snd_soc_component_read(tas2764->component,
72 tas2764_int_readout_regs[i]);
73
74 for (i = 0; i < 8; i++) {
75 if (latched[0] & BIT(i)) {
76 dev_crit_ratelimited(tas2764->dev, "%s\n",
77 tas2764_int_ltch0_msgs[i]);
78 ret = IRQ_HANDLED;
79 }
80 }
81
82 if (latched[0]) {
83 dev_err_ratelimited(tas2764->dev, "other context to the fault: %02x,%02x,%02x,%02x,%02x",
84 latched[1], latched[2], latched[3], latched[4], latched[5]);
85 snd_soc_component_update_bits(tas2764->component,
86 TAS2764_INT_CLK_CFG,
87 TAS2764_INT_CLK_CFG_IRQZ_CLR,
88 TAS2764_INT_CLK_CFG_IRQZ_CLR);
89 }
90
91 return ret;
92 }
93
tas2764_reset(struct tas2764_priv * tas2764)94 static void tas2764_reset(struct tas2764_priv *tas2764)
95 {
96 if (tas2764->reset_gpio) {
97 gpiod_set_value_cansleep(tas2764->reset_gpio, 0);
98 msleep(20);
99 gpiod_set_value_cansleep(tas2764->reset_gpio, 1);
100 usleep_range(1000, 2000);
101 }
102
103 snd_soc_component_write(tas2764->component, TAS2764_SW_RST,
104 TAS2764_RST);
105 usleep_range(1000, 2000);
106 }
107
tas2764_update_pwr_ctrl(struct tas2764_priv * tas2764)108 static int tas2764_update_pwr_ctrl(struct tas2764_priv *tas2764)
109 {
110 struct snd_soc_component *component = tas2764->component;
111 unsigned int val;
112 int ret;
113
114 if (tas2764->dac_powered)
115 val = tas2764->unmuted ?
116 TAS2764_PWR_CTRL_ACTIVE : TAS2764_PWR_CTRL_MUTE;
117 else
118 val = TAS2764_PWR_CTRL_SHUTDOWN;
119
120 ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
121 TAS2764_PWR_CTRL_MASK, val);
122 if (ret < 0)
123 return ret;
124
125 return 0;
126 }
127
128 #ifdef CONFIG_PM
tas2764_codec_suspend(struct snd_soc_component * component)129 static int tas2764_codec_suspend(struct snd_soc_component *component)
130 {
131 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
132 int ret;
133
134 ret = snd_soc_component_update_bits(component, TAS2764_PWR_CTRL,
135 TAS2764_PWR_CTRL_MASK,
136 TAS2764_PWR_CTRL_SHUTDOWN);
137
138 if (ret < 0)
139 return ret;
140
141 if (tas2764->sdz_gpio)
142 gpiod_set_value_cansleep(tas2764->sdz_gpio, 0);
143
144 regcache_cache_only(tas2764->regmap, true);
145 regcache_mark_dirty(tas2764->regmap);
146
147 return 0;
148 }
149
tas2764_codec_resume(struct snd_soc_component * component)150 static int tas2764_codec_resume(struct snd_soc_component *component)
151 {
152 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
153 int ret;
154
155 if (tas2764->sdz_gpio) {
156 gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
157 usleep_range(1000, 2000);
158 }
159
160 ret = tas2764_update_pwr_ctrl(tas2764);
161
162 if (ret < 0)
163 return ret;
164
165 regcache_cache_only(tas2764->regmap, false);
166
167 return regcache_sync(tas2764->regmap);
168 }
169 #else
170 #define tas2764_codec_suspend NULL
171 #define tas2764_codec_resume NULL
172 #endif
173
174 static const char * const tas2764_ASI1_src[] = {
175 "I2C offset", "Left", "Right", "LeftRightDiv2",
176 };
177
178 static SOC_ENUM_SINGLE_DECL(
179 tas2764_ASI1_src_enum, TAS2764_TDM_CFG2, TAS2764_TDM_CFG2_SCFG_SHIFT,
180 tas2764_ASI1_src);
181
182 static const struct snd_kcontrol_new tas2764_asi1_mux =
183 SOC_DAPM_ENUM("ASI1 Source", tas2764_ASI1_src_enum);
184
tas2764_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)185 static int tas2764_dac_event(struct snd_soc_dapm_widget *w,
186 struct snd_kcontrol *kcontrol, int event)
187 {
188 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
189 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
190 int ret;
191
192 switch (event) {
193 case SND_SOC_DAPM_POST_PMU:
194 tas2764->dac_powered = true;
195 ret = tas2764_update_pwr_ctrl(tas2764);
196 break;
197 case SND_SOC_DAPM_PRE_PMD:
198 tas2764->dac_powered = false;
199 ret = tas2764_update_pwr_ctrl(tas2764);
200 break;
201 default:
202 dev_err(tas2764->dev, "Unsupported event\n");
203 return -EINVAL;
204 }
205
206 if (ret < 0)
207 return ret;
208
209 return 0;
210 }
211
212 static const struct snd_kcontrol_new isense_switch =
213 SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN, 1, 1);
214 static const struct snd_kcontrol_new vsense_switch =
215 SOC_DAPM_SINGLE("Switch", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN, 1, 1);
216
217 static const struct snd_soc_dapm_widget tas2764_dapm_widgets[] = {
218 SND_SOC_DAPM_AIF_IN("ASI1", "ASI1 Playback", 0, SND_SOC_NOPM, 0, 0),
219 SND_SOC_DAPM_MUX("ASI1 Sel", SND_SOC_NOPM, 0, 0, &tas2764_asi1_mux),
220 SND_SOC_DAPM_SWITCH("ISENSE", TAS2764_PWR_CTRL, TAS2764_ISENSE_POWER_EN,
221 1, &isense_switch),
222 SND_SOC_DAPM_SWITCH("VSENSE", TAS2764_PWR_CTRL, TAS2764_VSENSE_POWER_EN,
223 1, &vsense_switch),
224 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0, tas2764_dac_event,
225 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
226 SND_SOC_DAPM_OUTPUT("OUT"),
227 SND_SOC_DAPM_SIGGEN("VMON"),
228 SND_SOC_DAPM_SIGGEN("IMON")
229 };
230
231 static const struct snd_soc_dapm_route tas2764_audio_map[] = {
232 {"ASI1 Sel", "I2C offset", "ASI1"},
233 {"ASI1 Sel", "Left", "ASI1"},
234 {"ASI1 Sel", "Right", "ASI1"},
235 {"ASI1 Sel", "LeftRightDiv2", "ASI1"},
236 {"DAC", NULL, "ASI1 Sel"},
237 {"OUT", NULL, "DAC"},
238 {"ISENSE", "Switch", "IMON"},
239 {"VSENSE", "Switch", "VMON"},
240 };
241
tas2764_mute(struct snd_soc_dai * dai,int mute,int direction)242 static int tas2764_mute(struct snd_soc_dai *dai, int mute, int direction)
243 {
244 struct tas2764_priv *tas2764 =
245 snd_soc_component_get_drvdata(dai->component);
246
247 tas2764->unmuted = !mute;
248 return tas2764_update_pwr_ctrl(tas2764);
249 }
250
tas2764_set_bitwidth(struct tas2764_priv * tas2764,int bitwidth)251 static int tas2764_set_bitwidth(struct tas2764_priv *tas2764, int bitwidth)
252 {
253 struct snd_soc_component *component = tas2764->component;
254 int sense_en;
255 int val;
256 int ret;
257
258 switch (bitwidth) {
259 case SNDRV_PCM_FORMAT_S16_LE:
260 ret = snd_soc_component_update_bits(component,
261 TAS2764_TDM_CFG2,
262 TAS2764_TDM_CFG2_RXW_MASK,
263 TAS2764_TDM_CFG2_RXW_16BITS);
264 break;
265 case SNDRV_PCM_FORMAT_S24_LE:
266 ret = snd_soc_component_update_bits(component,
267 TAS2764_TDM_CFG2,
268 TAS2764_TDM_CFG2_RXW_MASK,
269 TAS2764_TDM_CFG2_RXW_24BITS);
270 break;
271 case SNDRV_PCM_FORMAT_S32_LE:
272 ret = snd_soc_component_update_bits(component,
273 TAS2764_TDM_CFG2,
274 TAS2764_TDM_CFG2_RXW_MASK,
275 TAS2764_TDM_CFG2_RXW_32BITS);
276 break;
277
278 default:
279 return -EINVAL;
280 }
281
282 if (ret < 0)
283 return ret;
284
285 val = snd_soc_component_read(tas2764->component, TAS2764_PWR_CTRL);
286 if (val < 0)
287 return val;
288
289 if (val & (1 << TAS2764_VSENSE_POWER_EN))
290 sense_en = 0;
291 else
292 sense_en = TAS2764_TDM_CFG5_VSNS_ENABLE;
293
294 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
295 TAS2764_TDM_CFG5_VSNS_ENABLE,
296 sense_en);
297 if (ret < 0)
298 return ret;
299
300 if (val & (1 << TAS2764_ISENSE_POWER_EN))
301 sense_en = 0;
302 else
303 sense_en = TAS2764_TDM_CFG6_ISNS_ENABLE;
304
305 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
306 TAS2764_TDM_CFG6_ISNS_ENABLE,
307 sense_en);
308 if (ret < 0)
309 return ret;
310
311 return 0;
312 }
313
tas2764_set_samplerate(struct tas2764_priv * tas2764,int samplerate)314 static int tas2764_set_samplerate(struct tas2764_priv *tas2764, int samplerate)
315 {
316 struct snd_soc_component *component = tas2764->component;
317 int ramp_rate_val;
318 int ret;
319
320 switch (samplerate) {
321 case 48000:
322 ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
323 TAS2764_TDM_CFG0_44_1_48KHZ;
324 break;
325 case 44100:
326 ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
327 TAS2764_TDM_CFG0_44_1_48KHZ;
328 break;
329 case 96000:
330 ramp_rate_val = TAS2764_TDM_CFG0_SMP_48KHZ |
331 TAS2764_TDM_CFG0_88_2_96KHZ;
332 break;
333 case 88200:
334 ramp_rate_val = TAS2764_TDM_CFG0_SMP_44_1KHZ |
335 TAS2764_TDM_CFG0_88_2_96KHZ;
336 break;
337 default:
338 return -EINVAL;
339 }
340
341 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0,
342 TAS2764_TDM_CFG0_SMP_MASK |
343 TAS2764_TDM_CFG0_MASK,
344 ramp_rate_val);
345 if (ret < 0)
346 return ret;
347
348 return 0;
349 }
350
tas2764_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)351 static int tas2764_hw_params(struct snd_pcm_substream *substream,
352 struct snd_pcm_hw_params *params,
353 struct snd_soc_dai *dai)
354 {
355 struct snd_soc_component *component = dai->component;
356 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
357 int ret;
358
359 ret = tas2764_set_bitwidth(tas2764, params_format(params));
360 if (ret < 0)
361 return ret;
362
363 return tas2764_set_samplerate(tas2764, params_rate(params));
364 }
365
tas2764_set_fmt(struct snd_soc_dai * dai,unsigned int fmt)366 static int tas2764_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
367 {
368 struct snd_soc_component *component = dai->component;
369 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
370 u8 tdm_rx_start_slot = 0, asi_cfg_0 = 0, asi_cfg_1 = 0, asi_cfg_4 = 0;
371 int ret;
372
373 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
374 case SND_SOC_DAIFMT_NB_IF:
375 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
376 fallthrough;
377 case SND_SOC_DAIFMT_NB_NF:
378 asi_cfg_1 = TAS2764_TDM_CFG1_RX_RISING;
379 asi_cfg_4 = TAS2764_TDM_CFG4_TX_FALLING;
380 break;
381 case SND_SOC_DAIFMT_IB_IF:
382 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
383 fallthrough;
384 case SND_SOC_DAIFMT_IB_NF:
385 asi_cfg_1 = TAS2764_TDM_CFG1_RX_FALLING;
386 asi_cfg_4 = TAS2764_TDM_CFG4_TX_RISING;
387 break;
388 }
389
390 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
391 TAS2764_TDM_CFG1_RX_MASK,
392 asi_cfg_1);
393 if (ret < 0)
394 return ret;
395
396 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG4,
397 TAS2764_TDM_CFG4_TX_MASK,
398 asi_cfg_4);
399 if (ret < 0)
400 return ret;
401
402 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
403 case SND_SOC_DAIFMT_I2S:
404 asi_cfg_0 ^= TAS2764_TDM_CFG0_FRAME_START;
405 fallthrough;
406 case SND_SOC_DAIFMT_DSP_A:
407 tdm_rx_start_slot = 1;
408 break;
409 case SND_SOC_DAIFMT_DSP_B:
410 case SND_SOC_DAIFMT_LEFT_J:
411 tdm_rx_start_slot = 0;
412 break;
413 default:
414 dev_err(tas2764->dev,
415 "DAI Format is not found, fmt=0x%x\n", fmt);
416 return -EINVAL;
417 }
418
419 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG0,
420 TAS2764_TDM_CFG0_FRAME_START,
421 asi_cfg_0);
422 if (ret < 0)
423 return ret;
424
425 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG1,
426 TAS2764_TDM_CFG1_MASK,
427 (tdm_rx_start_slot << TAS2764_TDM_CFG1_51_SHIFT));
428 if (ret < 0)
429 return ret;
430
431 return 0;
432 }
433
tas2764_set_dai_tdm_slot(struct snd_soc_dai * dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)434 static int tas2764_set_dai_tdm_slot(struct snd_soc_dai *dai,
435 unsigned int tx_mask,
436 unsigned int rx_mask,
437 int slots, int slot_width)
438 {
439 struct snd_soc_component *component = dai->component;
440 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
441 int left_slot, right_slot;
442 int slots_cfg;
443 int slot_size;
444 int ret;
445
446 if (tx_mask == 0 || rx_mask != 0)
447 return -EINVAL;
448
449 left_slot = __ffs(tx_mask);
450 tx_mask &= ~(1 << left_slot);
451 if (tx_mask == 0) {
452 right_slot = left_slot;
453 } else {
454 right_slot = __ffs(tx_mask);
455 tx_mask &= ~(1 << right_slot);
456 }
457
458 if (tx_mask != 0 || left_slot >= slots || right_slot >= slots)
459 return -EINVAL;
460
461 slots_cfg = (right_slot << TAS2764_TDM_CFG3_RXS_SHIFT) | left_slot;
462
463 ret = snd_soc_component_write(component, TAS2764_TDM_CFG3, slots_cfg);
464 if (ret)
465 return ret;
466
467 switch (slot_width) {
468 case 16:
469 slot_size = TAS2764_TDM_CFG2_RXS_16BITS;
470 break;
471 case 24:
472 slot_size = TAS2764_TDM_CFG2_RXS_24BITS;
473 break;
474 case 32:
475 slot_size = TAS2764_TDM_CFG2_RXS_32BITS;
476 break;
477 default:
478 return -EINVAL;
479 }
480
481 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG2,
482 TAS2764_TDM_CFG2_RXS_MASK,
483 slot_size);
484 if (ret < 0)
485 return ret;
486
487 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG5,
488 TAS2764_TDM_CFG5_50_MASK,
489 tas2764->v_sense_slot);
490 if (ret < 0)
491 return ret;
492
493 ret = snd_soc_component_update_bits(component, TAS2764_TDM_CFG6,
494 TAS2764_TDM_CFG6_50_MASK,
495 tas2764->i_sense_slot);
496 if (ret < 0)
497 return ret;
498
499 return 0;
500 }
501
502 static const struct snd_soc_dai_ops tas2764_dai_ops = {
503 .mute_stream = tas2764_mute,
504 .hw_params = tas2764_hw_params,
505 .set_fmt = tas2764_set_fmt,
506 .set_tdm_slot = tas2764_set_dai_tdm_slot,
507 .no_capture_mute = 1,
508 };
509
510 #define TAS2764_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
511 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
512
513 #define TAS2764_RATES (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
514 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_88200)
515
516 static struct snd_soc_dai_driver tas2764_dai_driver[] = {
517 {
518 .name = "tas2764 ASI1",
519 .id = 0,
520 .playback = {
521 .stream_name = "ASI1 Playback",
522 .channels_min = 1,
523 .channels_max = 2,
524 .rates = TAS2764_RATES,
525 .formats = TAS2764_FORMATS,
526 },
527 .capture = {
528 .stream_name = "ASI1 Capture",
529 .channels_min = 0,
530 .channels_max = 2,
531 .rates = TAS2764_RATES,
532 .formats = TAS2764_FORMATS,
533 },
534 .ops = &tas2764_dai_ops,
535 .symmetric_rate = 1,
536 },
537 };
538
tas2764_codec_probe(struct snd_soc_component * component)539 static int tas2764_codec_probe(struct snd_soc_component *component)
540 {
541 struct tas2764_priv *tas2764 = snd_soc_component_get_drvdata(component);
542 int ret;
543
544 tas2764->component = component;
545
546 if (tas2764->sdz_gpio) {
547 gpiod_set_value_cansleep(tas2764->sdz_gpio, 1);
548 usleep_range(1000, 2000);
549 }
550
551 tas2764_reset(tas2764);
552
553 if (tas2764->irq) {
554 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK0, 0xff);
555 if (ret < 0)
556 return ret;
557
558 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK1, 0xff);
559 if (ret < 0)
560 return ret;
561
562 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK2, 0xff);
563 if (ret < 0)
564 return ret;
565
566 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK3, 0xff);
567 if (ret < 0)
568 return ret;
569
570 ret = snd_soc_component_write(tas2764->component, TAS2764_INT_MASK4, 0xff);
571 if (ret < 0)
572 return ret;
573
574 ret = devm_request_threaded_irq(tas2764->dev, tas2764->irq, NULL, tas2764_irq,
575 IRQF_ONESHOT | IRQF_SHARED | IRQF_TRIGGER_LOW,
576 "tas2764", tas2764);
577 if (ret)
578 dev_warn(tas2764->dev, "failed to request IRQ: %d\n", ret);
579 }
580
581 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG5,
582 TAS2764_TDM_CFG5_VSNS_ENABLE, 0);
583 if (ret < 0)
584 return ret;
585
586 ret = snd_soc_component_update_bits(tas2764->component, TAS2764_TDM_CFG6,
587 TAS2764_TDM_CFG6_ISNS_ENABLE, 0);
588 if (ret < 0)
589 return ret;
590
591 return 0;
592 }
593
594 static DECLARE_TLV_DB_SCALE(tas2764_digital_tlv, 1100, 50, 0);
595 static DECLARE_TLV_DB_SCALE(tas2764_playback_volume, -10050, 50, 1);
596
597 static const char * const tas2764_hpf_texts[] = {
598 "Disabled", "2 Hz", "50 Hz", "100 Hz", "200 Hz",
599 "400 Hz", "800 Hz"
600 };
601
602 static SOC_ENUM_SINGLE_DECL(
603 tas2764_hpf_enum, TAS2764_DC_BLK0,
604 TAS2764_DC_BLK0_HPF_FREQ_PB_SHIFT, tas2764_hpf_texts);
605
606 static const struct snd_kcontrol_new tas2764_snd_controls[] = {
607 SOC_SINGLE_TLV("Speaker Volume", TAS2764_DVC, 0,
608 TAS2764_DVC_MAX, 1, tas2764_playback_volume),
609 SOC_SINGLE_TLV("Amp Gain Volume", TAS2764_CHNL_0, 1, 0x14, 0,
610 tas2764_digital_tlv),
611 SOC_ENUM("HPF Corner Frequency", tas2764_hpf_enum),
612 };
613
614 static const struct snd_soc_component_driver soc_component_driver_tas2764 = {
615 .probe = tas2764_codec_probe,
616 .suspend = tas2764_codec_suspend,
617 .resume = tas2764_codec_resume,
618 .controls = tas2764_snd_controls,
619 .num_controls = ARRAY_SIZE(tas2764_snd_controls),
620 .dapm_widgets = tas2764_dapm_widgets,
621 .num_dapm_widgets = ARRAY_SIZE(tas2764_dapm_widgets),
622 .dapm_routes = tas2764_audio_map,
623 .num_dapm_routes = ARRAY_SIZE(tas2764_audio_map),
624 .idle_bias_on = 1,
625 .endianness = 1,
626 };
627
628 static const struct reg_default tas2764_reg_defaults[] = {
629 { TAS2764_PAGE, 0x00 },
630 { TAS2764_SW_RST, 0x00 },
631 { TAS2764_PWR_CTRL, 0x1a },
632 { TAS2764_DVC, 0x00 },
633 { TAS2764_CHNL_0, 0x28 },
634 { TAS2764_TDM_CFG0, 0x09 },
635 { TAS2764_TDM_CFG1, 0x02 },
636 { TAS2764_TDM_CFG2, 0x0a },
637 { TAS2764_TDM_CFG3, 0x10 },
638 { TAS2764_TDM_CFG5, 0x42 },
639 };
640
641 static const struct regmap_range_cfg tas2764_regmap_ranges[] = {
642 {
643 .range_min = 0,
644 .range_max = 1 * 128,
645 .selector_reg = TAS2764_PAGE,
646 .selector_mask = 0xff,
647 .selector_shift = 0,
648 .window_start = 0,
649 .window_len = 128,
650 },
651 };
652
tas2764_volatile_register(struct device * dev,unsigned int reg)653 static bool tas2764_volatile_register(struct device *dev, unsigned int reg)
654 {
655 switch (reg) {
656 case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4:
657 case TAS2764_INT_CLK_CFG:
658 return true;
659 default:
660 return false;
661 }
662 }
663
664 static const struct regmap_config tas2764_i2c_regmap = {
665 .reg_bits = 8,
666 .val_bits = 8,
667 .volatile_reg = tas2764_volatile_register,
668 .reg_defaults = tas2764_reg_defaults,
669 .num_reg_defaults = ARRAY_SIZE(tas2764_reg_defaults),
670 .cache_type = REGCACHE_RBTREE,
671 .ranges = tas2764_regmap_ranges,
672 .num_ranges = ARRAY_SIZE(tas2764_regmap_ranges),
673 .max_register = 1 * 128,
674 };
675
tas2764_parse_dt(struct device * dev,struct tas2764_priv * tas2764)676 static int tas2764_parse_dt(struct device *dev, struct tas2764_priv *tas2764)
677 {
678 int ret = 0;
679
680 tas2764->reset_gpio = devm_gpiod_get_optional(tas2764->dev, "reset",
681 GPIOD_OUT_HIGH);
682 if (IS_ERR(tas2764->reset_gpio)) {
683 if (PTR_ERR(tas2764->reset_gpio) == -EPROBE_DEFER) {
684 tas2764->reset_gpio = NULL;
685 return -EPROBE_DEFER;
686 }
687 }
688
689 tas2764->sdz_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
690 if (IS_ERR(tas2764->sdz_gpio)) {
691 if (PTR_ERR(tas2764->sdz_gpio) == -EPROBE_DEFER)
692 return -EPROBE_DEFER;
693
694 tas2764->sdz_gpio = NULL;
695 }
696
697 ret = fwnode_property_read_u32(dev->fwnode, "ti,imon-slot-no",
698 &tas2764->i_sense_slot);
699 if (ret)
700 tas2764->i_sense_slot = 0;
701
702 ret = fwnode_property_read_u32(dev->fwnode, "ti,vmon-slot-no",
703 &tas2764->v_sense_slot);
704 if (ret)
705 tas2764->v_sense_slot = 2;
706
707 return 0;
708 }
709
tas2764_i2c_probe(struct i2c_client * client)710 static int tas2764_i2c_probe(struct i2c_client *client)
711 {
712 struct tas2764_priv *tas2764;
713 int result;
714
715 tas2764 = devm_kzalloc(&client->dev, sizeof(struct tas2764_priv),
716 GFP_KERNEL);
717 if (!tas2764)
718 return -ENOMEM;
719
720 tas2764->dev = &client->dev;
721 tas2764->irq = client->irq;
722 i2c_set_clientdata(client, tas2764);
723 dev_set_drvdata(&client->dev, tas2764);
724
725 tas2764->regmap = devm_regmap_init_i2c(client, &tas2764_i2c_regmap);
726 if (IS_ERR(tas2764->regmap)) {
727 result = PTR_ERR(tas2764->regmap);
728 dev_err(&client->dev, "Failed to allocate register map: %d\n",
729 result);
730 return result;
731 }
732
733 if (client->dev.of_node) {
734 result = tas2764_parse_dt(&client->dev, tas2764);
735 if (result) {
736 dev_err(tas2764->dev, "%s: Failed to parse devicetree\n",
737 __func__);
738 return result;
739 }
740 }
741
742 return devm_snd_soc_register_component(tas2764->dev,
743 &soc_component_driver_tas2764,
744 tas2764_dai_driver,
745 ARRAY_SIZE(tas2764_dai_driver));
746 }
747
748 static const struct i2c_device_id tas2764_i2c_id[] = {
749 { "tas2764", 0},
750 { }
751 };
752 MODULE_DEVICE_TABLE(i2c, tas2764_i2c_id);
753
754 #if defined(CONFIG_OF)
755 static const struct of_device_id tas2764_of_match[] = {
756 { .compatible = "ti,tas2764" },
757 {},
758 };
759 MODULE_DEVICE_TABLE(of, tas2764_of_match);
760 #endif
761
762 static struct i2c_driver tas2764_i2c_driver = {
763 .driver = {
764 .name = "tas2764",
765 .of_match_table = of_match_ptr(tas2764_of_match),
766 },
767 .probe = tas2764_i2c_probe,
768 .id_table = tas2764_i2c_id,
769 };
770 module_i2c_driver(tas2764_i2c_driver);
771
772 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
773 MODULE_DESCRIPTION("TAS2764 I2C Smart Amplifier driver");
774 MODULE_LICENSE("GPL v2");
775