1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Common interrupt code for 32 and 64 bit
4 */
5 #include <linux/cpu.h>
6 #include <linux/interrupt.h>
7 #include <linux/kernel_stat.h>
8 #include <linux/of.h>
9 #include <linux/seq_file.h>
10 #include <linux/smp.h>
11 #include <linux/ftrace.h>
12 #include <linux/delay.h>
13 #include <linux/export.h>
14 #include <linux/irq.h>
15
16 #include <asm/irq_stack.h>
17 #include <asm/apic.h>
18 #include <asm/io_apic.h>
19 #include <asm/irq.h>
20 #include <asm/mce.h>
21 #include <asm/hw_irq.h>
22 #include <asm/desc.h>
23 #include <asm/traps.h>
24 #include <asm/thermal.h>
25
26 #if defined(CONFIG_X86_LOCAL_APIC) || defined(CONFIG_X86_THERMAL_VECTOR)
27 #define CREATE_TRACE_POINTS
28 #include <asm/trace/irq_vectors.h>
29 #endif
30
31 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
32 EXPORT_PER_CPU_SYMBOL(irq_stat);
33
34 atomic_t irq_err_count;
35
36 /*
37 * 'what should we do if we get a hw irq event on an illegal vector'.
38 * each architecture has to answer this themselves.
39 */
ack_bad_irq(unsigned int irq)40 void ack_bad_irq(unsigned int irq)
41 {
42 if (printk_ratelimit())
43 pr_err("unexpected IRQ trap at vector %02x\n", irq);
44
45 /*
46 * Currently unexpected vectors happen only on SMP and APIC.
47 * We _must_ ack these because every local APIC has only N
48 * irq slots per priority level, and a 'hanging, unacked' IRQ
49 * holds up an irq slot - in excessive cases (when multiple
50 * unexpected vectors occur) that might lock up the APIC
51 * completely.
52 * But only ack when the APIC is enabled -AK
53 */
54 apic_eoi();
55 }
56
57 #define irq_stats(x) (&per_cpu(irq_stat, x))
58 /*
59 * /proc/interrupts printing for arch specific interrupts
60 */
arch_show_interrupts(struct seq_file * p,int prec)61 int arch_show_interrupts(struct seq_file *p, int prec)
62 {
63 int j;
64
65 seq_printf(p, "%*s: ", prec, "NMI");
66 for_each_online_cpu(j)
67 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
68 seq_puts(p, " Non-maskable interrupts\n");
69 #ifdef CONFIG_X86_LOCAL_APIC
70 seq_printf(p, "%*s: ", prec, "LOC");
71 for_each_online_cpu(j)
72 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
73 seq_puts(p, " Local timer interrupts\n");
74
75 seq_printf(p, "%*s: ", prec, "SPU");
76 for_each_online_cpu(j)
77 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
78 seq_puts(p, " Spurious interrupts\n");
79 seq_printf(p, "%*s: ", prec, "PMI");
80 for_each_online_cpu(j)
81 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
82 seq_puts(p, " Performance monitoring interrupts\n");
83 seq_printf(p, "%*s: ", prec, "IWI");
84 for_each_online_cpu(j)
85 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
86 seq_puts(p, " IRQ work interrupts\n");
87 seq_printf(p, "%*s: ", prec, "RTR");
88 for_each_online_cpu(j)
89 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
90 seq_puts(p, " APIC ICR read retries\n");
91 if (x86_platform_ipi_callback) {
92 seq_printf(p, "%*s: ", prec, "PLT");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
95 seq_puts(p, " Platform interrupts\n");
96 }
97 #endif
98 #ifdef CONFIG_SMP
99 seq_printf(p, "%*s: ", prec, "RES");
100 for_each_online_cpu(j)
101 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
102 seq_puts(p, " Rescheduling interrupts\n");
103 seq_printf(p, "%*s: ", prec, "CAL");
104 for_each_online_cpu(j)
105 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
106 seq_puts(p, " Function call interrupts\n");
107 seq_printf(p, "%*s: ", prec, "TLB");
108 for_each_online_cpu(j)
109 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
110 seq_puts(p, " TLB shootdowns\n");
111 #endif
112 #ifdef CONFIG_X86_THERMAL_VECTOR
113 seq_printf(p, "%*s: ", prec, "TRM");
114 for_each_online_cpu(j)
115 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
116 seq_puts(p, " Thermal event interrupts\n");
117 #endif
118 #ifdef CONFIG_X86_MCE_THRESHOLD
119 seq_printf(p, "%*s: ", prec, "THR");
120 for_each_online_cpu(j)
121 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
122 seq_puts(p, " Threshold APIC interrupts\n");
123 #endif
124 #ifdef CONFIG_X86_MCE_AMD
125 seq_printf(p, "%*s: ", prec, "DFR");
126 for_each_online_cpu(j)
127 seq_printf(p, "%10u ", irq_stats(j)->irq_deferred_error_count);
128 seq_puts(p, " Deferred Error APIC interrupts\n");
129 #endif
130 #ifdef CONFIG_X86_MCE
131 seq_printf(p, "%*s: ", prec, "MCE");
132 for_each_online_cpu(j)
133 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
134 seq_puts(p, " Machine check exceptions\n");
135 seq_printf(p, "%*s: ", prec, "MCP");
136 for_each_online_cpu(j)
137 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
138 seq_puts(p, " Machine check polls\n");
139 #endif
140 #ifdef CONFIG_X86_HV_CALLBACK_VECTOR
141 if (test_bit(HYPERVISOR_CALLBACK_VECTOR, system_vectors)) {
142 seq_printf(p, "%*s: ", prec, "HYP");
143 for_each_online_cpu(j)
144 seq_printf(p, "%10u ",
145 irq_stats(j)->irq_hv_callback_count);
146 seq_puts(p, " Hypervisor callback interrupts\n");
147 }
148 #endif
149 #if IS_ENABLED(CONFIG_HYPERV)
150 if (test_bit(HYPERV_REENLIGHTENMENT_VECTOR, system_vectors)) {
151 seq_printf(p, "%*s: ", prec, "HRE");
152 for_each_online_cpu(j)
153 seq_printf(p, "%10u ",
154 irq_stats(j)->irq_hv_reenlightenment_count);
155 seq_puts(p, " Hyper-V reenlightenment interrupts\n");
156 }
157 if (test_bit(HYPERV_STIMER0_VECTOR, system_vectors)) {
158 seq_printf(p, "%*s: ", prec, "HVS");
159 for_each_online_cpu(j)
160 seq_printf(p, "%10u ",
161 irq_stats(j)->hyperv_stimer0_count);
162 seq_puts(p, " Hyper-V stimer0 interrupts\n");
163 }
164 #endif
165 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
166 #if defined(CONFIG_X86_IO_APIC)
167 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
168 #endif
169 #ifdef CONFIG_HAVE_KVM
170 seq_printf(p, "%*s: ", prec, "PIN");
171 for_each_online_cpu(j)
172 seq_printf(p, "%10u ", irq_stats(j)->kvm_posted_intr_ipis);
173 seq_puts(p, " Posted-interrupt notification event\n");
174
175 seq_printf(p, "%*s: ", prec, "NPI");
176 for_each_online_cpu(j)
177 seq_printf(p, "%10u ",
178 irq_stats(j)->kvm_posted_intr_nested_ipis);
179 seq_puts(p, " Nested posted-interrupt event\n");
180
181 seq_printf(p, "%*s: ", prec, "PIW");
182 for_each_online_cpu(j)
183 seq_printf(p, "%10u ",
184 irq_stats(j)->kvm_posted_intr_wakeup_ipis);
185 seq_puts(p, " Posted-interrupt wakeup event\n");
186 #endif
187 return 0;
188 }
189
190 /*
191 * /proc/stat helpers
192 */
arch_irq_stat_cpu(unsigned int cpu)193 u64 arch_irq_stat_cpu(unsigned int cpu)
194 {
195 u64 sum = irq_stats(cpu)->__nmi_count;
196
197 #ifdef CONFIG_X86_LOCAL_APIC
198 sum += irq_stats(cpu)->apic_timer_irqs;
199 sum += irq_stats(cpu)->irq_spurious_count;
200 sum += irq_stats(cpu)->apic_perf_irqs;
201 sum += irq_stats(cpu)->apic_irq_work_irqs;
202 sum += irq_stats(cpu)->icr_read_retry_count;
203 if (x86_platform_ipi_callback)
204 sum += irq_stats(cpu)->x86_platform_ipis;
205 #endif
206 #ifdef CONFIG_SMP
207 sum += irq_stats(cpu)->irq_resched_count;
208 sum += irq_stats(cpu)->irq_call_count;
209 #endif
210 #ifdef CONFIG_X86_THERMAL_VECTOR
211 sum += irq_stats(cpu)->irq_thermal_count;
212 #endif
213 #ifdef CONFIG_X86_MCE_THRESHOLD
214 sum += irq_stats(cpu)->irq_threshold_count;
215 #endif
216 #ifdef CONFIG_X86_HV_CALLBACK_VECTOR
217 sum += irq_stats(cpu)->irq_hv_callback_count;
218 #endif
219 #if IS_ENABLED(CONFIG_HYPERV)
220 sum += irq_stats(cpu)->irq_hv_reenlightenment_count;
221 sum += irq_stats(cpu)->hyperv_stimer0_count;
222 #endif
223 #ifdef CONFIG_X86_MCE
224 sum += per_cpu(mce_exception_count, cpu);
225 sum += per_cpu(mce_poll_count, cpu);
226 #endif
227 return sum;
228 }
229
arch_irq_stat(void)230 u64 arch_irq_stat(void)
231 {
232 u64 sum = atomic_read(&irq_err_count);
233 return sum;
234 }
235
handle_irq(struct irq_desc * desc,struct pt_regs * regs)236 static __always_inline void handle_irq(struct irq_desc *desc,
237 struct pt_regs *regs)
238 {
239 if (IS_ENABLED(CONFIG_X86_64))
240 generic_handle_irq_desc(desc);
241 else
242 __handle_irq(desc, regs);
243 }
244
245 /*
246 * common_interrupt() handles all normal device IRQ's (the special SMP
247 * cross-CPU interrupts have their own entry points).
248 */
DEFINE_IDTENTRY_IRQ(common_interrupt)249 DEFINE_IDTENTRY_IRQ(common_interrupt)
250 {
251 struct pt_regs *old_regs = set_irq_regs(regs);
252 struct irq_desc *desc;
253
254 /* entry code tells RCU that we're not quiescent. Check it. */
255 RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU");
256
257 desc = __this_cpu_read(vector_irq[vector]);
258 if (likely(!IS_ERR_OR_NULL(desc))) {
259 handle_irq(desc, regs);
260 } else {
261 apic_eoi();
262
263 if (desc == VECTOR_UNUSED) {
264 pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n",
265 __func__, smp_processor_id(),
266 vector);
267 } else {
268 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
269 }
270 }
271
272 set_irq_regs(old_regs);
273 }
274
275 #ifdef CONFIG_X86_LOCAL_APIC
276 /* Function pointer for generic interrupt vector handling */
277 void (*x86_platform_ipi_callback)(void) = NULL;
278 /*
279 * Handler for X86_PLATFORM_IPI_VECTOR.
280 */
DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)281 DEFINE_IDTENTRY_SYSVEC(sysvec_x86_platform_ipi)
282 {
283 struct pt_regs *old_regs = set_irq_regs(regs);
284
285 apic_eoi();
286 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
287 inc_irq_stat(x86_platform_ipis);
288 if (x86_platform_ipi_callback)
289 x86_platform_ipi_callback();
290 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
291 set_irq_regs(old_regs);
292 }
293 #endif
294
295 #ifdef CONFIG_HAVE_KVM
dummy_handler(void)296 static void dummy_handler(void) {}
297 static void (*kvm_posted_intr_wakeup_handler)(void) = dummy_handler;
298
kvm_set_posted_intr_wakeup_handler(void (* handler)(void))299 void kvm_set_posted_intr_wakeup_handler(void (*handler)(void))
300 {
301 if (handler)
302 kvm_posted_intr_wakeup_handler = handler;
303 else {
304 kvm_posted_intr_wakeup_handler = dummy_handler;
305 synchronize_rcu();
306 }
307 }
308 EXPORT_SYMBOL_GPL(kvm_set_posted_intr_wakeup_handler);
309
310 /*
311 * Handler for POSTED_INTERRUPT_VECTOR.
312 */
DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)313 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_ipi)
314 {
315 apic_eoi();
316 inc_irq_stat(kvm_posted_intr_ipis);
317 }
318
319 /*
320 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
321 */
DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)322 DEFINE_IDTENTRY_SYSVEC(sysvec_kvm_posted_intr_wakeup_ipi)
323 {
324 apic_eoi();
325 inc_irq_stat(kvm_posted_intr_wakeup_ipis);
326 kvm_posted_intr_wakeup_handler();
327 }
328
329 /*
330 * Handler for POSTED_INTERRUPT_NESTED_VECTOR.
331 */
DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)332 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_kvm_posted_intr_nested_ipi)
333 {
334 apic_eoi();
335 inc_irq_stat(kvm_posted_intr_nested_ipis);
336 }
337 #endif
338
339
340 #ifdef CONFIG_HOTPLUG_CPU
341 /* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
fixup_irqs(void)342 void fixup_irqs(void)
343 {
344 unsigned int irr, vector;
345 struct irq_desc *desc;
346 struct irq_data *data;
347 struct irq_chip *chip;
348
349 irq_migrate_all_off_this_cpu();
350
351 /*
352 * We can remove mdelay() and then send spurious interrupts to
353 * new cpu targets for all the irqs that were handled previously by
354 * this cpu. While it works, I have seen spurious interrupt messages
355 * (nothing wrong but still...).
356 *
357 * So for now, retain mdelay(1) and check the IRR and then send those
358 * interrupts to new targets as this cpu is already offlined...
359 */
360 mdelay(1);
361
362 /*
363 * We can walk the vector array of this cpu without holding
364 * vector_lock because the cpu is already marked !online, so
365 * nothing else will touch it.
366 */
367 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
368 if (IS_ERR_OR_NULL(__this_cpu_read(vector_irq[vector])))
369 continue;
370
371 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
372 if (irr & (1 << (vector % 32))) {
373 desc = __this_cpu_read(vector_irq[vector]);
374
375 raw_spin_lock(&desc->lock);
376 data = irq_desc_get_irq_data(desc);
377 chip = irq_data_get_irq_chip(data);
378 if (chip->irq_retrigger) {
379 chip->irq_retrigger(data);
380 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
381 }
382 raw_spin_unlock(&desc->lock);
383 }
384 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
385 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED);
386 }
387 }
388 #endif
389
390 #ifdef CONFIG_X86_THERMAL_VECTOR
smp_thermal_vector(void)391 static void smp_thermal_vector(void)
392 {
393 if (x86_thermal_enabled())
394 intel_thermal_interrupt();
395 else
396 pr_err("CPU%d: Unexpected LVT thermal interrupt!\n",
397 smp_processor_id());
398 }
399
DEFINE_IDTENTRY_SYSVEC(sysvec_thermal)400 DEFINE_IDTENTRY_SYSVEC(sysvec_thermal)
401 {
402 trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
403 inc_irq_stat(irq_thermal_count);
404 smp_thermal_vector();
405 trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
406 apic_eoi();
407 }
408 #endif
409