xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/dc.h (revision d32fd6bb9f2bc8178cdd65ebec1ad670a8bfa241)
1  /*
2   * Copyright 2012-2023 Advanced Micro Devices, Inc.
3   *
4   * Permission is hereby granted, free of charge, to any person obtaining a
5   * copy of this software and associated documentation files (the "Software"),
6   * to deal in the Software without restriction, including without limitation
7   * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8   * and/or sell copies of the Software, and to permit persons to whom the
9   * Software is furnished to do so, subject to the following conditions:
10   *
11   * The above copyright notice and this permission notice shall be included in
12   * all copies or substantial portions of the Software.
13   *
14   * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15   * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16   * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17   * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18   * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19   * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20   * OTHER DEALINGS IN THE SOFTWARE.
21   *
22   * Authors: AMD
23   *
24   */
25  
26  #ifndef DC_INTERFACE_H_
27  #define DC_INTERFACE_H_
28  
29  #include "dc_types.h"
30  #include "grph_object_defs.h"
31  #include "logger_types.h"
32  #include "hdcp_msg_types.h"
33  #include "gpio_types.h"
34  #include "link_service_types.h"
35  #include "grph_object_ctrl_defs.h"
36  #include <inc/hw/opp.h>
37  
38  #include "inc/hw_sequencer.h"
39  #include "inc/compressor.h"
40  #include "inc/hw/dmcu.h"
41  #include "dml/display_mode_lib.h"
42  
43  struct abm_save_restore;
44  
45  /* forward declaration */
46  struct aux_payload;
47  struct set_config_cmd_payload;
48  struct dmub_notification;
49  
50  #define DC_VER "3.2.247"
51  
52  #define MAX_SURFACES 4
53  #define MAX_PLANES 6
54  #define MAX_STREAMS 6
55  #define MIN_VIEWPORT_SIZE 12
56  #define MAX_NUM_EDP 2
57  
58  /* Display Core Interfaces */
59  struct dc_versions {
60  	const char *dc_ver;
61  	struct dmcu_version dmcu_version;
62  };
63  
64  enum dp_protocol_version {
65  	DP_VERSION_1_4 = 0,
66  	DP_VERSION_2_1,
67  	DP_VERSION_UNKNOWN,
68  };
69  
70  enum dc_plane_type {
71  	DC_PLANE_TYPE_INVALID,
72  	DC_PLANE_TYPE_DCE_RGB,
73  	DC_PLANE_TYPE_DCE_UNDERLAY,
74  	DC_PLANE_TYPE_DCN_UNIVERSAL,
75  };
76  
77  // Sizes defined as multiples of 64KB
78  enum det_size {
79  	DET_SIZE_DEFAULT = 0,
80  	DET_SIZE_192KB = 3,
81  	DET_SIZE_256KB = 4,
82  	DET_SIZE_320KB = 5,
83  	DET_SIZE_384KB = 6
84  };
85  
86  
87  struct dc_plane_cap {
88  	enum dc_plane_type type;
89  	uint32_t per_pixel_alpha : 1;
90  	struct {
91  		uint32_t argb8888 : 1;
92  		uint32_t nv12 : 1;
93  		uint32_t fp16 : 1;
94  		uint32_t p010 : 1;
95  		uint32_t ayuv : 1;
96  	} pixel_format_support;
97  	// max upscaling factor x1000
98  	// upscaling factors are always >= 1
99  	// for example, 1080p -> 8K is 4.0, or 4000 raw value
100  	struct {
101  		uint32_t argb8888;
102  		uint32_t nv12;
103  		uint32_t fp16;
104  	} max_upscale_factor;
105  	// max downscale factor x1000
106  	// downscale factors are always <= 1
107  	// for example, 8K -> 1080p is 0.25, or 250 raw value
108  	struct {
109  		uint32_t argb8888;
110  		uint32_t nv12;
111  		uint32_t fp16;
112  	} max_downscale_factor;
113  	// minimal width/height
114  	uint32_t min_width;
115  	uint32_t min_height;
116  };
117  
118  /**
119   * DOC: color-management-caps
120   *
121   * **Color management caps (DPP and MPC)**
122   *
123   * Modules/color calculates various color operations which are translated to
124   * abstracted HW. DCE 5-12 had almost no important changes, but starting with
125   * DCN1, every new generation comes with fairly major differences in color
126   * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can
127   * decide mapping to HW block based on logical capabilities.
128   */
129  
130  /**
131   * struct rom_curve_caps - predefined transfer function caps for degamma and regamma
132   * @srgb: RGB color space transfer func
133   * @bt2020: BT.2020 transfer func
134   * @gamma2_2: standard gamma
135   * @pq: perceptual quantizer transfer function
136   * @hlg: hybrid log–gamma transfer function
137   */
138  struct rom_curve_caps {
139  	uint16_t srgb : 1;
140  	uint16_t bt2020 : 1;
141  	uint16_t gamma2_2 : 1;
142  	uint16_t pq : 1;
143  	uint16_t hlg : 1;
144  };
145  
146  /**
147   * struct dpp_color_caps - color pipeline capabilities for display pipe and
148   * plane blocks
149   *
150   * @dcn_arch: all DCE generations treated the same
151   * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs,
152   * just plain 256-entry lookup
153   * @icsc: input color space conversion
154   * @dgam_ram: programmable degamma LUT
155   * @post_csc: post color space conversion, before gamut remap
156   * @gamma_corr: degamma correction
157   * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared
158   * with MPC by setting mpc:shared_3d_lut flag
159   * @ogam_ram: programmable out/blend gamma LUT
160   * @ocsc: output color space conversion
161   * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes
162   * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT
163   * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
164   *
165   * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order)
166   */
167  struct dpp_color_caps {
168  	uint16_t dcn_arch : 1;
169  	uint16_t input_lut_shared : 1;
170  	uint16_t icsc : 1;
171  	uint16_t dgam_ram : 1;
172  	uint16_t post_csc : 1;
173  	uint16_t gamma_corr : 1;
174  	uint16_t hw_3d_lut : 1;
175  	uint16_t ogam_ram : 1;
176  	uint16_t ocsc : 1;
177  	uint16_t dgam_rom_for_yuv : 1;
178  	struct rom_curve_caps dgam_rom_caps;
179  	struct rom_curve_caps ogam_rom_caps;
180  };
181  
182  /**
183   * struct mpc_color_caps - color pipeline capabilities for multiple pipe and
184   * plane combined blocks
185   *
186   * @gamut_remap: color transformation matrix
187   * @ogam_ram: programmable out gamma LUT
188   * @ocsc: output color space conversion matrix
189   * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT
190   * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single
191   * instance
192   * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT
193   */
194  struct mpc_color_caps {
195  	uint16_t gamut_remap : 1;
196  	uint16_t ogam_ram : 1;
197  	uint16_t ocsc : 1;
198  	uint16_t num_3dluts : 3;
199  	uint16_t shared_3d_lut:1;
200  	struct rom_curve_caps ogam_rom_caps;
201  };
202  
203  /**
204   * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks
205   * @dpp: color pipes caps for DPP
206   * @mpc: color pipes caps for MPC
207   */
208  struct dc_color_caps {
209  	struct dpp_color_caps dpp;
210  	struct mpc_color_caps mpc;
211  };
212  
213  struct dc_dmub_caps {
214  	bool psr;
215  	bool mclk_sw;
216  	bool subvp_psr;
217  	bool gecc_enable;
218  };
219  
220  struct dc_caps {
221  	uint32_t max_streams;
222  	uint32_t max_links;
223  	uint32_t max_audios;
224  	uint32_t max_slave_planes;
225  	uint32_t max_slave_yuv_planes;
226  	uint32_t max_slave_rgb_planes;
227  	uint32_t max_planes;
228  	uint32_t max_downscale_ratio;
229  	uint32_t i2c_speed_in_khz;
230  	uint32_t i2c_speed_in_khz_hdcp;
231  	uint32_t dmdata_alloc_size;
232  	unsigned int max_cursor_size;
233  	unsigned int max_video_width;
234  	/*
235  	 * max video plane width that can be safely assumed to be always
236  	 * supported by single DPP pipe.
237  	 */
238  	unsigned int max_optimizable_video_width;
239  	unsigned int min_horizontal_blanking_period;
240  	int linear_pitch_alignment;
241  	bool dcc_const_color;
242  	bool dynamic_audio;
243  	bool is_apu;
244  	bool dual_link_dvi;
245  	bool post_blend_color_processing;
246  	bool force_dp_tps4_for_cp2520;
247  	bool disable_dp_clk_share;
248  	bool psp_setup_panel_mode;
249  	bool extended_aux_timeout_support;
250  	bool dmcub_support;
251  	bool zstate_support;
252  	uint32_t num_of_internal_disp;
253  	enum dp_protocol_version max_dp_protocol_version;
254  	unsigned int mall_size_per_mem_channel;
255  	unsigned int mall_size_total;
256  	unsigned int cursor_cache_size;
257  	struct dc_plane_cap planes[MAX_PLANES];
258  	struct dc_color_caps color;
259  	struct dc_dmub_caps dmub_caps;
260  	bool dp_hpo;
261  	bool dp_hdmi21_pcon_support;
262  	bool edp_dsc_support;
263  	bool vbios_lttpr_aware;
264  	bool vbios_lttpr_enable;
265  	uint32_t max_otg_num;
266  	uint32_t max_cab_allocation_bytes;
267  	uint32_t cache_line_size;
268  	uint32_t cache_num_ways;
269  	uint16_t subvp_fw_processing_delay_us;
270  	uint8_t subvp_drr_max_vblank_margin_us;
271  	uint16_t subvp_prefetch_end_to_mall_start_us;
272  	uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height
273  	uint16_t subvp_pstate_allow_width_us;
274  	uint16_t subvp_vertical_int_margin_us;
275  	bool seamless_odm;
276  	uint32_t max_v_total;
277  	uint8_t subvp_drr_vblank_start_margin_us;
278  };
279  
280  struct dc_bug_wa {
281  	bool no_connect_phy_config;
282  	bool dedcn20_305_wa;
283  	bool skip_clock_update;
284  	bool lt_early_cr_pattern;
285  	struct {
286  		uint8_t uclk : 1;
287  		uint8_t fclk : 1;
288  		uint8_t dcfclk : 1;
289  		uint8_t dcfclk_ds: 1;
290  	} clock_update_disable_mask;
291  };
292  struct dc_dcc_surface_param {
293  	struct dc_size surface_size;
294  	enum surface_pixel_format format;
295  	enum swizzle_mode_values swizzle_mode;
296  	enum dc_scan_direction scan;
297  };
298  
299  struct dc_dcc_setting {
300  	unsigned int max_compressed_blk_size;
301  	unsigned int max_uncompressed_blk_size;
302  	bool independent_64b_blks;
303  	//These bitfields to be used starting with DCN
304  	struct {
305  		uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN (the worst compression case)
306  		uint32_t dcc_128_128_uncontrained : 1;  //available in ASICs before DCN
307  		uint32_t dcc_256_128_128 : 1;		//available starting with DCN
308  		uint32_t dcc_256_256_unconstrained : 1;  //available in ASICs before DCN (the best compression case)
309  	} dcc_controls;
310  };
311  
312  struct dc_surface_dcc_cap {
313  	union {
314  		struct {
315  			struct dc_dcc_setting rgb;
316  		} grph;
317  
318  		struct {
319  			struct dc_dcc_setting luma;
320  			struct dc_dcc_setting chroma;
321  		} video;
322  	};
323  
324  	bool capable;
325  	bool const_color_support;
326  };
327  
328  struct dc_static_screen_params {
329  	struct {
330  		bool force_trigger;
331  		bool cursor_update;
332  		bool surface_update;
333  		bool overlay_update;
334  	} triggers;
335  	unsigned int num_frames;
336  };
337  
338  
339  /* Surface update type is used by dc_update_surfaces_and_stream
340   * The update type is determined at the very beginning of the function based
341   * on parameters passed in and decides how much programming (or updating) is
342   * going to be done during the call.
343   *
344   * UPDATE_TYPE_FAST is used for really fast updates that do not require much
345   * logical calculations or hardware register programming. This update MUST be
346   * ISR safe on windows. Currently fast update will only be used to flip surface
347   * address.
348   *
349   * UPDATE_TYPE_MED is used for slower updates which require significant hw
350   * re-programming however do not affect bandwidth consumption or clock
351   * requirements. At present, this is the level at which front end updates
352   * that do not require us to run bw_calcs happen. These are in/out transfer func
353   * updates, viewport offset changes, recout size changes and pixel depth changes.
354   * This update can be done at ISR, but we want to minimize how often this happens.
355   *
356   * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our
357   * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front
358   * end related. Any time viewport dimensions, recout dimensions, scaling ratios or
359   * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do
360   * a full update. This cannot be done at ISR level and should be a rare event.
361   * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting
362   * underscan we don't expect to see this call at all.
363   */
364  
365  enum surface_update_type {
366  	UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */
367  	UPDATE_TYPE_MED,  /* ISR safe, most of programming needed, no bw/clk change*/
368  	UPDATE_TYPE_FULL, /* may need to shuffle resources */
369  };
370  
371  /* Forward declaration*/
372  struct dc;
373  struct dc_plane_state;
374  struct dc_state;
375  
376  
377  struct dc_cap_funcs {
378  	bool (*get_dcc_compression_cap)(const struct dc *dc,
379  			const struct dc_dcc_surface_param *input,
380  			struct dc_surface_dcc_cap *output);
381  };
382  
383  struct link_training_settings;
384  
385  union allow_lttpr_non_transparent_mode {
386  	struct {
387  		bool DP1_4A : 1;
388  		bool DP2_0 : 1;
389  	} bits;
390  	unsigned char raw;
391  };
392  
393  /* Structure to hold configuration flags set by dm at dc creation. */
394  struct dc_config {
395  	bool gpu_vm_support;
396  	bool disable_disp_pll_sharing;
397  	bool fbc_support;
398  	bool disable_fractional_pwm;
399  	bool allow_seamless_boot_optimization;
400  	bool seamless_boot_edp_requested;
401  	bool edp_not_connected;
402  	bool edp_no_power_sequencing;
403  	bool force_enum_edp;
404  	bool forced_clocks;
405  	union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode;
406  	bool multi_mon_pp_mclk_switch;
407  	bool disable_dmcu;
408  	bool enable_4to1MPC;
409  	bool enable_windowed_mpo_odm;
410  	bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520
411  	uint32_t allow_edp_hotplug_detection;
412  	bool clamp_min_dcfclk;
413  	uint64_t vblank_alignment_dto_params;
414  	uint8_t  vblank_alignment_max_frame_time_diff;
415  	bool is_asymmetric_memory;
416  	bool is_single_rank_dimm;
417  	bool is_vmin_only_asic;
418  	bool use_pipe_ctx_sync_logic;
419  	bool ignore_dpref_ss;
420  	bool enable_mipi_converter_optimization;
421  	bool use_default_clock_table;
422  	bool force_bios_enable_lttpr;
423  	uint8_t force_bios_fixed_vs;
424  	int sdpif_request_limit_words_per_umc;
425  	bool use_old_fixed_vs_sequence;
426  	bool dc_mode_clk_limit_support;
427  };
428  
429  enum visual_confirm {
430  	VISUAL_CONFIRM_DISABLE = 0,
431  	VISUAL_CONFIRM_SURFACE = 1,
432  	VISUAL_CONFIRM_HDR = 2,
433  	VISUAL_CONFIRM_MPCTREE = 4,
434  	VISUAL_CONFIRM_PSR = 5,
435  	VISUAL_CONFIRM_SWAPCHAIN = 6,
436  	VISUAL_CONFIRM_FAMS = 7,
437  	VISUAL_CONFIRM_SWIZZLE = 9,
438  	VISUAL_CONFIRM_REPLAY = 12,
439  	VISUAL_CONFIRM_SUBVP = 14,
440  	VISUAL_CONFIRM_MCLK_SWITCH = 16,
441  };
442  
443  enum dc_psr_power_opts {
444  	psr_power_opt_invalid = 0x0,
445  	psr_power_opt_smu_opt_static_screen = 0x1,
446  	psr_power_opt_z10_static_screen = 0x10,
447  	psr_power_opt_ds_disable_allow = 0x100,
448  };
449  
450  enum dml_hostvm_override_opts {
451  	DML_HOSTVM_NO_OVERRIDE = 0x0,
452  	DML_HOSTVM_OVERRIDE_FALSE = 0x1,
453  	DML_HOSTVM_OVERRIDE_TRUE = 0x2,
454  };
455  
456  enum dcc_option {
457  	DCC_ENABLE = 0,
458  	DCC_DISABLE = 1,
459  	DCC_HALF_REQ_DISALBE = 2,
460  };
461  
462  /**
463   * enum pipe_split_policy - Pipe split strategy supported by DCN
464   *
465   * This enum is used to define the pipe split policy supported by DCN. By
466   * default, DC favors MPC_SPLIT_DYNAMIC.
467   */
468  enum pipe_split_policy {
469  	/**
470  	 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the
471  	 * pipe in order to bring the best trade-off between performance and
472  	 * power consumption. This is the recommended option.
473  	 */
474  	MPC_SPLIT_DYNAMIC = 0,
475  
476  	/**
477  	 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not
478  	 * try any sort of split optimization.
479  	 */
480  	MPC_SPLIT_AVOID = 1,
481  
482  	/**
483  	 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to
484  	 * optimize the pipe utilization when using a single display; if the
485  	 * user connects to a second display, DC will avoid pipe split.
486  	 */
487  	MPC_SPLIT_AVOID_MULT_DISP = 2,
488  };
489  
490  enum wm_report_mode {
491  	WM_REPORT_DEFAULT = 0,
492  	WM_REPORT_OVERRIDE = 1,
493  };
494  enum dtm_pstate{
495  	dtm_level_p0 = 0,/*highest voltage*/
496  	dtm_level_p1,
497  	dtm_level_p2,
498  	dtm_level_p3,
499  	dtm_level_p4,/*when active_display_count = 0*/
500  };
501  
502  enum dcn_pwr_state {
503  	DCN_PWR_STATE_UNKNOWN = -1,
504  	DCN_PWR_STATE_MISSION_MODE = 0,
505  	DCN_PWR_STATE_LOW_POWER = 3,
506  };
507  
508  enum dcn_zstate_support_state {
509  	DCN_ZSTATE_SUPPORT_UNKNOWN,
510  	DCN_ZSTATE_SUPPORT_ALLOW,
511  	DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY,
512  	DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY,
513  	DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY,
514  	DCN_ZSTATE_SUPPORT_DISALLOW,
515  };
516  
517  /*
518   * struct dc_clocks - DC pipe clocks
519   *
520   * For any clocks that may differ per pipe only the max is stored in this
521   * structure
522   */
523  struct dc_clocks {
524  	int dispclk_khz;
525  	int actual_dispclk_khz;
526  	int dppclk_khz;
527  	int actual_dppclk_khz;
528  	int disp_dpp_voltage_level_khz;
529  	int dcfclk_khz;
530  	int socclk_khz;
531  	int dcfclk_deep_sleep_khz;
532  	int fclk_khz;
533  	int phyclk_khz;
534  	int dramclk_khz;
535  	bool p_state_change_support;
536  	enum dcn_zstate_support_state zstate_support;
537  	bool dtbclk_en;
538  	int ref_dtbclk_khz;
539  	bool fclk_p_state_change_support;
540  	enum dcn_pwr_state pwr_state;
541  	/*
542  	 * Elements below are not compared for the purposes of
543  	 * optimization required
544  	 */
545  	bool prev_p_state_change_support;
546  	bool fclk_prev_p_state_change_support;
547  	int num_ways;
548  
549  	/*
550  	 * @fw_based_mclk_switching
551  	 *
552  	 * DC has a mechanism that leverage the variable refresh rate to switch
553  	 * memory clock in cases that we have a large latency to achieve the
554  	 * memory clock change and a short vblank window. DC has some
555  	 * requirements to enable this feature, and this field describes if the
556  	 * system support or not such a feature.
557  	 */
558  	bool fw_based_mclk_switching;
559  	bool fw_based_mclk_switching_shut_down;
560  	int prev_num_ways;
561  	enum dtm_pstate dtm_level;
562  	int max_supported_dppclk_khz;
563  	int max_supported_dispclk_khz;
564  	int bw_dppclk_khz; /*a copy of dppclk_khz*/
565  	int bw_dispclk_khz;
566  };
567  
568  struct dc_bw_validation_profile {
569  	bool enable;
570  
571  	unsigned long long total_ticks;
572  	unsigned long long voltage_level_ticks;
573  	unsigned long long watermark_ticks;
574  	unsigned long long rq_dlg_ticks;
575  
576  	unsigned long long total_count;
577  	unsigned long long skip_fast_count;
578  	unsigned long long skip_pass_count;
579  	unsigned long long skip_fail_count;
580  };
581  
582  #define BW_VAL_TRACE_SETUP() \
583  		unsigned long long end_tick = 0; \
584  		unsigned long long voltage_level_tick = 0; \
585  		unsigned long long watermark_tick = 0; \
586  		unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \
587  				dm_get_timestamp(dc->ctx) : 0
588  
589  #define BW_VAL_TRACE_COUNT() \
590  		if (dc->debug.bw_val_profile.enable) \
591  			dc->debug.bw_val_profile.total_count++
592  
593  #define BW_VAL_TRACE_SKIP(status) \
594  		if (dc->debug.bw_val_profile.enable) { \
595  			if (!voltage_level_tick) \
596  				voltage_level_tick = dm_get_timestamp(dc->ctx); \
597  			dc->debug.bw_val_profile.skip_ ## status ## _count++; \
598  		}
599  
600  #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \
601  		if (dc->debug.bw_val_profile.enable) \
602  			voltage_level_tick = dm_get_timestamp(dc->ctx)
603  
604  #define BW_VAL_TRACE_END_WATERMARKS() \
605  		if (dc->debug.bw_val_profile.enable) \
606  			watermark_tick = dm_get_timestamp(dc->ctx)
607  
608  #define BW_VAL_TRACE_FINISH() \
609  		if (dc->debug.bw_val_profile.enable) { \
610  			end_tick = dm_get_timestamp(dc->ctx); \
611  			dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \
612  			dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \
613  			if (watermark_tick) { \
614  				dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \
615  				dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \
616  			} \
617  		}
618  
619  union mem_low_power_enable_options {
620  	struct {
621  		bool vga: 1;
622  		bool i2c: 1;
623  		bool dmcu: 1;
624  		bool dscl: 1;
625  		bool cm: 1;
626  		bool mpc: 1;
627  		bool optc: 1;
628  		bool vpg: 1;
629  		bool afmt: 1;
630  	} bits;
631  	uint32_t u32All;
632  };
633  
634  union root_clock_optimization_options {
635  	struct {
636  		bool dpp: 1;
637  		bool dsc: 1;
638  		bool hdmistream: 1;
639  		bool hdmichar: 1;
640  		bool dpstream: 1;
641  		bool symclk32_se: 1;
642  		bool symclk32_le: 1;
643  		bool symclk_fe: 1;
644  		bool physymclk: 1;
645  		bool dpiasymclk: 1;
646  		uint32_t reserved: 22;
647  	} bits;
648  	uint32_t u32All;
649  };
650  
651  union dpia_debug_options {
652  	struct {
653  		uint32_t disable_dpia:1; /* bit 0 */
654  		uint32_t force_non_lttpr:1; /* bit 1 */
655  		uint32_t extend_aux_rd_interval:1; /* bit 2 */
656  		uint32_t disable_mst_dsc_work_around:1; /* bit 3 */
657  		uint32_t enable_force_tbt3_work_around:1; /* bit 4 */
658  		uint32_t reserved:27;
659  	} bits;
660  	uint32_t raw;
661  };
662  
663  /* AUX wake work around options
664   * 0: enable/disable work around
665   * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS
666   * 15-2: reserved
667   * 31-16: timeout in ms
668   */
669  union aux_wake_wa_options {
670  	struct {
671  		uint32_t enable_wa : 1;
672  		uint32_t use_default_timeout : 1;
673  		uint32_t rsvd: 14;
674  		uint32_t timeout_ms : 16;
675  	} bits;
676  	uint32_t raw;
677  };
678  
679  struct dc_debug_data {
680  	uint32_t ltFailCount;
681  	uint32_t i2cErrorCount;
682  	uint32_t auxErrorCount;
683  };
684  
685  struct dc_phy_addr_space_config {
686  	struct {
687  		uint64_t start_addr;
688  		uint64_t end_addr;
689  		uint64_t fb_top;
690  		uint64_t fb_offset;
691  		uint64_t fb_base;
692  		uint64_t agp_top;
693  		uint64_t agp_bot;
694  		uint64_t agp_base;
695  	} system_aperture;
696  
697  	struct {
698  		uint64_t page_table_start_addr;
699  		uint64_t page_table_end_addr;
700  		uint64_t page_table_base_addr;
701  		bool base_addr_is_mc_addr;
702  	} gart_config;
703  
704  	bool valid;
705  	bool is_hvm_enabled;
706  	uint64_t page_table_default_page_addr;
707  };
708  
709  struct dc_virtual_addr_space_config {
710  	uint64_t	page_table_base_addr;
711  	uint64_t	page_table_start_addr;
712  	uint64_t	page_table_end_addr;
713  	uint32_t	page_table_block_size_in_bytes;
714  	uint8_t		page_table_depth; // 1 = 1 level, 2 = 2 level, etc.  0 = invalid
715  };
716  
717  struct dc_bounding_box_overrides {
718  	int sr_exit_time_ns;
719  	int sr_enter_plus_exit_time_ns;
720  	int sr_exit_z8_time_ns;
721  	int sr_enter_plus_exit_z8_time_ns;
722  	int urgent_latency_ns;
723  	int percent_of_ideal_drambw;
724  	int dram_clock_change_latency_ns;
725  	int dummy_clock_change_latency_ns;
726  	int fclk_clock_change_latency_ns;
727  	/* This forces a hard min on the DCFCLK we use
728  	 * for DML.  Unlike the debug option for forcing
729  	 * DCFCLK, this override affects watermark calculations
730  	 */
731  	int min_dcfclk_mhz;
732  };
733  
734  struct dc_state;
735  struct resource_pool;
736  struct dce_hwseq;
737  struct link_service;
738  
739  /*
740   * struct dc_debug_options - DC debug struct
741   *
742   * This struct provides a simple mechanism for developers to change some
743   * configurations, enable/disable features, and activate extra debug options.
744   * This can be very handy to narrow down whether some specific feature is
745   * causing an issue or not.
746   */
747  struct dc_debug_options {
748  	bool native422_support;
749  	bool disable_dsc;
750  	enum visual_confirm visual_confirm;
751  	int visual_confirm_rect_height;
752  
753  	bool sanity_checks;
754  	bool max_disp_clk;
755  	bool surface_trace;
756  	bool timing_trace;
757  	bool clock_trace;
758  	bool validation_trace;
759  	bool bandwidth_calcs_trace;
760  	int max_downscale_src_width;
761  
762  	/* stutter efficiency related */
763  	bool disable_stutter;
764  	bool use_max_lb;
765  	enum dcc_option disable_dcc;
766  
767  	/*
768  	 * @pipe_split_policy: Define which pipe split policy is used by the
769  	 * display core.
770  	 */
771  	enum pipe_split_policy pipe_split_policy;
772  	bool force_single_disp_pipe_split;
773  	bool voltage_align_fclk;
774  	bool disable_min_fclk;
775  
776  	bool disable_dfs_bypass;
777  	bool disable_dpp_power_gate;
778  	bool disable_hubp_power_gate;
779  	bool disable_dsc_power_gate;
780  	int dsc_min_slice_height_override;
781  	int dsc_bpp_increment_div;
782  	bool disable_pplib_wm_range;
783  	enum wm_report_mode pplib_wm_report_mode;
784  	unsigned int min_disp_clk_khz;
785  	unsigned int min_dpp_clk_khz;
786  	unsigned int min_dram_clk_khz;
787  	int sr_exit_time_dpm0_ns;
788  	int sr_enter_plus_exit_time_dpm0_ns;
789  	int sr_exit_time_ns;
790  	int sr_enter_plus_exit_time_ns;
791  	int sr_exit_z8_time_ns;
792  	int sr_enter_plus_exit_z8_time_ns;
793  	int urgent_latency_ns;
794  	uint32_t underflow_assert_delay_us;
795  	int percent_of_ideal_drambw;
796  	int dram_clock_change_latency_ns;
797  	bool optimized_watermark;
798  	int always_scale;
799  	bool disable_pplib_clock_request;
800  	bool disable_clock_gate;
801  	bool disable_mem_low_power;
802  	bool pstate_enabled;
803  	bool disable_dmcu;
804  	bool force_abm_enable;
805  	bool disable_stereo_support;
806  	bool vsr_support;
807  	bool performance_trace;
808  	bool az_endpoint_mute_only;
809  	bool always_use_regamma;
810  	bool recovery_enabled;
811  	bool avoid_vbios_exec_table;
812  	bool scl_reset_length10;
813  	bool hdmi20_disable;
814  	bool skip_detection_link_training;
815  	uint32_t edid_read_retry_times;
816  	unsigned int force_odm_combine; //bit vector based on otg inst
817  	unsigned int seamless_boot_odm_combine;
818  	unsigned int force_odm_combine_4to1; //bit vector based on otg inst
819  	int minimum_z8_residency_time;
820  	bool disable_z9_mpc;
821  	unsigned int force_fclk_khz;
822  	bool enable_tri_buf;
823  	bool dmub_offload_enabled;
824  	bool dmcub_emulation;
825  	bool disable_idle_power_optimizations;
826  	unsigned int mall_size_override;
827  	unsigned int mall_additional_timer_percent;
828  	bool mall_error_as_fatal;
829  	bool dmub_command_table; /* for testing only */
830  	struct dc_bw_validation_profile bw_val_profile;
831  	bool disable_fec;
832  	bool disable_48mhz_pwrdwn;
833  	/* This forces a hard min on the DCFCLK requested to SMU/PP
834  	 * watermarks are not affected.
835  	 */
836  	unsigned int force_min_dcfclk_mhz;
837  	int dwb_fi_phase;
838  	bool disable_timing_sync;
839  	bool cm_in_bypass;
840  	int force_clock_mode;/*every mode change.*/
841  
842  	bool disable_dram_clock_change_vactive_support;
843  	bool validate_dml_output;
844  	bool enable_dmcub_surface_flip;
845  	bool usbc_combo_phy_reset_wa;
846  	bool enable_dram_clock_change_one_display_vactive;
847  	/* TODO - remove once tested */
848  	bool legacy_dp2_lt;
849  	bool set_mst_en_for_sst;
850  	bool disable_uhbr;
851  	bool force_dp2_lt_fallback_method;
852  	bool ignore_cable_id;
853  	union mem_low_power_enable_options enable_mem_low_power;
854  	union root_clock_optimization_options root_clock_optimization;
855  	bool hpo_optimization;
856  	bool force_vblank_alignment;
857  
858  	/* Enable dmub aux for legacy ddc */
859  	bool enable_dmub_aux_for_legacy_ddc;
860  	bool disable_fams;
861  	bool disable_fams_gaming;
862  	/* FEC/PSR1 sequence enable delay in 100us */
863  	uint8_t fec_enable_delay_in100us;
864  	bool enable_driver_sequence_debug;
865  	enum det_size crb_alloc_policy;
866  	int crb_alloc_policy_min_disp_count;
867  	bool disable_z10;
868  	bool enable_z9_disable_interface;
869  	bool psr_skip_crtc_disable;
870  	union dpia_debug_options dpia_debug;
871  	bool disable_fixed_vs_aux_timeout_wa;
872  	uint32_t fixed_vs_aux_delay_config_wa;
873  	bool force_disable_subvp;
874  	bool force_subvp_mclk_switch;
875  	bool allow_sw_cursor_fallback;
876  	unsigned int force_subvp_num_ways;
877  	unsigned int force_mall_ss_num_ways;
878  	bool alloc_extra_way_for_cursor;
879  	uint32_t subvp_extra_lines;
880  	bool force_usr_allow;
881  	/* uses value at boot and disables switch */
882  	bool disable_dtb_ref_clk_switch;
883  	bool extended_blank_optimization;
884  	union aux_wake_wa_options aux_wake_wa;
885  	uint32_t mst_start_top_delay;
886  	uint8_t psr_power_use_phy_fsm;
887  	enum dml_hostvm_override_opts dml_hostvm_override;
888  	bool dml_disallow_alternate_prefetch_modes;
889  	bool use_legacy_soc_bb_mechanism;
890  	bool exit_idle_opt_for_cursor_updates;
891  	bool enable_single_display_2to1_odm_policy;
892  	bool enable_double_buffered_dsc_pg_support;
893  	bool enable_dp_dig_pixel_rate_div_policy;
894  	enum lttpr_mode lttpr_mode_override;
895  	unsigned int dsc_delay_factor_wa_x1000;
896  	unsigned int min_prefetch_in_strobe_ns;
897  	bool disable_unbounded_requesting;
898  	bool dig_fifo_off_in_blank;
899  	bool temp_mst_deallocation_sequence;
900  	bool override_dispclk_programming;
901  	bool disable_fpo_optimizations;
902  	bool support_eDP1_5;
903  	uint32_t fpo_vactive_margin_us;
904  	bool disable_fpo_vactive;
905  	bool disable_boot_optimizations;
906  	bool override_odm_optimization;
907  	bool minimize_dispclk_using_odm;
908  	bool disable_subvp_high_refresh;
909  	bool disable_dp_plus_plus_wa;
910  	uint32_t fpo_vactive_min_active_margin_us;
911  	uint32_t fpo_vactive_max_blank_us;
912  	bool enable_legacy_fast_update;
913  	bool disable_dc_mode_overwrite;
914  	bool replay_skip_crtc_disabled;
915  };
916  
917  struct gpu_info_soc_bounding_box_v1_0;
918  
919  /* Generic structure that can be used to query properties of DC. More fields
920   * can be added as required.
921   */
922  struct dc_current_properties {
923  	unsigned int cursor_size_limit;
924  };
925  
926  struct dc {
927  	struct dc_debug_options debug;
928  	struct dc_versions versions;
929  	struct dc_caps caps;
930  	struct dc_cap_funcs cap_funcs;
931  	struct dc_config config;
932  	struct dc_bounding_box_overrides bb_overrides;
933  	struct dc_bug_wa work_arounds;
934  	struct dc_context *ctx;
935  	struct dc_phy_addr_space_config vm_pa_config;
936  
937  	uint8_t link_count;
938  	struct dc_link *links[MAX_PIPES * 2];
939  	struct link_service *link_srv;
940  
941  	struct dc_state *current_state;
942  	struct resource_pool *res_pool;
943  
944  	struct clk_mgr *clk_mgr;
945  
946  	/* Display Engine Clock levels */
947  	struct dm_pp_clock_levels sclk_lvls;
948  
949  	/* Inputs into BW and WM calculations. */
950  	struct bw_calcs_dceip *bw_dceip;
951  	struct bw_calcs_vbios *bw_vbios;
952  	struct dcn_soc_bounding_box *dcn_soc;
953  	struct dcn_ip_params *dcn_ip;
954  	struct display_mode_lib dml;
955  
956  	/* HW functions */
957  	struct hw_sequencer_funcs hwss;
958  	struct dce_hwseq *hwseq;
959  
960  	/* Require to optimize clocks and bandwidth for added/removed planes */
961  	bool optimized_required;
962  	bool wm_optimized_required;
963  	bool idle_optimizations_allowed;
964  	bool enable_c20_dtm_b0;
965  
966  	/* Require to maintain clocks and bandwidth for UEFI enabled HW */
967  
968  	/* FBC compressor */
969  	struct compressor *fbc_compressor;
970  
971  	struct dc_debug_data debug_data;
972  	struct dpcd_vendor_signature vendor_signature;
973  
974  	const char *build_id;
975  	struct vm_helper *vm_helper;
976  
977  	uint32_t *dcn_reg_offsets;
978  	uint32_t *nbio_reg_offsets;
979  
980  	/* Scratch memory */
981  	struct {
982  		struct {
983  			/*
984  			 * For matching clock_limits table in driver with table
985  			 * from PMFW.
986  			 */
987  			struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
988  		} update_bw_bounding_box;
989  	} scratch;
990  };
991  
992  enum frame_buffer_mode {
993  	FRAME_BUFFER_MODE_LOCAL_ONLY = 0,
994  	FRAME_BUFFER_MODE_ZFB_ONLY,
995  	FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL,
996  } ;
997  
998  struct dchub_init_data {
999  	int64_t zfb_phys_addr_base;
1000  	int64_t zfb_mc_base_addr;
1001  	uint64_t zfb_size_in_byte;
1002  	enum frame_buffer_mode fb_mode;
1003  	bool dchub_initialzied;
1004  	bool dchub_info_valid;
1005  };
1006  
1007  struct dc_init_data {
1008  	struct hw_asic_id asic_id;
1009  	void *driver; /* ctx */
1010  	struct cgs_device *cgs_device;
1011  	struct dc_bounding_box_overrides bb_overrides;
1012  
1013  	int num_virtual_links;
1014  	/*
1015  	 * If 'vbios_override' not NULL, it will be called instead
1016  	 * of the real VBIOS. Intended use is Diagnostics on FPGA.
1017  	 */
1018  	struct dc_bios *vbios_override;
1019  	enum dce_environment dce_environment;
1020  
1021  	struct dmub_offload_funcs *dmub_if;
1022  	struct dc_reg_helper_state *dmub_offload;
1023  
1024  	struct dc_config flags;
1025  	uint64_t log_mask;
1026  
1027  	struct dpcd_vendor_signature vendor_signature;
1028  	bool force_smu_not_present;
1029  	/*
1030  	 * IP offset for run time initializaion of register addresses
1031  	 *
1032  	 * DCN3.5+ will fail dc_create() if these fields are null for them. They are
1033  	 * applicable starting with DCN32/321 and are not used for ASICs upstreamed
1034  	 * before them.
1035  	 */
1036  	uint32_t *dcn_reg_offsets;
1037  	uint32_t *nbio_reg_offsets;
1038  };
1039  
1040  struct dc_callback_init {
1041  	struct cp_psp cp_psp;
1042  };
1043  
1044  struct dc *dc_create(const struct dc_init_data *init_params);
1045  void dc_hardware_init(struct dc *dc);
1046  
1047  int dc_get_vmid_use_vector(struct dc *dc);
1048  void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid);
1049  /* Returns the number of vmids supported */
1050  int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config);
1051  void dc_init_callbacks(struct dc *dc,
1052  		const struct dc_callback_init *init_params);
1053  void dc_deinit_callbacks(struct dc *dc);
1054  void dc_destroy(struct dc **dc);
1055  
1056  /* Surface Interfaces */
1057  
1058  enum {
1059  	TRANSFER_FUNC_POINTS = 1025
1060  };
1061  
1062  struct dc_hdr_static_metadata {
1063  	/* display chromaticities and white point in units of 0.00001 */
1064  	unsigned int chromaticity_green_x;
1065  	unsigned int chromaticity_green_y;
1066  	unsigned int chromaticity_blue_x;
1067  	unsigned int chromaticity_blue_y;
1068  	unsigned int chromaticity_red_x;
1069  	unsigned int chromaticity_red_y;
1070  	unsigned int chromaticity_white_point_x;
1071  	unsigned int chromaticity_white_point_y;
1072  
1073  	uint32_t min_luminance;
1074  	uint32_t max_luminance;
1075  	uint32_t maximum_content_light_level;
1076  	uint32_t maximum_frame_average_light_level;
1077  };
1078  
1079  enum dc_transfer_func_type {
1080  	TF_TYPE_PREDEFINED,
1081  	TF_TYPE_DISTRIBUTED_POINTS,
1082  	TF_TYPE_BYPASS,
1083  	TF_TYPE_HWPWL
1084  };
1085  
1086  struct dc_transfer_func_distributed_points {
1087  	struct fixed31_32 red[TRANSFER_FUNC_POINTS];
1088  	struct fixed31_32 green[TRANSFER_FUNC_POINTS];
1089  	struct fixed31_32 blue[TRANSFER_FUNC_POINTS];
1090  
1091  	uint16_t end_exponent;
1092  	uint16_t x_point_at_y1_red;
1093  	uint16_t x_point_at_y1_green;
1094  	uint16_t x_point_at_y1_blue;
1095  };
1096  
1097  enum dc_transfer_func_predefined {
1098  	TRANSFER_FUNCTION_SRGB,
1099  	TRANSFER_FUNCTION_BT709,
1100  	TRANSFER_FUNCTION_PQ,
1101  	TRANSFER_FUNCTION_LINEAR,
1102  	TRANSFER_FUNCTION_UNITY,
1103  	TRANSFER_FUNCTION_HLG,
1104  	TRANSFER_FUNCTION_HLG12,
1105  	TRANSFER_FUNCTION_GAMMA22,
1106  	TRANSFER_FUNCTION_GAMMA24,
1107  	TRANSFER_FUNCTION_GAMMA26
1108  };
1109  
1110  
1111  struct dc_transfer_func {
1112  	struct kref refcount;
1113  	enum dc_transfer_func_type type;
1114  	enum dc_transfer_func_predefined tf;
1115  	/* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/
1116  	uint32_t sdr_ref_white_level;
1117  	union {
1118  		struct pwl_params pwl;
1119  		struct dc_transfer_func_distributed_points tf_pts;
1120  	};
1121  };
1122  
1123  
1124  union dc_3dlut_state {
1125  	struct {
1126  		uint32_t initialized:1;		/*if 3dlut is went through color module for initialization */
1127  		uint32_t rmu_idx_valid:1;	/*if mux settings are valid*/
1128  		uint32_t rmu_mux_num:3;		/*index of mux to use*/
1129  		uint32_t mpc_rmu0_mux:4;	/*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/
1130  		uint32_t mpc_rmu1_mux:4;
1131  		uint32_t mpc_rmu2_mux:4;
1132  		uint32_t reserved:15;
1133  	} bits;
1134  	uint32_t raw;
1135  };
1136  
1137  
1138  struct dc_3dlut {
1139  	struct kref refcount;
1140  	struct tetrahedral_params lut_3d;
1141  	struct fixed31_32 hdr_multiplier;
1142  	union dc_3dlut_state state;
1143  };
1144  /*
1145   * This structure is filled in by dc_surface_get_status and contains
1146   * the last requested address and the currently active address so the called
1147   * can determine if there are any outstanding flips
1148   */
1149  struct dc_plane_status {
1150  	struct dc_plane_address requested_address;
1151  	struct dc_plane_address current_address;
1152  	bool is_flip_pending;
1153  	bool is_right_eye;
1154  };
1155  
1156  union surface_update_flags {
1157  
1158  	struct {
1159  		uint32_t addr_update:1;
1160  		/* Medium updates */
1161  		uint32_t dcc_change:1;
1162  		uint32_t color_space_change:1;
1163  		uint32_t horizontal_mirror_change:1;
1164  		uint32_t per_pixel_alpha_change:1;
1165  		uint32_t global_alpha_change:1;
1166  		uint32_t hdr_mult:1;
1167  		uint32_t rotation_change:1;
1168  		uint32_t swizzle_change:1;
1169  		uint32_t scaling_change:1;
1170  		uint32_t position_change:1;
1171  		uint32_t in_transfer_func_change:1;
1172  		uint32_t input_csc_change:1;
1173  		uint32_t coeff_reduction_change:1;
1174  		uint32_t output_tf_change:1;
1175  		uint32_t pixel_format_change:1;
1176  		uint32_t plane_size_change:1;
1177  		uint32_t gamut_remap_change:1;
1178  
1179  		/* Full updates */
1180  		uint32_t new_plane:1;
1181  		uint32_t bpp_change:1;
1182  		uint32_t gamma_change:1;
1183  		uint32_t bandwidth_change:1;
1184  		uint32_t clock_change:1;
1185  		uint32_t stereo_format_change:1;
1186  		uint32_t lut_3d:1;
1187  		uint32_t tmz_changed:1;
1188  		uint32_t full_update:1;
1189  	} bits;
1190  
1191  	uint32_t raw;
1192  };
1193  
1194  struct dc_plane_state {
1195  	struct dc_plane_address address;
1196  	struct dc_plane_flip_time time;
1197  	bool triplebuffer_flips;
1198  	struct scaling_taps scaling_quality;
1199  	struct rect src_rect;
1200  	struct rect dst_rect;
1201  	struct rect clip_rect;
1202  
1203  	struct plane_size plane_size;
1204  	union dc_tiling_info tiling_info;
1205  
1206  	struct dc_plane_dcc_param dcc;
1207  
1208  	struct dc_gamma *gamma_correction;
1209  	struct dc_transfer_func *in_transfer_func;
1210  	struct dc_bias_and_scale *bias_and_scale;
1211  	struct dc_csc_transform input_csc_color_matrix;
1212  	struct fixed31_32 coeff_reduction_factor;
1213  	struct fixed31_32 hdr_mult;
1214  	struct colorspace_transform gamut_remap_matrix;
1215  
1216  	// TODO: No longer used, remove
1217  	struct dc_hdr_static_metadata hdr_static_ctx;
1218  
1219  	enum dc_color_space color_space;
1220  
1221  	struct dc_3dlut *lut3d_func;
1222  	struct dc_transfer_func *in_shaper_func;
1223  	struct dc_transfer_func *blend_tf;
1224  
1225  	struct dc_transfer_func *gamcor_tf;
1226  	enum surface_pixel_format format;
1227  	enum dc_rotation_angle rotation;
1228  	enum plane_stereo_format stereo_format;
1229  
1230  	bool is_tiling_rotated;
1231  	bool per_pixel_alpha;
1232  	bool pre_multiplied_alpha;
1233  	bool global_alpha;
1234  	int  global_alpha_value;
1235  	bool visible;
1236  	bool flip_immediate;
1237  	bool horizontal_mirror;
1238  	int layer_index;
1239  
1240  	union surface_update_flags update_flags;
1241  	bool flip_int_enabled;
1242  	bool skip_manual_trigger;
1243  
1244  	/* private to DC core */
1245  	struct dc_plane_status status;
1246  	struct dc_context *ctx;
1247  
1248  	/* HACK: Workaround for forcing full reprogramming under some conditions */
1249  	bool force_full_update;
1250  
1251  	bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead
1252  
1253  	/* private to dc_surface.c */
1254  	enum dc_irq_source irq_source;
1255  	struct kref refcount;
1256  	struct tg_color visual_confirm_color;
1257  
1258  	bool is_statically_allocated;
1259  };
1260  
1261  struct dc_plane_info {
1262  	struct plane_size plane_size;
1263  	union dc_tiling_info tiling_info;
1264  	struct dc_plane_dcc_param dcc;
1265  	enum surface_pixel_format format;
1266  	enum dc_rotation_angle rotation;
1267  	enum plane_stereo_format stereo_format;
1268  	enum dc_color_space color_space;
1269  	bool horizontal_mirror;
1270  	bool visible;
1271  	bool per_pixel_alpha;
1272  	bool pre_multiplied_alpha;
1273  	bool global_alpha;
1274  	int  global_alpha_value;
1275  	bool input_csc_enabled;
1276  	int layer_index;
1277  };
1278  
1279  struct dc_scaling_info {
1280  	struct rect src_rect;
1281  	struct rect dst_rect;
1282  	struct rect clip_rect;
1283  	struct scaling_taps scaling_quality;
1284  };
1285  
1286  struct dc_fast_update {
1287  	const struct dc_flip_addrs *flip_addr;
1288  	const struct dc_gamma *gamma;
1289  	const struct colorspace_transform *gamut_remap_matrix;
1290  	const struct dc_csc_transform *input_csc_color_matrix;
1291  	const struct fixed31_32 *coeff_reduction_factor;
1292  	struct dc_transfer_func *out_transfer_func;
1293  	struct dc_csc_transform *output_csc_transform;
1294  };
1295  
1296  struct dc_surface_update {
1297  	struct dc_plane_state *surface;
1298  
1299  	/* isr safe update parameters.  null means no updates */
1300  	const struct dc_flip_addrs *flip_addr;
1301  	const struct dc_plane_info *plane_info;
1302  	const struct dc_scaling_info *scaling_info;
1303  	struct fixed31_32 hdr_mult;
1304  	/* following updates require alloc/sleep/spin that is not isr safe,
1305  	 * null means no updates
1306  	 */
1307  	const struct dc_gamma *gamma;
1308  	const struct dc_transfer_func *in_transfer_func;
1309  
1310  	const struct dc_csc_transform *input_csc_color_matrix;
1311  	const struct fixed31_32 *coeff_reduction_factor;
1312  	const struct dc_transfer_func *func_shaper;
1313  	const struct dc_3dlut *lut3d_func;
1314  	const struct dc_transfer_func *blend_tf;
1315  	const struct colorspace_transform *gamut_remap_matrix;
1316  };
1317  
1318  /*
1319   * Create a new surface with default parameters;
1320   */
1321  struct dc_plane_state *dc_create_plane_state(struct dc *dc);
1322  const struct dc_plane_status *dc_plane_get_status(
1323  		const struct dc_plane_state *plane_state);
1324  
1325  void dc_plane_state_retain(struct dc_plane_state *plane_state);
1326  void dc_plane_state_release(struct dc_plane_state *plane_state);
1327  
1328  void dc_gamma_retain(struct dc_gamma *dc_gamma);
1329  void dc_gamma_release(struct dc_gamma **dc_gamma);
1330  struct dc_gamma *dc_create_gamma(void);
1331  
1332  void dc_transfer_func_retain(struct dc_transfer_func *dc_tf);
1333  void dc_transfer_func_release(struct dc_transfer_func *dc_tf);
1334  struct dc_transfer_func *dc_create_transfer_func(void);
1335  
1336  struct dc_3dlut *dc_create_3dlut_func(void);
1337  void dc_3dlut_func_release(struct dc_3dlut *lut);
1338  void dc_3dlut_func_retain(struct dc_3dlut *lut);
1339  
1340  void dc_post_update_surfaces_to_stream(
1341  		struct dc *dc);
1342  
1343  #include "dc_stream.h"
1344  
1345  /**
1346   * struct dc_validation_set - Struct to store surface/stream associations for validation
1347   */
1348  struct dc_validation_set {
1349  	/**
1350  	 * @stream: Stream state properties
1351  	 */
1352  	struct dc_stream_state *stream;
1353  
1354  	/**
1355  	 * @plane_states: Surface state
1356  	 */
1357  	struct dc_plane_state *plane_states[MAX_SURFACES];
1358  
1359  	/**
1360  	 * @plane_count: Total of active planes
1361  	 */
1362  	uint8_t plane_count;
1363  };
1364  
1365  bool dc_validate_boot_timing(const struct dc *dc,
1366  				const struct dc_sink *sink,
1367  				struct dc_crtc_timing *crtc_timing);
1368  
1369  enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
1370  
1371  void get_clock_requirements_for_state(struct dc_state *state, struct AsicStateEx *info);
1372  
1373  enum dc_status dc_validate_with_context(struct dc *dc,
1374  					const struct dc_validation_set set[],
1375  					int set_count,
1376  					struct dc_state *context,
1377  					bool fast_validate);
1378  
1379  bool dc_set_generic_gpio_for_stereo(bool enable,
1380  		struct gpio_service *gpio_service);
1381  
1382  /*
1383   * fast_validate: we return after determining if we can support the new state,
1384   * but before we populate the programming info
1385   */
1386  enum dc_status dc_validate_global_state(
1387  		struct dc *dc,
1388  		struct dc_state *new_ctx,
1389  		bool fast_validate);
1390  
1391  
1392  void dc_resource_state_construct(
1393  		const struct dc *dc,
1394  		struct dc_state *dst_ctx);
1395  
1396  bool dc_acquire_release_mpc_3dlut(
1397  		struct dc *dc, bool acquire,
1398  		struct dc_stream_state *stream,
1399  		struct dc_3dlut **lut,
1400  		struct dc_transfer_func **shaper);
1401  
1402  void dc_resource_state_copy_construct(
1403  		const struct dc_state *src_ctx,
1404  		struct dc_state *dst_ctx);
1405  
1406  void dc_resource_state_copy_construct_current(
1407  		const struct dc *dc,
1408  		struct dc_state *dst_ctx);
1409  
1410  void dc_resource_state_destruct(struct dc_state *context);
1411  
1412  bool dc_resource_is_dsc_encoding_supported(const struct dc *dc);
1413  
1414  enum dc_status dc_commit_streams(struct dc *dc,
1415  				 struct dc_stream_state *streams[],
1416  				 uint8_t stream_count);
1417  
1418  struct dc_state *dc_create_state(struct dc *dc);
1419  struct dc_state *dc_copy_state(struct dc_state *src_ctx);
1420  void dc_retain_state(struct dc_state *context);
1421  void dc_release_state(struct dc_state *context);
1422  
1423  struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc,
1424  		struct dc_stream_state *stream,
1425  		int mpcc_inst);
1426  
1427  
1428  uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane);
1429  
1430  void dc_set_disable_128b_132b_stream_overhead(bool disable);
1431  
1432  /* The function returns minimum bandwidth required to drive a given timing
1433   * return - minimum required timing bandwidth in kbps.
1434   */
1435  uint32_t dc_bandwidth_in_kbps_from_timing(
1436  		const struct dc_crtc_timing *timing,
1437  		const enum dc_link_encoding_format link_encoding);
1438  
1439  /* Link Interfaces */
1440  /*
1441   * A link contains one or more sinks and their connected status.
1442   * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported.
1443   */
1444  struct dc_link {
1445  	struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK];
1446  	unsigned int sink_count;
1447  	struct dc_sink *local_sink;
1448  	unsigned int link_index;
1449  	enum dc_connection_type type;
1450  	enum signal_type connector_signal;
1451  	enum dc_irq_source irq_source_hpd;
1452  	enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse  */
1453  
1454  	bool is_hpd_filter_disabled;
1455  	bool dp_ss_off;
1456  
1457  	/**
1458  	 * @link_state_valid:
1459  	 *
1460  	 * If there is no link and local sink, this variable should be set to
1461  	 * false. Otherwise, it should be set to true; usually, the function
1462  	 * core_link_enable_stream sets this field to true.
1463  	 */
1464  	bool link_state_valid;
1465  	bool aux_access_disabled;
1466  	bool sync_lt_in_progress;
1467  	bool skip_stream_reenable;
1468  	bool is_internal_display;
1469  	/** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */
1470  	bool is_dig_mapping_flexible;
1471  	bool hpd_status; /* HPD status of link without physical HPD pin. */
1472  	bool is_hpd_pending; /* Indicates a new received hpd */
1473  	bool is_automated; /* Indicates automated testing */
1474  
1475  	bool edp_sink_present;
1476  
1477  	struct dp_trace dp_trace;
1478  
1479  	/* caps is the same as reported_link_cap. link_traing use
1480  	 * reported_link_cap. Will clean up.  TODO
1481  	 */
1482  	struct dc_link_settings reported_link_cap;
1483  	struct dc_link_settings verified_link_cap;
1484  	struct dc_link_settings cur_link_settings;
1485  	struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX];
1486  	struct dc_link_settings preferred_link_setting;
1487  	/* preferred_training_settings are override values that
1488  	 * come from DM. DM is responsible for the memory
1489  	 * management of the override pointers.
1490  	 */
1491  	struct dc_link_training_overrides preferred_training_settings;
1492  	struct dp_audio_test_data audio_test_data;
1493  
1494  	uint8_t ddc_hw_inst;
1495  
1496  	uint8_t hpd_src;
1497  
1498  	uint8_t link_enc_hw_inst;
1499  	/* DIG link encoder ID. Used as index in link encoder resource pool.
1500  	 * For links with fixed mapping to DIG, this is not changed after dc_link
1501  	 * object creation.
1502  	 */
1503  	enum engine_id eng_id;
1504  	enum engine_id dpia_preferred_eng_id;
1505  
1506  	bool test_pattern_enabled;
1507  	enum dp_test_pattern current_test_pattern;
1508  	union compliance_test_state compliance_test_state;
1509  
1510  	void *priv;
1511  
1512  	struct ddc_service *ddc;
1513  
1514  	enum dp_panel_mode panel_mode;
1515  	bool aux_mode;
1516  
1517  	/* Private to DC core */
1518  
1519  	const struct dc *dc;
1520  
1521  	struct dc_context *ctx;
1522  
1523  	struct panel_cntl *panel_cntl;
1524  	struct link_encoder *link_enc;
1525  	struct graphics_object_id link_id;
1526  	/* Endpoint type distinguishes display endpoints which do not have entries
1527  	 * in the BIOS connector table from those that do. Helps when tracking link
1528  	 * encoder to display endpoint assignments.
1529  	 */
1530  	enum display_endpoint_type ep_type;
1531  	union ddi_channel_mapping ddi_channel_mapping;
1532  	struct connector_device_tag_info device_tag;
1533  	struct dpcd_caps dpcd_caps;
1534  	uint32_t dongle_max_pix_clk;
1535  	unsigned short chip_caps;
1536  	unsigned int dpcd_sink_count;
1537  	struct hdcp_caps hdcp_caps;
1538  	enum edp_revision edp_revision;
1539  	union dpcd_sink_ext_caps dpcd_sink_ext_caps;
1540  
1541  	struct psr_settings psr_settings;
1542  
1543  	struct replay_settings replay_settings;
1544  
1545  	/* Drive settings read from integrated info table */
1546  	struct dc_lane_settings bios_forced_drive_settings;
1547  
1548  	/* Vendor specific LTTPR workaround variables */
1549  	uint8_t vendor_specific_lttpr_link_rate_wa;
1550  	bool apply_vendor_specific_lttpr_link_rate_wa;
1551  
1552  	/* MST record stream using this link */
1553  	struct link_flags {
1554  		bool dp_keep_receiver_powered;
1555  		bool dp_skip_DID2;
1556  		bool dp_skip_reset_segment;
1557  		bool dp_skip_fs_144hz;
1558  		bool dp_mot_reset_segment;
1559  		/* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */
1560  		bool dpia_mst_dsc_always_on;
1561  		/* Forced DPIA into TBT3 compatibility mode. */
1562  		bool dpia_forced_tbt3_mode;
1563  		bool dongle_mode_timing_override;
1564  		bool blank_stream_on_ocs_change;
1565  		bool read_dpcd204h_on_irq_hpd;
1566  	} wa_flags;
1567  	struct link_mst_stream_allocation_table mst_stream_alloc_table;
1568  
1569  	struct dc_link_status link_status;
1570  	struct dprx_states dprx_states;
1571  
1572  	struct gpio *hpd_gpio;
1573  	enum dc_link_fec_state fec_state;
1574  	bool link_powered_externally;	// Used to bypass hardware sequencing delays when panel is powered down forcibly
1575  
1576  	struct dc_panel_config panel_config;
1577  	struct phy_state phy_state;
1578  	// BW ALLOCATON USB4 ONLY
1579  	struct dc_dpia_bw_alloc dpia_bw_alloc_config;
1580  	bool skip_implict_edp_power_control;
1581  };
1582  
1583  /* Return an enumerated dc_link.
1584   * dc_link order is constant and determined at
1585   * boot time.  They cannot be created or destroyed.
1586   * Use dc_get_caps() to get number of links.
1587   */
1588  struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
1589  
1590  /* Return instance id of the edp link. Inst 0 is primary edp link. */
1591  bool dc_get_edp_link_panel_inst(const struct dc *dc,
1592  		const struct dc_link *link,
1593  		unsigned int *inst_out);
1594  
1595  /* Return an array of link pointers to edp links. */
1596  void dc_get_edp_links(const struct dc *dc,
1597  		struct dc_link **edp_links,
1598  		int *edp_num);
1599  
1600  void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link,
1601  				 bool powerOn);
1602  
1603  /* The function initiates detection handshake over the given link. It first
1604   * determines if there are display connections over the link. If so it initiates
1605   * detection protocols supported by the connected receiver device. The function
1606   * contains protocol specific handshake sequences which are sometimes mandatory
1607   * to establish a proper connection between TX and RX. So it is always
1608   * recommended to call this function as the first link operation upon HPD event
1609   * or power up event. Upon completion, the function will update link structure
1610   * in place based on latest RX capabilities. The function may also cause dpms
1611   * to be reset to off for all currently enabled streams to the link. It is DM's
1612   * responsibility to serialize detection and DPMS updates.
1613   *
1614   * @reason - Indicate which event triggers this detection. dc may customize
1615   * detection flow depending on the triggering events.
1616   * return false - if detection is not fully completed. This could happen when
1617   * there is an unrecoverable error during detection or detection is partially
1618   * completed (detection has been delegated to dm mst manager ie.
1619   * link->connection_type == dc_connection_mst_branch when returning false).
1620   * return true - detection is completed, link has been fully updated with latest
1621   * detection result.
1622   */
1623  bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason);
1624  
1625  struct dc_sink_init_data;
1626  
1627  /* When link connection type is dc_connection_mst_branch, remote sink can be
1628   * added to the link. The interface creates a remote sink and associates it with
1629   * current link. The sink will be retained by link until remove remote sink is
1630   * called.
1631   *
1632   * @dc_link - link the remote sink will be added to.
1633   * @edid - byte array of EDID raw data.
1634   * @len - size of the edid in byte
1635   * @init_data -
1636   */
1637  struct dc_sink *dc_link_add_remote_sink(
1638  		struct dc_link *dc_link,
1639  		const uint8_t *edid,
1640  		int len,
1641  		struct dc_sink_init_data *init_data);
1642  
1643  /* Remove remote sink from a link with dc_connection_mst_branch connection type.
1644   * @link - link the sink should be removed from
1645   * @sink - sink to be removed.
1646   */
1647  void dc_link_remove_remote_sink(
1648  	struct dc_link *link,
1649  	struct dc_sink *sink);
1650  
1651  /* Enable HPD interrupt handler for a given link */
1652  void dc_link_enable_hpd(const struct dc_link *link);
1653  
1654  /* Disable HPD interrupt handler for a given link */
1655  void dc_link_disable_hpd(const struct dc_link *link);
1656  
1657  /* determine if there is a sink connected to the link
1658   *
1659   * @type - dc_connection_single if connected, dc_connection_none otherwise.
1660   * return - false if an unexpected error occurs, true otherwise.
1661   *
1662   * NOTE: This function doesn't detect downstream sink connections i.e
1663   * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will
1664   * return dc_connection_single if the branch device is connected despite of
1665   * downstream sink's connection status.
1666   */
1667  bool dc_link_detect_connection_type(struct dc_link *link,
1668  		enum dc_connection_type *type);
1669  
1670  /* query current hpd pin value
1671   * return - true HPD is asserted (HPD high), false otherwise (HPD low)
1672   *
1673   */
1674  bool dc_link_get_hpd_state(struct dc_link *link);
1675  
1676  /* Getter for cached link status from given link */
1677  const struct dc_link_status *dc_link_get_status(const struct dc_link *link);
1678  
1679  /* enable/disable hardware HPD filter.
1680   *
1681   * @link - The link the HPD pin is associated with.
1682   * @enable = true - enable hardware HPD filter. HPD event will only queued to irq
1683   * handler once after no HPD change has been detected within dc default HPD
1684   * filtering interval since last HPD event. i.e if display keeps toggling hpd
1685   * pulses within default HPD interval, no HPD event will be received until HPD
1686   * toggles have stopped. Then HPD event will be queued to irq handler once after
1687   * dc default HPD filtering interval since last HPD event.
1688   *
1689   * @enable = false - disable hardware HPD filter. HPD event will be queued
1690   * immediately to irq handler after no HPD change has been detected within
1691   * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms).
1692   */
1693  void dc_link_enable_hpd_filter(struct dc_link *link, bool enable);
1694  
1695  /* submit i2c read/write payloads through ddc channel
1696   * @link_index - index to a link with ddc in i2c mode
1697   * @cmd - i2c command structure
1698   * return - true if success, false otherwise.
1699   */
1700  bool dc_submit_i2c(
1701  		struct dc *dc,
1702  		uint32_t link_index,
1703  		struct i2c_command *cmd);
1704  
1705  /* submit i2c read/write payloads through oem channel
1706   * @link_index - index to a link with ddc in i2c mode
1707   * @cmd - i2c command structure
1708   * return - true if success, false otherwise.
1709   */
1710  bool dc_submit_i2c_oem(
1711  		struct dc *dc,
1712  		struct i2c_command *cmd);
1713  
1714  enum aux_return_code_type;
1715  /* Attempt to transfer the given aux payload. This function does not perform
1716   * retries or handle error states. The reply is returned in the payload->reply
1717   * and the result through operation_result. Returns the number of bytes
1718   * transferred,or -1 on a failure.
1719   */
1720  int dc_link_aux_transfer_raw(struct ddc_service *ddc,
1721  		struct aux_payload *payload,
1722  		enum aux_return_code_type *operation_result);
1723  
1724  bool dc_is_oem_i2c_device_present(
1725  	struct dc *dc,
1726  	size_t slave_address
1727  );
1728  
1729  /* return true if the connected receiver supports the hdcp version */
1730  bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal);
1731  bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal);
1732  
1733  /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD).
1734   *
1735   * TODO - When defer_handling is true the function will have a different purpose.
1736   * It no longer does complete hpd rx irq handling. We should create a separate
1737   * interface specifically for this case.
1738   *
1739   * Return:
1740   * true - Downstream port status changed. DM should call DC to do the
1741   * detection.
1742   * false - no change in Downstream port status. No further action required
1743   * from DM.
1744   */
1745  bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link,
1746  		union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss,
1747  		bool defer_handling, bool *has_left_work);
1748  /* handle DP specs define test automation sequence*/
1749  void dc_link_dp_handle_automated_test(struct dc_link *link);
1750  
1751  /* handle DP Link loss sequence and try to recover RX link loss with best
1752   * effort
1753   */
1754  void dc_link_dp_handle_link_loss(struct dc_link *link);
1755  
1756  /* Determine if hpd rx irq should be handled or ignored
1757   * return true - hpd rx irq should be handled.
1758   * return false - it is safe to ignore hpd rx irq event
1759   */
1760  bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link);
1761  
1762  /* Determine if link loss is indicated with a given hpd_irq_dpcd_data.
1763   * @link - link the hpd irq data associated with
1764   * @hpd_irq_dpcd_data - input hpd irq data
1765   * return - true if hpd irq data indicates a link lost
1766   */
1767  bool dc_link_check_link_loss_status(struct dc_link *link,
1768  		union hpd_irq_data *hpd_irq_dpcd_data);
1769  
1770  /* Read hpd rx irq data from a given link
1771   * @link - link where the hpd irq data should be read from
1772   * @irq_data - output hpd irq data
1773   * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data
1774   * read has failed.
1775   */
1776  enum dc_status dc_link_dp_read_hpd_rx_irq_data(
1777  	struct dc_link *link,
1778  	union hpd_irq_data *irq_data);
1779  
1780  /* The function clears recorded DP RX states in the link. DM should call this
1781   * function when it is resuming from S3 power state to previously connected links.
1782   *
1783   * TODO - in the future we should consider to expand link resume interface to
1784   * support clearing previous rx states. So we don't have to rely on dm to call
1785   * this interface explicitly.
1786   */
1787  void dc_link_clear_dprx_states(struct dc_link *link);
1788  
1789  /* Destruct the mst topology of the link and reset the allocated payload table
1790   *
1791   * NOTE: this should only be called if DM chooses not to call dc_link_detect but
1792   * still wants to reset MST topology on an unplug event */
1793  bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link);
1794  
1795  /* The function calculates effective DP link bandwidth when a given link is
1796   * using the given link settings.
1797   *
1798   * return - total effective link bandwidth in kbps.
1799   */
1800  uint32_t dc_link_bandwidth_kbps(
1801  	const struct dc_link *link,
1802  	const struct dc_link_settings *link_setting);
1803  
1804  /* The function takes a snapshot of current link resource allocation state
1805   * @dc: pointer to dc of the dm calling this
1806   * @map: a dc link resource snapshot defined internally to dc.
1807   *
1808   * DM needs to capture a snapshot of current link resource allocation mapping
1809   * and store it in its persistent storage.
1810   *
1811   * Some of the link resource is using first come first serve policy.
1812   * The allocation mapping depends on original hotplug order. This information
1813   * is lost after driver is loaded next time. The snapshot is used in order to
1814   * restore link resource to its previous state so user will get consistent
1815   * link capability allocation across reboot.
1816   *
1817   */
1818  void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map);
1819  
1820  /* This function restores link resource allocation state from a snapshot
1821   * @dc: pointer to dc of the dm calling this
1822   * @map: a dc link resource snapshot defined internally to dc.
1823   *
1824   * DM needs to call this function after initial link detection on boot and
1825   * before first commit streams to restore link resource allocation state
1826   * from previous boot session.
1827   *
1828   * Some of the link resource is using first come first serve policy.
1829   * The allocation mapping depends on original hotplug order. This information
1830   * is lost after driver is loaded next time. The snapshot is used in order to
1831   * restore link resource to its previous state so user will get consistent
1832   * link capability allocation across reboot.
1833   *
1834   */
1835  void dc_restore_link_res_map(const struct dc *dc, uint32_t *map);
1836  
1837  /* TODO: this is not meant to be exposed to DM. Should switch to stream update
1838   * interface i.e stream_update->dsc_config
1839   */
1840  bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx);
1841  
1842  /* translate a raw link rate data to bandwidth in kbps */
1843  uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw);
1844  
1845  /* determine the optimal bandwidth given link and required bw.
1846   * @link - current detected link
1847   * @req_bw - requested bandwidth in kbps
1848   * @link_settings - returned most optimal link settings that can fit the
1849   * requested bandwidth
1850   * return - false if link can't support requested bandwidth, true if link
1851   * settings is found.
1852   */
1853  bool dc_link_decide_edp_link_settings(struct dc_link *link,
1854  		struct dc_link_settings *link_settings,
1855  		uint32_t req_bw);
1856  
1857  /* return the max dp link settings can be driven by the link without considering
1858   * connected RX device and its capability
1859   */
1860  bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link,
1861  		struct dc_link_settings *max_link_enc_cap);
1862  
1863  /* determine when the link is driving MST mode, what DP link channel coding
1864   * format will be used. The decision will remain unchanged until next HPD event.
1865   *
1866   * @link -  a link with DP RX connection
1867   * return - if stream is committed to this link with MST signal type, type of
1868   * channel coding format dc will choose.
1869   */
1870  enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format(
1871  		const struct dc_link *link);
1872  
1873  /* get max dp link settings the link can enable with all things considered. (i.e
1874   * TX/RX/Cable capabilities and dp override policies.
1875   *
1876   * @link - a link with DP RX connection
1877   * return - max dp link settings the link can enable.
1878   *
1879   */
1880  const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link);
1881  
1882  /* Get the highest encoding format that the link supports; highest meaning the
1883   * encoding format which supports the maximum bandwidth.
1884   *
1885   * @link - a link with DP RX connection
1886   * return - highest encoding format link supports.
1887   */
1888  enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link);
1889  
1890  /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected
1891   * to a link with dp connector signal type.
1892   * @link - a link with dp connector signal type
1893   * return - true if connected, false otherwise
1894   */
1895  bool dc_link_is_dp_sink_present(struct dc_link *link);
1896  
1897  /* Force DP lane settings update to main-link video signal and notify the change
1898   * to DP RX via DPCD. This is a debug interface used for video signal integrity
1899   * tuning purpose. The interface assumes link has already been enabled with DP
1900   * signal.
1901   *
1902   * @lt_settings - a container structure with desired hw_lane_settings
1903   */
1904  void dc_link_set_drive_settings(struct dc *dc,
1905  				struct link_training_settings *lt_settings,
1906  				struct dc_link *link);
1907  
1908  /* Enable a test pattern in Link or PHY layer in an active link for compliance
1909   * test or debugging purpose. The test pattern will remain until next un-plug.
1910   *
1911   * @link - active link with DP signal output enabled.
1912   * @test_pattern - desired test pattern to output.
1913   * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern.
1914   * @test_pattern_color_space - for video test pattern choose a desired color
1915   * space.
1916   * @p_link_settings - For PHY pattern choose a desired link settings
1917   * @p_custom_pattern - some test pattern will require a custom input to
1918   * customize some pattern details. Otherwise keep it to NULL.
1919   * @cust_pattern_size - size of the custom pattern input.
1920   *
1921   */
1922  bool dc_link_dp_set_test_pattern(
1923  	struct dc_link *link,
1924  	enum dp_test_pattern test_pattern,
1925  	enum dp_test_pattern_color_space test_pattern_color_space,
1926  	const struct link_training_settings *p_link_settings,
1927  	const unsigned char *p_custom_pattern,
1928  	unsigned int cust_pattern_size);
1929  
1930  /* Force DP link settings to always use a specific value until reboot to a
1931   * specific link. If link has already been enabled, the interface will also
1932   * switch to desired link settings immediately. This is a debug interface to
1933   * generic dp issue trouble shooting.
1934   */
1935  void dc_link_set_preferred_link_settings(struct dc *dc,
1936  		struct dc_link_settings *link_setting,
1937  		struct dc_link *link);
1938  
1939  /* Force DP link to customize a specific link training behavior by overriding to
1940   * standard DP specs defined protocol. This is a debug interface to trouble shoot
1941   * display specific link training issues or apply some display specific
1942   * workaround in link training.
1943   *
1944   * @link_settings - if not NULL, force preferred link settings to the link.
1945   * @lt_override - a set of override pointers. If any pointer is none NULL, dc
1946   * will apply this particular override in future link training. If NULL is
1947   * passed in, dc resets previous overrides.
1948   * NOTE: DM must keep the memory from override pointers until DM resets preferred
1949   * training settings.
1950   */
1951  void dc_link_set_preferred_training_settings(struct dc *dc,
1952  		struct dc_link_settings *link_setting,
1953  		struct dc_link_training_overrides *lt_overrides,
1954  		struct dc_link *link,
1955  		bool skip_immediate_retrain);
1956  
1957  /* return - true if FEC is supported with connected DP RX, false otherwise */
1958  bool dc_link_is_fec_supported(const struct dc_link *link);
1959  
1960  /* query FEC enablement policy to determine if FEC will be enabled by dc during
1961   * link enablement.
1962   * return - true if FEC should be enabled, false otherwise.
1963   */
1964  bool dc_link_should_enable_fec(const struct dc_link *link);
1965  
1966  /* determine lttpr mode the current link should be enabled with a specific link
1967   * settings.
1968   */
1969  enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link,
1970  		struct dc_link_settings *link_setting);
1971  
1972  /* Force DP RX to update its power state.
1973   * NOTE: this interface doesn't update dp main-link. Calling this function will
1974   * cause DP TX main-link and DP RX power states out of sync. DM has to restore
1975   * RX power state back upon finish DM specific execution requiring DP RX in a
1976   * specific power state.
1977   * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power
1978   * state.
1979   */
1980  void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on);
1981  
1982  /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite
1983   * current value read from extended receiver cap from 02200h - 0220Fh.
1984   * Some DP RX has problems of providing accurate DP receiver caps from extended
1985   * field, this interface is a workaround to revert link back to use base caps.
1986   */
1987  void dc_link_overwrite_extended_receiver_cap(
1988  		struct dc_link *link);
1989  
1990  void dc_link_edp_panel_backlight_power_on(struct dc_link *link,
1991  		bool wait_for_hpd);
1992  
1993  /* Set backlight level of an embedded panel (eDP, LVDS).
1994   * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer
1995   * and 16 bit fractional, where 1.0 is max backlight value.
1996   */
1997  bool dc_link_set_backlight_level(const struct dc_link *dc_link,
1998  		uint32_t backlight_pwm_u16_16,
1999  		uint32_t frame_ramp);
2000  
2001  /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */
2002  bool dc_link_set_backlight_level_nits(struct dc_link *link,
2003  		bool isHDR,
2004  		uint32_t backlight_millinits,
2005  		uint32_t transition_time_in_ms);
2006  
2007  bool dc_link_get_backlight_level_nits(struct dc_link *link,
2008  		uint32_t *backlight_millinits,
2009  		uint32_t *backlight_millinits_peak);
2010  
2011  int dc_link_get_backlight_level(const struct dc_link *dc_link);
2012  
2013  int dc_link_get_target_backlight_pwm(const struct dc_link *link);
2014  
2015  bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable,
2016  		bool wait, bool force_static, const unsigned int *power_opts);
2017  
2018  bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state);
2019  
2020  bool dc_link_setup_psr(struct dc_link *dc_link,
2021  		const struct dc_stream_state *stream, struct psr_config *psr_config,
2022  		struct psr_context *psr_context);
2023  
2024  bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state);
2025  
2026  /* On eDP links this function call will stall until T12 has elapsed.
2027   * If the panel is not in power off state, this function will return
2028   * immediately.
2029   */
2030  bool dc_link_wait_for_t12(struct dc_link *link);
2031  
2032  /* Determine if dp trace has been initialized to reflect upto date result *
2033   * return - true if trace is initialized and has valid data. False dp trace
2034   * doesn't have valid result.
2035   */
2036  bool dc_dp_trace_is_initialized(struct dc_link *link);
2037  
2038  /* Query a dp trace flag to indicate if the current dp trace data has been
2039   * logged before
2040   */
2041  bool dc_dp_trace_is_logged(struct dc_link *link,
2042  		bool in_detection);
2043  
2044  /* Set dp trace flag to indicate whether DM has already logged the current dp
2045   * trace data. DM can set is_logged to true upon logging and check
2046   * dc_dp_trace_is_logged before logging to avoid logging the same result twice.
2047   */
2048  void dc_dp_trace_set_is_logged_flag(struct dc_link *link,
2049  		bool in_detection,
2050  		bool is_logged);
2051  
2052  /* Obtain driver time stamp for last dp link training end. The time stamp is
2053   * formatted based on dm_get_timestamp DM function.
2054   * @in_detection - true to get link training end time stamp of last link
2055   * training in detection sequence. false to get link training end time stamp
2056   * of last link training in commit (dpms) sequence
2057   */
2058  unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link,
2059  		bool in_detection);
2060  
2061  /* Get how many link training attempts dc has done with latest sequence.
2062   * @in_detection - true to get link training count of last link
2063   * training in detection sequence. false to get link training count of last link
2064   * training in commit (dpms) sequence
2065   */
2066  const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link,
2067  		bool in_detection);
2068  
2069  /* Get how many link loss has happened since last link training attempts */
2070  unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link);
2071  
2072  /*
2073   *  USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS
2074   */
2075  /*
2076   * Send a request from DP-Tx requesting to allocate BW remotely after
2077   * allocating it locally. This will get processed by CM and a CB function
2078   * will be called.
2079   *
2080   * @link: pointer to the dc_link struct instance
2081   * @req_bw: The requested bw in Kbyte to allocated
2082   *
2083   * return: none
2084   */
2085  void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw);
2086  
2087  /*
2088   * Handle function for when the status of the Request above is complete.
2089   * We will find out the result of allocating on CM and update structs.
2090   *
2091   * @link: pointer to the dc_link struct instance
2092   * @bw: Allocated or Estimated BW depending on the result
2093   * @result: Response type
2094   *
2095   * return: none
2096   */
2097  void dc_link_handle_usb4_bw_alloc_response(struct dc_link *link,
2098  		uint8_t bw, uint8_t result);
2099  
2100  /*
2101   * Handle the USB4 BW Allocation related functionality here:
2102   * Plug => Try to allocate max bw from timing parameters supported by the sink
2103   * Unplug => de-allocate bw
2104   *
2105   * @link: pointer to the dc_link struct instance
2106   * @peak_bw: Peak bw used by the link/sink
2107   *
2108   * return: allocated bw else return 0
2109   */
2110  int dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link(
2111  		struct dc_link *link, int peak_bw);
2112  
2113  /*
2114   * Validate the BW of all the valid DPIA links to make sure it doesn't exceed
2115   * available BW for each host router
2116   *
2117   * @dc: pointer to dc struct
2118   * @stream: pointer to all possible streams
2119   * @count: number of valid DPIA streams
2120   *
2121   * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE
2122   */
2123  bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams,
2124  		const unsigned int count);
2125  
2126  /* Sink Interfaces - A sink corresponds to a display output device */
2127  
2128  struct dc_container_id {
2129  	// 128bit GUID in binary form
2130  	unsigned char  guid[16];
2131  	// 8 byte port ID -> ELD.PortID
2132  	unsigned int   portId[2];
2133  	// 128bit GUID in binary formufacturer name -> ELD.ManufacturerName
2134  	unsigned short manufacturerName;
2135  	// 2 byte product code -> ELD.ProductCode
2136  	unsigned short productCode;
2137  };
2138  
2139  
2140  struct dc_sink_dsc_caps {
2141  	// 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology),
2142  	// 'false' if they are sink's DSC caps
2143  	bool is_virtual_dpcd_dsc;
2144  #if defined(CONFIG_DRM_AMD_DC_FP)
2145  	// 'true' if MST topology supports DSC passthrough for sink
2146  	// 'false' if MST topology does not support DSC passthrough
2147  	bool is_dsc_passthrough_supported;
2148  #endif
2149  	struct dsc_dec_dpcd_caps dsc_dec_caps;
2150  };
2151  
2152  struct dc_sink_fec_caps {
2153  	bool is_rx_fec_supported;
2154  	bool is_topology_fec_supported;
2155  };
2156  
2157  struct scdc_caps {
2158  	union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI;
2159  	union hdmi_scdc_device_id_data device_id;
2160  };
2161  
2162  /*
2163   * The sink structure contains EDID and other display device properties
2164   */
2165  struct dc_sink {
2166  	enum signal_type sink_signal;
2167  	struct dc_edid dc_edid; /* raw edid */
2168  	struct dc_edid_caps edid_caps; /* parse display caps */
2169  	struct dc_container_id *dc_container_id;
2170  	uint32_t dongle_max_pix_clk;
2171  	void *priv;
2172  	struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX];
2173  	bool converter_disable_audio;
2174  
2175  	struct scdc_caps scdc_caps;
2176  	struct dc_sink_dsc_caps dsc_caps;
2177  	struct dc_sink_fec_caps fec_caps;
2178  
2179  	bool is_vsc_sdp_colorimetry_supported;
2180  
2181  	/* private to DC core */
2182  	struct dc_link *link;
2183  	struct dc_context *ctx;
2184  
2185  	uint32_t sink_id;
2186  
2187  	/* private to dc_sink.c */
2188  	// refcount must be the last member in dc_sink, since we want the
2189  	// sink structure to be logically cloneable up to (but not including)
2190  	// refcount
2191  	struct kref refcount;
2192  };
2193  
2194  void dc_sink_retain(struct dc_sink *sink);
2195  void dc_sink_release(struct dc_sink *sink);
2196  
2197  struct dc_sink_init_data {
2198  	enum signal_type sink_signal;
2199  	struct dc_link *link;
2200  	uint32_t dongle_max_pix_clk;
2201  	bool converter_disable_audio;
2202  };
2203  
2204  struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params);
2205  
2206  /* Newer interfaces  */
2207  struct dc_cursor {
2208  	struct dc_plane_address address;
2209  	struct dc_cursor_attributes attributes;
2210  };
2211  
2212  
2213  /* Interrupt interfaces */
2214  enum dc_irq_source dc_interrupt_to_irq_source(
2215  		struct dc *dc,
2216  		uint32_t src_id,
2217  		uint32_t ext_id);
2218  bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
2219  void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
2220  enum dc_irq_source dc_get_hpd_irq_source_at_index(
2221  		struct dc *dc, uint32_t link_index);
2222  
2223  void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable);
2224  
2225  /* Power Interfaces */
2226  
2227  void dc_set_power_state(
2228  		struct dc *dc,
2229  		enum dc_acpi_cm_power_state power_state);
2230  void dc_resume(struct dc *dc);
2231  
2232  void dc_power_down_on_boot(struct dc *dc);
2233  
2234  /*
2235   * HDCP Interfaces
2236   */
2237  enum hdcp_message_status dc_process_hdcp_msg(
2238  		enum signal_type signal,
2239  		struct dc_link *link,
2240  		struct hdcp_protection_message *message_info);
2241  bool dc_is_dmcu_initialized(struct dc *dc);
2242  
2243  enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping);
2244  void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
2245  
2246  bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, struct dc_plane_state *plane,
2247  				struct dc_cursor_attributes *cursor_attr);
2248  
2249  void dc_allow_idle_optimizations(struct dc *dc, bool allow);
2250  
2251  /* set min and max memory clock to lowest and highest DPM level, respectively */
2252  void dc_unlock_memory_clock_frequency(struct dc *dc);
2253  
2254  /* set min memory clock to the min required for current mode, max to maxDPM */
2255  void dc_lock_memory_clock_frequency(struct dc *dc);
2256  
2257  /* set soft max for memclk, to be used for AC/DC switching clock limitations */
2258  void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable);
2259  
2260  /* cleanup on driver unload */
2261  void dc_hardware_release(struct dc *dc);
2262  
2263  /* disables fw based mclk switch */
2264  void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc);
2265  
2266  bool dc_set_psr_allow_active(struct dc *dc, bool enable);
2267  void dc_z10_restore(const struct dc *dc);
2268  void dc_z10_save_init(struct dc *dc);
2269  
2270  bool dc_is_dmub_outbox_supported(struct dc *dc);
2271  bool dc_enable_dmub_notifications(struct dc *dc);
2272  
2273  bool dc_abm_save_restore(
2274  		struct dc *dc,
2275  		struct dc_stream_state *stream,
2276  		struct abm_save_restore *pData);
2277  
2278  void dc_enable_dmub_outbox(struct dc *dc);
2279  
2280  bool dc_process_dmub_aux_transfer_async(struct dc *dc,
2281  				uint32_t link_index,
2282  				struct aux_payload *payload);
2283  
2284  /* Get dc link index from dpia port index */
2285  uint8_t get_link_index_from_dpia_port_index(const struct dc *dc,
2286  				uint8_t dpia_port_index);
2287  
2288  bool dc_process_dmub_set_config_async(struct dc *dc,
2289  				uint32_t link_index,
2290  				struct set_config_cmd_payload *payload,
2291  				struct dmub_notification *notify);
2292  
2293  enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
2294  				uint32_t link_index,
2295  				uint8_t mst_alloc_slots,
2296  				uint8_t *mst_slots_in_use);
2297  
2298  void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc,
2299  				uint32_t hpd_int_enable);
2300  
2301  void dc_print_dmub_diagnostic_data(const struct dc *dc);
2302  
2303  void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties);
2304  
2305  /* DSC Interfaces */
2306  #include "dc_dsc.h"
2307  
2308  /* Disable acc mode Interfaces */
2309  void dc_disable_accelerated_mode(struct dc *dc);
2310  
2311  bool dc_is_timing_changed(struct dc_stream_state *cur_stream,
2312  		       struct dc_stream_state *new_stream);
2313  
2314  #endif /* DC_INTERFACE_H_ */
2315