1 /*
2 * QEMU SuperH CPU
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
25 #include "cpu.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "exec/translation-block.h"
29 #include "fpu/softfloat-helpers.h"
30 #include "tcg/tcg.h"
31
superh_cpu_set_pc(CPUState * cs,vaddr value)32 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
33 {
34 SuperHCPU *cpu = SUPERH_CPU(cs);
35
36 cpu->env.pc = value;
37 }
38
superh_cpu_get_pc(CPUState * cs)39 static vaddr superh_cpu_get_pc(CPUState *cs)
40 {
41 SuperHCPU *cpu = SUPERH_CPU(cs);
42
43 return cpu->env.pc;
44 }
45
superh_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)46 static void superh_cpu_synchronize_from_tb(CPUState *cs,
47 const TranslationBlock *tb)
48 {
49 SuperHCPU *cpu = SUPERH_CPU(cs);
50
51 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
52 cpu->env.pc = tb->pc;
53 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
54 }
55
superh_restore_state_to_opc(CPUState * cs,const TranslationBlock * tb,const uint64_t * data)56 static void superh_restore_state_to_opc(CPUState *cs,
57 const TranslationBlock *tb,
58 const uint64_t *data)
59 {
60 SuperHCPU *cpu = SUPERH_CPU(cs);
61
62 cpu->env.pc = data[0];
63 cpu->env.flags = data[1];
64 /*
65 * Theoretically delayed_pc should also be restored. In practice the
66 * branch instruction is re-executed after exception, so the delayed
67 * branch target will be recomputed.
68 */
69 }
70
71 #ifndef CONFIG_USER_ONLY
superh_io_recompile_replay_branch(CPUState * cs,const TranslationBlock * tb)72 static bool superh_io_recompile_replay_branch(CPUState *cs,
73 const TranslationBlock *tb)
74 {
75 CPUSH4State *env = cpu_env(cs);
76
77 if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
78 && !tcg_cflags_has(cs, CF_PCREL) && env->pc != tb->pc) {
79 env->pc -= 2;
80 env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
81 return true;
82 }
83 return false;
84 }
85
superh_cpu_has_work(CPUState * cs)86 static bool superh_cpu_has_work(CPUState *cs)
87 {
88 return cs->interrupt_request & CPU_INTERRUPT_HARD;
89 }
90 #endif /* !CONFIG_USER_ONLY */
91
sh4_cpu_mmu_index(CPUState * cs,bool ifetch)92 static int sh4_cpu_mmu_index(CPUState *cs, bool ifetch)
93 {
94 CPUSH4State *env = cpu_env(cs);
95
96 /*
97 * The instruction in a RTE delay slot is fetched in privileged mode,
98 * but executed in user mode.
99 */
100 if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
101 return 0;
102 } else {
103 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
104 }
105 }
106
superh_cpu_reset_hold(Object * obj,ResetType type)107 static void superh_cpu_reset_hold(Object *obj, ResetType type)
108 {
109 CPUState *cs = CPU(obj);
110 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(obj);
111 CPUSH4State *env = cpu_env(cs);
112
113 if (scc->parent_phases.hold) {
114 scc->parent_phases.hold(obj, type);
115 }
116
117 memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
118
119 env->pc = 0xA0000000;
120 #if defined(CONFIG_USER_ONLY)
121 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
122 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
123 #else
124 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
125 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
126 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
127 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
128 set_flush_to_zero(1, &env->fp_status);
129 #endif
130 set_default_nan_mode(1, &env->fp_status);
131 set_snan_bit_is_one(true, &env->fp_status);
132 /* sign bit clear, set all frac bits other than msb */
133 set_float_default_nan_pattern(0b00111111, &env->fp_status);
134 /*
135 * TODO: "SH-4 CPU Core Architecture ADCS 7182230F" doesn't say whether
136 * it detects tininess before or after rounding. Section 6.4 is clear
137 * that flush-to-zero happens when the result underflows, though, so
138 * either this should be "detect ftz after rounding" or else we should
139 * be setting "detect tininess before rounding".
140 */
141 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status);
142 }
143
superh_cpu_disas_set_info(CPUState * cpu,disassemble_info * info)144 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
145 {
146 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
147 : BFD_ENDIAN_LITTLE;
148 info->mach = bfd_mach_sh4;
149 info->print_insn = print_insn_sh;
150 }
151
superh_cpu_class_by_name(const char * cpu_model)152 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
153 {
154 ObjectClass *oc;
155 char *s, *typename = NULL;
156
157 s = g_ascii_strdown(cpu_model, -1);
158 if (strcmp(s, "any") == 0) {
159 oc = object_class_by_name(TYPE_SH7750R_CPU);
160 goto out;
161 }
162
163 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
164 oc = object_class_by_name(typename);
165
166 out:
167 g_free(s);
168 g_free(typename);
169 return oc;
170 }
171
sh7750r_cpu_initfn(Object * obj)172 static void sh7750r_cpu_initfn(Object *obj)
173 {
174 CPUSH4State *env = cpu_env(CPU(obj));
175
176 env->id = SH_CPU_SH7750R;
177 env->features = SH_FEATURE_BCR3_AND_BCR4;
178 }
179
sh7750r_class_init(ObjectClass * oc,void * data)180 static void sh7750r_class_init(ObjectClass *oc, void *data)
181 {
182 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
183
184 scc->pvr = 0x00050000;
185 scc->prr = 0x00000100;
186 scc->cvr = 0x00110000;
187 }
188
sh7751r_cpu_initfn(Object * obj)189 static void sh7751r_cpu_initfn(Object *obj)
190 {
191 CPUSH4State *env = cpu_env(CPU(obj));
192
193 env->id = SH_CPU_SH7751R;
194 env->features = SH_FEATURE_BCR3_AND_BCR4;
195 }
196
sh7751r_class_init(ObjectClass * oc,void * data)197 static void sh7751r_class_init(ObjectClass *oc, void *data)
198 {
199 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
200
201 scc->pvr = 0x04050005;
202 scc->prr = 0x00000113;
203 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
204 }
205
sh7785_cpu_initfn(Object * obj)206 static void sh7785_cpu_initfn(Object *obj)
207 {
208 CPUSH4State *env = cpu_env(CPU(obj));
209
210 env->id = SH_CPU_SH7785;
211 env->features = SH_FEATURE_SH4A;
212 }
213
sh7785_class_init(ObjectClass * oc,void * data)214 static void sh7785_class_init(ObjectClass *oc, void *data)
215 {
216 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
217
218 scc->pvr = 0x10300700;
219 scc->prr = 0x00000200;
220 scc->cvr = 0x71440211;
221 }
222
superh_cpu_realizefn(DeviceState * dev,Error ** errp)223 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
224 {
225 CPUState *cs = CPU(dev);
226 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
227 Error *local_err = NULL;
228
229 cpu_exec_realizefn(cs, &local_err);
230 if (local_err != NULL) {
231 error_propagate(errp, local_err);
232 return;
233 }
234
235 cpu_reset(cs);
236 qemu_init_vcpu(cs);
237
238 scc->parent_realize(dev, errp);
239 }
240
superh_cpu_initfn(Object * obj)241 static void superh_cpu_initfn(Object *obj)
242 {
243 CPUSH4State *env = cpu_env(CPU(obj));
244
245 env->movcal_backup_tail = &(env->movcal_backup);
246 }
247
248 #ifndef CONFIG_USER_ONLY
249 static const VMStateDescription vmstate_sh_cpu = {
250 .name = "cpu",
251 .unmigratable = 1,
252 };
253
254 #include "hw/core/sysemu-cpu-ops.h"
255
256 static const struct SysemuCPUOps sh4_sysemu_ops = {
257 .has_work = superh_cpu_has_work,
258 .get_phys_page_debug = superh_cpu_get_phys_page_debug,
259 };
260 #endif
261
262 #include "accel/tcg/cpu-ops.h"
263
264 static const TCGCPUOps superh_tcg_ops = {
265 .initialize = sh4_translate_init,
266 .translate_code = sh4_translate_code,
267 .synchronize_from_tb = superh_cpu_synchronize_from_tb,
268 .restore_state_to_opc = superh_restore_state_to_opc,
269
270 #ifndef CONFIG_USER_ONLY
271 .tlb_fill = superh_cpu_tlb_fill,
272 .cpu_exec_interrupt = superh_cpu_exec_interrupt,
273 .cpu_exec_halt = superh_cpu_has_work,
274 .do_interrupt = superh_cpu_do_interrupt,
275 .do_unaligned_access = superh_cpu_do_unaligned_access,
276 .io_recompile_replay_branch = superh_io_recompile_replay_branch,
277 #endif /* !CONFIG_USER_ONLY */
278 };
279
superh_cpu_class_init(ObjectClass * oc,void * data)280 static void superh_cpu_class_init(ObjectClass *oc, void *data)
281 {
282 DeviceClass *dc = DEVICE_CLASS(oc);
283 CPUClass *cc = CPU_CLASS(oc);
284 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
285 ResettableClass *rc = RESETTABLE_CLASS(oc);
286
287 device_class_set_parent_realize(dc, superh_cpu_realizefn,
288 &scc->parent_realize);
289
290 resettable_class_set_parent_phases(rc, NULL, superh_cpu_reset_hold, NULL,
291 &scc->parent_phases);
292
293 cc->class_by_name = superh_cpu_class_by_name;
294 cc->mmu_index = sh4_cpu_mmu_index;
295 cc->dump_state = superh_cpu_dump_state;
296 cc->set_pc = superh_cpu_set_pc;
297 cc->get_pc = superh_cpu_get_pc;
298 cc->gdb_read_register = superh_cpu_gdb_read_register;
299 cc->gdb_write_register = superh_cpu_gdb_write_register;
300 #ifndef CONFIG_USER_ONLY
301 cc->sysemu_ops = &sh4_sysemu_ops;
302 dc->vmsd = &vmstate_sh_cpu;
303 #endif
304 cc->disas_set_info = superh_cpu_disas_set_info;
305
306 cc->gdb_num_core_regs = 59;
307 cc->tcg_ops = &superh_tcg_ops;
308 }
309
310 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
311 { \
312 .name = type_name, \
313 .parent = TYPE_SUPERH_CPU, \
314 .class_init = cinit, \
315 .instance_init = initfn, \
316 }
317 static const TypeInfo superh_cpu_type_infos[] = {
318 {
319 .name = TYPE_SUPERH_CPU,
320 .parent = TYPE_CPU,
321 .instance_size = sizeof(SuperHCPU),
322 .instance_align = __alignof(SuperHCPU),
323 .instance_init = superh_cpu_initfn,
324 .abstract = true,
325 .class_size = sizeof(SuperHCPUClass),
326 .class_init = superh_cpu_class_init,
327 },
328 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
329 sh7750r_cpu_initfn),
330 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
331 sh7751r_cpu_initfn),
332 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
333 sh7785_cpu_initfn),
334
335 };
336
337 DEFINE_TYPES(superh_cpu_type_infos)
338