Searched defs:sunxi_mctl_com_reg (Results 1 – 7 of 7) sorted by relevance
14 struct sunxi_mctl_com_reg { struct15 u32 cr; /* 0x00 */16 u32 ccr; /* 0x04 controller configuration register */17 u32 dbgcr; /* 0x08 */18 u8 res0[0x4]; /* 0x0c */19 u32 mcr0_0; /* 0x10 */20 u32 mcr1_0; /* 0x14 */21 u32 mcr0_1; /* 0x18 */22 u32 mcr1_1; /* 0x1c */23 u32 mcr0_2; /* 0x20 */[all …]
44 struct sunxi_mctl_com_reg { struct45 u32 cr; /* 0x00 */46 u32 ccr; /* 0x04 controller configuration register */47 u32 dbgcr; /* 0x08 */48 u8 res0[0x4]; /* 0x0c */49 u32 mcr0_0; /* 0x10 */50 u32 mcr1_0; /* 0x14 */51 u32 mcr0_1; /* 0x18 */52 u32 mcr1_1; /* 0x1c */53 u32 mcr0_2; /* 0x20 */[all …]
17 struct sunxi_mctl_com_reg { struct18 u32 cr; /* 0x00 control register */19 u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */20 u8 res0[0x4]; /* 0x08 */21 u32 tmr; /* 0x0c (unused on H3) */22 u32 mcr[16][2]; /* 0x10 */23 u32 bwcr; /* 0x90 bandwidth control register */24 u32 maer; /* 0x94 master enable register */25 u32 mapr; /* 0x98 master priority register */26 u32 mcgcr; /* 0x9c */[all …]
14 struct sunxi_mctl_com_reg { struct15 u32 cr; /* 0x00 */16 u32 ccr; /* 0x04 controller configuration register */17 u32 dbgcr; /* 0x08 */18 u32 dbgcr1; /* 0x0c */19 u32 rmcr; /* 0x10 */20 u8 res1[0x1c]; /* 0x14 */21 u32 mmcr; /* 0x30 */22 u8 res2[0x3c]; /* 0x34 */23 u32 mbagcr; /* 0x70 */[all …]
23 struct sunxi_mctl_com_reg { struct47 check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498); argument
16 struct sunxi_mctl_com_reg { struct17 u32 cr; /* 0x00 */18 u32 ccr; /* 0x04 controller configuration register */19 u32 dbgcr; /* 0x08 */20 u32 dbgcr1; /* 0x0c */21 u32 rmcr[8]; /* 0x10 */22 u32 mmcr[16]; /* 0x30 */23 u32 mbagcr[6]; /* 0x70 */24 u32 maer; /* 0x88 */25 u8 res0[0x14]; /* 0x8c */[all …]